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stm32-moto/Debug/moto-perf.list

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moto-perf.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000194 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 000054a8 080001a0 080001a0 000011a0 2**4
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 000003b4 08005648 08005648 00006648 2**3
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 080059fc 080059fc 000071d4 2**0
CONTENTS, READONLY
4 .ARM 00000008 080059fc 080059fc 000069fc 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08005a04 08005a04 000071d4 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08005a04 08005a04 00006a04 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08005a08 08005a08 00006a08 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 000001d4 20000000 08005a0c 00007000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000005d8 200001d4 08005be0 000071d4 2**2
ALLOC
10 ._user_heap_stack 00000c04 200007ac 08005be0 000077ac 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 000071d4 2**0
CONTENTS, READONLY
12 .debug_info 000089d6 00000000 00000000 00007204 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00001987 00000000 00000000 0000fbda 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000940 00000000 00000000 00011568 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 000006ef 00000000 00000000 00011ea8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 000219d8 00000000 00000000 00012597 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 0000a22c 00000000 00000000 00033f6f 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000d370a 00000000 00000000 0003e19b 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 001118a5 2**0
CONTENTS, READONLY
20 .debug_frame 00003420 00000000 00000000 001118e8 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000063 00000000 00000000 00114d08 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001a0 <__do_global_dtors_aux>:
80001a0: b510 push {r4, lr}
80001a2: 4c05 ldr r4, [pc, #20] @ (80001b8 <__do_global_dtors_aux+0x18>)
80001a4: 7823 ldrb r3, [r4, #0]
80001a6: b933 cbnz r3, 80001b6 <__do_global_dtors_aux+0x16>
80001a8: 4b04 ldr r3, [pc, #16] @ (80001bc <__do_global_dtors_aux+0x1c>)
80001aa: b113 cbz r3, 80001b2 <__do_global_dtors_aux+0x12>
80001ac: 4804 ldr r0, [pc, #16] @ (80001c0 <__do_global_dtors_aux+0x20>)
80001ae: f3af 8000 nop.w
80001b2: 2301 movs r3, #1
80001b4: 7023 strb r3, [r4, #0]
80001b6: bd10 pop {r4, pc}
80001b8: 200001d4 .word 0x200001d4
80001bc: 00000000 .word 0x00000000
80001c0: 08005630 .word 0x08005630
080001c4 <frame_dummy>:
80001c4: b508 push {r3, lr}
80001c6: 4b03 ldr r3, [pc, #12] @ (80001d4 <frame_dummy+0x10>)
80001c8: b11b cbz r3, 80001d2 <frame_dummy+0xe>
80001ca: 4903 ldr r1, [pc, #12] @ (80001d8 <frame_dummy+0x14>)
80001cc: 4803 ldr r0, [pc, #12] @ (80001dc <frame_dummy+0x18>)
80001ce: f3af 8000 nop.w
80001d2: bd08 pop {r3, pc}
80001d4: 00000000 .word 0x00000000
80001d8: 200001d8 .word 0x200001d8
80001dc: 08005630 .word 0x08005630
080001e0 <memchr>:
80001e0: f001 01ff and.w r1, r1, #255 @ 0xff
80001e4: 2a10 cmp r2, #16
80001e6: db2b blt.n 8000240 <memchr+0x60>
80001e8: f010 0f07 tst.w r0, #7
80001ec: d008 beq.n 8000200 <memchr+0x20>
80001ee: f810 3b01 ldrb.w r3, [r0], #1
80001f2: 3a01 subs r2, #1
80001f4: 428b cmp r3, r1
80001f6: d02d beq.n 8000254 <memchr+0x74>
80001f8: f010 0f07 tst.w r0, #7
80001fc: b342 cbz r2, 8000250 <memchr+0x70>
80001fe: d1f6 bne.n 80001ee <memchr+0xe>
8000200: b4f0 push {r4, r5, r6, r7}
8000202: ea41 2101 orr.w r1, r1, r1, lsl #8
8000206: ea41 4101 orr.w r1, r1, r1, lsl #16
800020a: f022 0407 bic.w r4, r2, #7
800020e: f07f 0700 mvns.w r7, #0
8000212: 2300 movs r3, #0
8000214: e8f0 5602 ldrd r5, r6, [r0], #8
8000218: 3c08 subs r4, #8
800021a: ea85 0501 eor.w r5, r5, r1
800021e: ea86 0601 eor.w r6, r6, r1
8000222: fa85 f547 uadd8 r5, r5, r7
8000226: faa3 f587 sel r5, r3, r7
800022a: fa86 f647 uadd8 r6, r6, r7
800022e: faa5 f687 sel r6, r5, r7
8000232: b98e cbnz r6, 8000258 <memchr+0x78>
8000234: d1ee bne.n 8000214 <memchr+0x34>
8000236: bcf0 pop {r4, r5, r6, r7}
8000238: f001 01ff and.w r1, r1, #255 @ 0xff
800023c: f002 0207 and.w r2, r2, #7
8000240: b132 cbz r2, 8000250 <memchr+0x70>
8000242: f810 3b01 ldrb.w r3, [r0], #1
8000246: 3a01 subs r2, #1
8000248: ea83 0301 eor.w r3, r3, r1
800024c: b113 cbz r3, 8000254 <memchr+0x74>
800024e: d1f8 bne.n 8000242 <memchr+0x62>
8000250: 2000 movs r0, #0
8000252: 4770 bx lr
8000254: 3801 subs r0, #1
8000256: 4770 bx lr
8000258: 2d00 cmp r5, #0
800025a: bf06 itte eq
800025c: 4635 moveq r5, r6
800025e: 3803 subeq r0, #3
8000260: 3807 subne r0, #7
8000262: f015 0f01 tst.w r5, #1
8000266: d107 bne.n 8000278 <memchr+0x98>
8000268: 3001 adds r0, #1
800026a: f415 7f80 tst.w r5, #256 @ 0x100
800026e: bf02 ittt eq
8000270: 3001 addeq r0, #1
8000272: f415 3fc0 tsteq.w r5, #98304 @ 0x18000
8000276: 3001 addeq r0, #1
8000278: bcf0 pop {r4, r5, r6, r7}
800027a: 3801 subs r0, #1
800027c: 4770 bx lr
800027e: bf00 nop
08000280 <strlen>:
8000280: 4603 mov r3, r0
8000282: f813 2b01 ldrb.w r2, [r3], #1
8000286: 2a00 cmp r2, #0
8000288: d1fb bne.n 8000282 <strlen+0x2>
800028a: 1a18 subs r0, r3, r0
800028c: 3801 subs r0, #1
800028e: 4770 bx lr
08000290 <__aeabi_drsub>:
8000290: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
8000294: e002 b.n 800029c <__adddf3>
8000296: bf00 nop
08000298 <__aeabi_dsub>:
8000298: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000
0800029c <__adddf3>:
800029c: b530 push {r4, r5, lr}
800029e: ea4f 0441 mov.w r4, r1, lsl #1
80002a2: ea4f 0543 mov.w r5, r3, lsl #1
80002a6: ea94 0f05 teq r4, r5
80002aa: bf08 it eq
80002ac: ea90 0f02 teqeq r0, r2
80002b0: bf1f itttt ne
80002b2: ea54 0c00 orrsne.w ip, r4, r0
80002b6: ea55 0c02 orrsne.w ip, r5, r2
80002ba: ea7f 5c64 mvnsne.w ip, r4, asr #21
80002be: ea7f 5c65 mvnsne.w ip, r5, asr #21
80002c2: f000 80e2 beq.w 800048a <__adddf3+0x1ee>
80002c6: ea4f 5454 mov.w r4, r4, lsr #21
80002ca: ebd4 5555 rsbs r5, r4, r5, lsr #21
80002ce: bfb8 it lt
80002d0: 426d neglt r5, r5
80002d2: dd0c ble.n 80002ee <__adddf3+0x52>
80002d4: 442c add r4, r5
80002d6: ea80 0202 eor.w r2, r0, r2
80002da: ea81 0303 eor.w r3, r1, r3
80002de: ea82 0000 eor.w r0, r2, r0
80002e2: ea83 0101 eor.w r1, r3, r1
80002e6: ea80 0202 eor.w r2, r0, r2
80002ea: ea81 0303 eor.w r3, r1, r3
80002ee: 2d36 cmp r5, #54 @ 0x36
80002f0: bf88 it hi
80002f2: bd30 pophi {r4, r5, pc}
80002f4: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
80002f8: ea4f 3101 mov.w r1, r1, lsl #12
80002fc: f44f 1c80 mov.w ip, #1048576 @ 0x100000
8000300: ea4c 3111 orr.w r1, ip, r1, lsr #12
8000304: d002 beq.n 800030c <__adddf3+0x70>
8000306: 4240 negs r0, r0
8000308: eb61 0141 sbc.w r1, r1, r1, lsl #1
800030c: f013 4f00 tst.w r3, #2147483648 @ 0x80000000
8000310: ea4f 3303 mov.w r3, r3, lsl #12
8000314: ea4c 3313 orr.w r3, ip, r3, lsr #12
8000318: d002 beq.n 8000320 <__adddf3+0x84>
800031a: 4252 negs r2, r2
800031c: eb63 0343 sbc.w r3, r3, r3, lsl #1
8000320: ea94 0f05 teq r4, r5
8000324: f000 80a7 beq.w 8000476 <__adddf3+0x1da>
8000328: f1a4 0401 sub.w r4, r4, #1
800032c: f1d5 0e20 rsbs lr, r5, #32
8000330: db0d blt.n 800034e <__adddf3+0xb2>
8000332: fa02 fc0e lsl.w ip, r2, lr
8000336: fa22 f205 lsr.w r2, r2, r5
800033a: 1880 adds r0, r0, r2
800033c: f141 0100 adc.w r1, r1, #0
8000340: fa03 f20e lsl.w r2, r3, lr
8000344: 1880 adds r0, r0, r2
8000346: fa43 f305 asr.w r3, r3, r5
800034a: 4159 adcs r1, r3
800034c: e00e b.n 800036c <__adddf3+0xd0>
800034e: f1a5 0520 sub.w r5, r5, #32
8000352: f10e 0e20 add.w lr, lr, #32
8000356: 2a01 cmp r2, #1
8000358: fa03 fc0e lsl.w ip, r3, lr
800035c: bf28 it cs
800035e: f04c 0c02 orrcs.w ip, ip, #2
8000362: fa43 f305 asr.w r3, r3, r5
8000366: 18c0 adds r0, r0, r3
8000368: eb51 71e3 adcs.w r1, r1, r3, asr #31
800036c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
8000370: d507 bpl.n 8000382 <__adddf3+0xe6>
8000372: f04f 0e00 mov.w lr, #0
8000376: f1dc 0c00 rsbs ip, ip, #0
800037a: eb7e 0000 sbcs.w r0, lr, r0
800037e: eb6e 0101 sbc.w r1, lr, r1
8000382: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
8000386: d31b bcc.n 80003c0 <__adddf3+0x124>
8000388: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
800038c: d30c bcc.n 80003a8 <__adddf3+0x10c>
800038e: 0849 lsrs r1, r1, #1
8000390: ea5f 0030 movs.w r0, r0, rrx
8000394: ea4f 0c3c mov.w ip, ip, rrx
8000398: f104 0401 add.w r4, r4, #1
800039c: ea4f 5244 mov.w r2, r4, lsl #21
80003a0: f512 0f80 cmn.w r2, #4194304 @ 0x400000
80003a4: f080 809a bcs.w 80004dc <__adddf3+0x240>
80003a8: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
80003ac: bf08 it eq
80003ae: ea5f 0c50 movseq.w ip, r0, lsr #1
80003b2: f150 0000 adcs.w r0, r0, #0
80003b6: eb41 5104 adc.w r1, r1, r4, lsl #20
80003ba: ea41 0105 orr.w r1, r1, r5
80003be: bd30 pop {r4, r5, pc}
80003c0: ea5f 0c4c movs.w ip, ip, lsl #1
80003c4: 4140 adcs r0, r0
80003c6: eb41 0101 adc.w r1, r1, r1
80003ca: 3c01 subs r4, #1
80003cc: bf28 it cs
80003ce: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000
80003d2: d2e9 bcs.n 80003a8 <__adddf3+0x10c>
80003d4: f091 0f00 teq r1, #0
80003d8: bf04 itt eq
80003da: 4601 moveq r1, r0
80003dc: 2000 moveq r0, #0
80003de: fab1 f381 clz r3, r1
80003e2: bf08 it eq
80003e4: 3320 addeq r3, #32
80003e6: f1a3 030b sub.w r3, r3, #11
80003ea: f1b3 0220 subs.w r2, r3, #32
80003ee: da0c bge.n 800040a <__adddf3+0x16e>
80003f0: 320c adds r2, #12
80003f2: dd08 ble.n 8000406 <__adddf3+0x16a>
80003f4: f102 0c14 add.w ip, r2, #20
80003f8: f1c2 020c rsb r2, r2, #12
80003fc: fa01 f00c lsl.w r0, r1, ip
8000400: fa21 f102 lsr.w r1, r1, r2
8000404: e00c b.n 8000420 <__adddf3+0x184>
8000406: f102 0214 add.w r2, r2, #20
800040a: bfd8 it le
800040c: f1c2 0c20 rsble ip, r2, #32
8000410: fa01 f102 lsl.w r1, r1, r2
8000414: fa20 fc0c lsr.w ip, r0, ip
8000418: bfdc itt le
800041a: ea41 010c orrle.w r1, r1, ip
800041e: 4090 lslle r0, r2
8000420: 1ae4 subs r4, r4, r3
8000422: bfa2 ittt ge
8000424: eb01 5104 addge.w r1, r1, r4, lsl #20
8000428: 4329 orrge r1, r5
800042a: bd30 popge {r4, r5, pc}
800042c: ea6f 0404 mvn.w r4, r4
8000430: 3c1f subs r4, #31
8000432: da1c bge.n 800046e <__adddf3+0x1d2>
8000434: 340c adds r4, #12
8000436: dc0e bgt.n 8000456 <__adddf3+0x1ba>
8000438: f104 0414 add.w r4, r4, #20
800043c: f1c4 0220 rsb r2, r4, #32
8000440: fa20 f004 lsr.w r0, r0, r4
8000444: fa01 f302 lsl.w r3, r1, r2
8000448: ea40 0003 orr.w r0, r0, r3
800044c: fa21 f304 lsr.w r3, r1, r4
8000450: ea45 0103 orr.w r1, r5, r3
8000454: bd30 pop {r4, r5, pc}
8000456: f1c4 040c rsb r4, r4, #12
800045a: f1c4 0220 rsb r2, r4, #32
800045e: fa20 f002 lsr.w r0, r0, r2
8000462: fa01 f304 lsl.w r3, r1, r4
8000466: ea40 0003 orr.w r0, r0, r3
800046a: 4629 mov r1, r5
800046c: bd30 pop {r4, r5, pc}
800046e: fa21 f004 lsr.w r0, r1, r4
8000472: 4629 mov r1, r5
8000474: bd30 pop {r4, r5, pc}
8000476: f094 0f00 teq r4, #0
800047a: f483 1380 eor.w r3, r3, #1048576 @ 0x100000
800047e: bf06 itte eq
8000480: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000
8000484: 3401 addeq r4, #1
8000486: 3d01 subne r5, #1
8000488: e74e b.n 8000328 <__adddf3+0x8c>
800048a: ea7f 5c64 mvns.w ip, r4, asr #21
800048e: bf18 it ne
8000490: ea7f 5c65 mvnsne.w ip, r5, asr #21
8000494: d029 beq.n 80004ea <__adddf3+0x24e>
8000496: ea94 0f05 teq r4, r5
800049a: bf08 it eq
800049c: ea90 0f02 teqeq r0, r2
80004a0: d005 beq.n 80004ae <__adddf3+0x212>
80004a2: ea54 0c00 orrs.w ip, r4, r0
80004a6: bf04 itt eq
80004a8: 4619 moveq r1, r3
80004aa: 4610 moveq r0, r2
80004ac: bd30 pop {r4, r5, pc}
80004ae: ea91 0f03 teq r1, r3
80004b2: bf1e ittt ne
80004b4: 2100 movne r1, #0
80004b6: 2000 movne r0, #0
80004b8: bd30 popne {r4, r5, pc}
80004ba: ea5f 5c54 movs.w ip, r4, lsr #21
80004be: d105 bne.n 80004cc <__adddf3+0x230>
80004c0: 0040 lsls r0, r0, #1
80004c2: 4149 adcs r1, r1
80004c4: bf28 it cs
80004c6: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000
80004ca: bd30 pop {r4, r5, pc}
80004cc: f514 0480 adds.w r4, r4, #4194304 @ 0x400000
80004d0: bf3c itt cc
80004d2: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000
80004d6: bd30 popcc {r4, r5, pc}
80004d8: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
80004dc: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000
80004e0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
80004e4: f04f 0000 mov.w r0, #0
80004e8: bd30 pop {r4, r5, pc}
80004ea: ea7f 5c64 mvns.w ip, r4, asr #21
80004ee: bf1a itte ne
80004f0: 4619 movne r1, r3
80004f2: 4610 movne r0, r2
80004f4: ea7f 5c65 mvnseq.w ip, r5, asr #21
80004f8: bf1c itt ne
80004fa: 460b movne r3, r1
80004fc: 4602 movne r2, r0
80004fe: ea50 3401 orrs.w r4, r0, r1, lsl #12
8000502: bf06 itte eq
8000504: ea52 3503 orrseq.w r5, r2, r3, lsl #12
8000508: ea91 0f03 teqeq r1, r3
800050c: f441 2100 orrne.w r1, r1, #524288 @ 0x80000
8000510: bd30 pop {r4, r5, pc}
8000512: bf00 nop
08000514 <__aeabi_ui2d>:
8000514: f090 0f00 teq r0, #0
8000518: bf04 itt eq
800051a: 2100 moveq r1, #0
800051c: 4770 bxeq lr
800051e: b530 push {r4, r5, lr}
8000520: f44f 6480 mov.w r4, #1024 @ 0x400
8000524: f104 0432 add.w r4, r4, #50 @ 0x32
8000528: f04f 0500 mov.w r5, #0
800052c: f04f 0100 mov.w r1, #0
8000530: e750 b.n 80003d4 <__adddf3+0x138>
8000532: bf00 nop
08000534 <__aeabi_i2d>:
8000534: f090 0f00 teq r0, #0
8000538: bf04 itt eq
800053a: 2100 moveq r1, #0
800053c: 4770 bxeq lr
800053e: b530 push {r4, r5, lr}
8000540: f44f 6480 mov.w r4, #1024 @ 0x400
8000544: f104 0432 add.w r4, r4, #50 @ 0x32
8000548: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000
800054c: bf48 it mi
800054e: 4240 negmi r0, r0
8000550: f04f 0100 mov.w r1, #0
8000554: e73e b.n 80003d4 <__adddf3+0x138>
8000556: bf00 nop
08000558 <__aeabi_f2d>:
8000558: 0042 lsls r2, r0, #1
800055a: ea4f 01e2 mov.w r1, r2, asr #3
800055e: ea4f 0131 mov.w r1, r1, rrx
8000562: ea4f 7002 mov.w r0, r2, lsl #28
8000566: bf1f itttt ne
8000568: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000
800056c: f093 4f7f teqne r3, #4278190080 @ 0xff000000
8000570: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000
8000574: 4770 bxne lr
8000576: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000
800057a: bf08 it eq
800057c: 4770 bxeq lr
800057e: f093 4f7f teq r3, #4278190080 @ 0xff000000
8000582: bf04 itt eq
8000584: f441 2100 orreq.w r1, r1, #524288 @ 0x80000
8000588: 4770 bxeq lr
800058a: b530 push {r4, r5, lr}
800058c: f44f 7460 mov.w r4, #896 @ 0x380
8000590: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
8000594: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
8000598: e71c b.n 80003d4 <__adddf3+0x138>
800059a: bf00 nop
0800059c <__aeabi_ul2d>:
800059c: ea50 0201 orrs.w r2, r0, r1
80005a0: bf08 it eq
80005a2: 4770 bxeq lr
80005a4: b530 push {r4, r5, lr}
80005a6: f04f 0500 mov.w r5, #0
80005aa: e00a b.n 80005c2 <__aeabi_l2d+0x16>
080005ac <__aeabi_l2d>:
80005ac: ea50 0201 orrs.w r2, r0, r1
80005b0: bf08 it eq
80005b2: 4770 bxeq lr
80005b4: b530 push {r4, r5, lr}
80005b6: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000
80005ba: d502 bpl.n 80005c2 <__aeabi_l2d+0x16>
80005bc: 4240 negs r0, r0
80005be: eb61 0141 sbc.w r1, r1, r1, lsl #1
80005c2: f44f 6480 mov.w r4, #1024 @ 0x400
80005c6: f104 0432 add.w r4, r4, #50 @ 0x32
80005ca: ea5f 5c91 movs.w ip, r1, lsr #22
80005ce: f43f aed8 beq.w 8000382 <__adddf3+0xe6>
80005d2: f04f 0203 mov.w r2, #3
80005d6: ea5f 0cdc movs.w ip, ip, lsr #3
80005da: bf18 it ne
80005dc: 3203 addne r2, #3
80005de: ea5f 0cdc movs.w ip, ip, lsr #3
80005e2: bf18 it ne
80005e4: 3203 addne r2, #3
80005e6: eb02 02dc add.w r2, r2, ip, lsr #3
80005ea: f1c2 0320 rsb r3, r2, #32
80005ee: fa00 fc03 lsl.w ip, r0, r3
80005f2: fa20 f002 lsr.w r0, r0, r2
80005f6: fa01 fe03 lsl.w lr, r1, r3
80005fa: ea40 000e orr.w r0, r0, lr
80005fe: fa21 f102 lsr.w r1, r1, r2
8000602: 4414 add r4, r2
8000604: e6bd b.n 8000382 <__adddf3+0xe6>
8000606: bf00 nop
08000608 <__aeabi_dmul>:
8000608: b570 push {r4, r5, r6, lr}
800060a: f04f 0cff mov.w ip, #255 @ 0xff
800060e: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
8000612: ea1c 5411 ands.w r4, ip, r1, lsr #20
8000616: bf1d ittte ne
8000618: ea1c 5513 andsne.w r5, ip, r3, lsr #20
800061c: ea94 0f0c teqne r4, ip
8000620: ea95 0f0c teqne r5, ip
8000624: f000 f8de bleq 80007e4 <__aeabi_dmul+0x1dc>
8000628: 442c add r4, r5
800062a: ea81 0603 eor.w r6, r1, r3
800062e: ea21 514c bic.w r1, r1, ip, lsl #21
8000632: ea23 534c bic.w r3, r3, ip, lsl #21
8000636: ea50 3501 orrs.w r5, r0, r1, lsl #12
800063a: bf18 it ne
800063c: ea52 3503 orrsne.w r5, r2, r3, lsl #12
8000640: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
8000644: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8000648: d038 beq.n 80006bc <__aeabi_dmul+0xb4>
800064a: fba0 ce02 umull ip, lr, r0, r2
800064e: f04f 0500 mov.w r5, #0
8000652: fbe1 e502 umlal lr, r5, r1, r2
8000656: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000
800065a: fbe0 e503 umlal lr, r5, r0, r3
800065e: f04f 0600 mov.w r6, #0
8000662: fbe1 5603 umlal r5, r6, r1, r3
8000666: f09c 0f00 teq ip, #0
800066a: bf18 it ne
800066c: f04e 0e01 orrne.w lr, lr, #1
8000670: f1a4 04ff sub.w r4, r4, #255 @ 0xff
8000674: f5b6 7f00 cmp.w r6, #512 @ 0x200
8000678: f564 7440 sbc.w r4, r4, #768 @ 0x300
800067c: d204 bcs.n 8000688 <__aeabi_dmul+0x80>
800067e: ea5f 0e4e movs.w lr, lr, lsl #1
8000682: 416d adcs r5, r5
8000684: eb46 0606 adc.w r6, r6, r6
8000688: ea42 21c6 orr.w r1, r2, r6, lsl #11
800068c: ea41 5155 orr.w r1, r1, r5, lsr #21
8000690: ea4f 20c5 mov.w r0, r5, lsl #11
8000694: ea40 505e orr.w r0, r0, lr, lsr #21
8000698: ea4f 2ece mov.w lr, lr, lsl #11
800069c: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
80006a0: bf88 it hi
80006a2: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
80006a6: d81e bhi.n 80006e6 <__aeabi_dmul+0xde>
80006a8: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000
80006ac: bf08 it eq
80006ae: ea5f 0e50 movseq.w lr, r0, lsr #1
80006b2: f150 0000 adcs.w r0, r0, #0
80006b6: eb41 5104 adc.w r1, r1, r4, lsl #20
80006ba: bd70 pop {r4, r5, r6, pc}
80006bc: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000
80006c0: ea46 0101 orr.w r1, r6, r1
80006c4: ea40 0002 orr.w r0, r0, r2
80006c8: ea81 0103 eor.w r1, r1, r3
80006cc: ebb4 045c subs.w r4, r4, ip, lsr #1
80006d0: bfc2 ittt gt
80006d2: ebd4 050c rsbsgt r5, r4, ip
80006d6: ea41 5104 orrgt.w r1, r1, r4, lsl #20
80006da: bd70 popgt {r4, r5, r6, pc}
80006dc: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
80006e0: f04f 0e00 mov.w lr, #0
80006e4: 3c01 subs r4, #1
80006e6: f300 80ab bgt.w 8000840 <__aeabi_dmul+0x238>
80006ea: f114 0f36 cmn.w r4, #54 @ 0x36
80006ee: bfde ittt le
80006f0: 2000 movle r0, #0
80006f2: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000
80006f6: bd70 pople {r4, r5, r6, pc}
80006f8: f1c4 0400 rsb r4, r4, #0
80006fc: 3c20 subs r4, #32
80006fe: da35 bge.n 800076c <__aeabi_dmul+0x164>
8000700: 340c adds r4, #12
8000702: dc1b bgt.n 800073c <__aeabi_dmul+0x134>
8000704: f104 0414 add.w r4, r4, #20
8000708: f1c4 0520 rsb r5, r4, #32
800070c: fa00 f305 lsl.w r3, r0, r5
8000710: fa20 f004 lsr.w r0, r0, r4
8000714: fa01 f205 lsl.w r2, r1, r5
8000718: ea40 0002 orr.w r0, r0, r2
800071c: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000
8000720: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
8000724: eb10 70d3 adds.w r0, r0, r3, lsr #31
8000728: fa21 f604 lsr.w r6, r1, r4
800072c: eb42 0106 adc.w r1, r2, r6
8000730: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
8000734: bf08 it eq
8000736: ea20 70d3 biceq.w r0, r0, r3, lsr #31
800073a: bd70 pop {r4, r5, r6, pc}
800073c: f1c4 040c rsb r4, r4, #12
8000740: f1c4 0520 rsb r5, r4, #32
8000744: fa00 f304 lsl.w r3, r0, r4
8000748: fa20 f005 lsr.w r0, r0, r5
800074c: fa01 f204 lsl.w r2, r1, r4
8000750: ea40 0002 orr.w r0, r0, r2
8000754: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000758: eb10 70d3 adds.w r0, r0, r3, lsr #31
800075c: f141 0100 adc.w r1, r1, #0
8000760: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
8000764: bf08 it eq
8000766: ea20 70d3 biceq.w r0, r0, r3, lsr #31
800076a: bd70 pop {r4, r5, r6, pc}
800076c: f1c4 0520 rsb r5, r4, #32
8000770: fa00 f205 lsl.w r2, r0, r5
8000774: ea4e 0e02 orr.w lr, lr, r2
8000778: fa20 f304 lsr.w r3, r0, r4
800077c: fa01 f205 lsl.w r2, r1, r5
8000780: ea43 0302 orr.w r3, r3, r2
8000784: fa21 f004 lsr.w r0, r1, r4
8000788: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
800078c: fa21 f204 lsr.w r2, r1, r4
8000790: ea20 0002 bic.w r0, r0, r2
8000794: eb00 70d3 add.w r0, r0, r3, lsr #31
8000798: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
800079c: bf08 it eq
800079e: ea20 70d3 biceq.w r0, r0, r3, lsr #31
80007a2: bd70 pop {r4, r5, r6, pc}
80007a4: f094 0f00 teq r4, #0
80007a8: d10f bne.n 80007ca <__aeabi_dmul+0x1c2>
80007aa: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000
80007ae: 0040 lsls r0, r0, #1
80007b0: eb41 0101 adc.w r1, r1, r1
80007b4: f411 1f80 tst.w r1, #1048576 @ 0x100000
80007b8: bf08 it eq
80007ba: 3c01 subeq r4, #1
80007bc: d0f7 beq.n 80007ae <__aeabi_dmul+0x1a6>
80007be: ea41 0106 orr.w r1, r1, r6
80007c2: f095 0f00 teq r5, #0
80007c6: bf18 it ne
80007c8: 4770 bxne lr
80007ca: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000
80007ce: 0052 lsls r2, r2, #1
80007d0: eb43 0303 adc.w r3, r3, r3
80007d4: f413 1f80 tst.w r3, #1048576 @ 0x100000
80007d8: bf08 it eq
80007da: 3d01 subeq r5, #1
80007dc: d0f7 beq.n 80007ce <__aeabi_dmul+0x1c6>
80007de: ea43 0306 orr.w r3, r3, r6
80007e2: 4770 bx lr
80007e4: ea94 0f0c teq r4, ip
80007e8: ea0c 5513 and.w r5, ip, r3, lsr #20
80007ec: bf18 it ne
80007ee: ea95 0f0c teqne r5, ip
80007f2: d00c beq.n 800080e <__aeabi_dmul+0x206>
80007f4: ea50 0641 orrs.w r6, r0, r1, lsl #1
80007f8: bf18 it ne
80007fa: ea52 0643 orrsne.w r6, r2, r3, lsl #1
80007fe: d1d1 bne.n 80007a4 <__aeabi_dmul+0x19c>
8000800: ea81 0103 eor.w r1, r1, r3
8000804: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000808: f04f 0000 mov.w r0, #0
800080c: bd70 pop {r4, r5, r6, pc}
800080e: ea50 0641 orrs.w r6, r0, r1, lsl #1
8000812: bf06 itte eq
8000814: 4610 moveq r0, r2
8000816: 4619 moveq r1, r3
8000818: ea52 0643 orrsne.w r6, r2, r3, lsl #1
800081c: d019 beq.n 8000852 <__aeabi_dmul+0x24a>
800081e: ea94 0f0c teq r4, ip
8000822: d102 bne.n 800082a <__aeabi_dmul+0x222>
8000824: ea50 3601 orrs.w r6, r0, r1, lsl #12
8000828: d113 bne.n 8000852 <__aeabi_dmul+0x24a>
800082a: ea95 0f0c teq r5, ip
800082e: d105 bne.n 800083c <__aeabi_dmul+0x234>
8000830: ea52 3603 orrs.w r6, r2, r3, lsl #12
8000834: bf1c itt ne
8000836: 4610 movne r0, r2
8000838: 4619 movne r1, r3
800083a: d10a bne.n 8000852 <__aeabi_dmul+0x24a>
800083c: ea81 0103 eor.w r1, r1, r3
8000840: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000844: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
8000848: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
800084c: f04f 0000 mov.w r0, #0
8000850: bd70 pop {r4, r5, r6, pc}
8000852: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
8000856: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000
800085a: bd70 pop {r4, r5, r6, pc}
0800085c <__aeabi_ddiv>:
800085c: b570 push {r4, r5, r6, lr}
800085e: f04f 0cff mov.w ip, #255 @ 0xff
8000862: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
8000866: ea1c 5411 ands.w r4, ip, r1, lsr #20
800086a: bf1d ittte ne
800086c: ea1c 5513 andsne.w r5, ip, r3, lsr #20
8000870: ea94 0f0c teqne r4, ip
8000874: ea95 0f0c teqne r5, ip
8000878: f000 f8a7 bleq 80009ca <__aeabi_ddiv+0x16e>
800087c: eba4 0405 sub.w r4, r4, r5
8000880: ea81 0e03 eor.w lr, r1, r3
8000884: ea52 3503 orrs.w r5, r2, r3, lsl #12
8000888: ea4f 3101 mov.w r1, r1, lsl #12
800088c: f000 8088 beq.w 80009a0 <__aeabi_ddiv+0x144>
8000890: ea4f 3303 mov.w r3, r3, lsl #12
8000894: f04f 5580 mov.w r5, #268435456 @ 0x10000000
8000898: ea45 1313 orr.w r3, r5, r3, lsr #4
800089c: ea43 6312 orr.w r3, r3, r2, lsr #24
80008a0: ea4f 2202 mov.w r2, r2, lsl #8
80008a4: ea45 1511 orr.w r5, r5, r1, lsr #4
80008a8: ea45 6510 orr.w r5, r5, r0, lsr #24
80008ac: ea4f 2600 mov.w r6, r0, lsl #8
80008b0: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000
80008b4: 429d cmp r5, r3
80008b6: bf08 it eq
80008b8: 4296 cmpeq r6, r2
80008ba: f144 04fd adc.w r4, r4, #253 @ 0xfd
80008be: f504 7440 add.w r4, r4, #768 @ 0x300
80008c2: d202 bcs.n 80008ca <__aeabi_ddiv+0x6e>
80008c4: 085b lsrs r3, r3, #1
80008c6: ea4f 0232 mov.w r2, r2, rrx
80008ca: 1ab6 subs r6, r6, r2
80008cc: eb65 0503 sbc.w r5, r5, r3
80008d0: 085b lsrs r3, r3, #1
80008d2: ea4f 0232 mov.w r2, r2, rrx
80008d6: f44f 1080 mov.w r0, #1048576 @ 0x100000
80008da: f44f 2c00 mov.w ip, #524288 @ 0x80000
80008de: ebb6 0e02 subs.w lr, r6, r2
80008e2: eb75 0e03 sbcs.w lr, r5, r3
80008e6: bf22 ittt cs
80008e8: 1ab6 subcs r6, r6, r2
80008ea: 4675 movcs r5, lr
80008ec: ea40 000c orrcs.w r0, r0, ip
80008f0: 085b lsrs r3, r3, #1
80008f2: ea4f 0232 mov.w r2, r2, rrx
80008f6: ebb6 0e02 subs.w lr, r6, r2
80008fa: eb75 0e03 sbcs.w lr, r5, r3
80008fe: bf22 ittt cs
8000900: 1ab6 subcs r6, r6, r2
8000902: 4675 movcs r5, lr
8000904: ea40 005c orrcs.w r0, r0, ip, lsr #1
8000908: 085b lsrs r3, r3, #1
800090a: ea4f 0232 mov.w r2, r2, rrx
800090e: ebb6 0e02 subs.w lr, r6, r2
8000912: eb75 0e03 sbcs.w lr, r5, r3
8000916: bf22 ittt cs
8000918: 1ab6 subcs r6, r6, r2
800091a: 4675 movcs r5, lr
800091c: ea40 009c orrcs.w r0, r0, ip, lsr #2
8000920: 085b lsrs r3, r3, #1
8000922: ea4f 0232 mov.w r2, r2, rrx
8000926: ebb6 0e02 subs.w lr, r6, r2
800092a: eb75 0e03 sbcs.w lr, r5, r3
800092e: bf22 ittt cs
8000930: 1ab6 subcs r6, r6, r2
8000932: 4675 movcs r5, lr
8000934: ea40 00dc orrcs.w r0, r0, ip, lsr #3
8000938: ea55 0e06 orrs.w lr, r5, r6
800093c: d018 beq.n 8000970 <__aeabi_ddiv+0x114>
800093e: ea4f 1505 mov.w r5, r5, lsl #4
8000942: ea45 7516 orr.w r5, r5, r6, lsr #28
8000946: ea4f 1606 mov.w r6, r6, lsl #4
800094a: ea4f 03c3 mov.w r3, r3, lsl #3
800094e: ea43 7352 orr.w r3, r3, r2, lsr #29
8000952: ea4f 02c2 mov.w r2, r2, lsl #3
8000956: ea5f 1c1c movs.w ip, ip, lsr #4
800095a: d1c0 bne.n 80008de <__aeabi_ddiv+0x82>
800095c: f411 1f80 tst.w r1, #1048576 @ 0x100000
8000960: d10b bne.n 800097a <__aeabi_ddiv+0x11e>
8000962: ea41 0100 orr.w r1, r1, r0
8000966: f04f 0000 mov.w r0, #0
800096a: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000
800096e: e7b6 b.n 80008de <__aeabi_ddiv+0x82>
8000970: f411 1f80 tst.w r1, #1048576 @ 0x100000
8000974: bf04 itt eq
8000976: 4301 orreq r1, r0
8000978: 2000 moveq r0, #0
800097a: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
800097e: bf88 it hi
8000980: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
8000984: f63f aeaf bhi.w 80006e6 <__aeabi_dmul+0xde>
8000988: ebb5 0c03 subs.w ip, r5, r3
800098c: bf04 itt eq
800098e: ebb6 0c02 subseq.w ip, r6, r2
8000992: ea5f 0c50 movseq.w ip, r0, lsr #1
8000996: f150 0000 adcs.w r0, r0, #0
800099a: eb41 5104 adc.w r1, r1, r4, lsl #20
800099e: bd70 pop {r4, r5, r6, pc}
80009a0: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000
80009a4: ea4e 3111 orr.w r1, lr, r1, lsr #12
80009a8: eb14 045c adds.w r4, r4, ip, lsr #1
80009ac: bfc2 ittt gt
80009ae: ebd4 050c rsbsgt r5, r4, ip
80009b2: ea41 5104 orrgt.w r1, r1, r4, lsl #20
80009b6: bd70 popgt {r4, r5, r6, pc}
80009b8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
80009bc: f04f 0e00 mov.w lr, #0
80009c0: 3c01 subs r4, #1
80009c2: e690 b.n 80006e6 <__aeabi_dmul+0xde>
80009c4: ea45 0e06 orr.w lr, r5, r6
80009c8: e68d b.n 80006e6 <__aeabi_dmul+0xde>
80009ca: ea0c 5513 and.w r5, ip, r3, lsr #20
80009ce: ea94 0f0c teq r4, ip
80009d2: bf08 it eq
80009d4: ea95 0f0c teqeq r5, ip
80009d8: f43f af3b beq.w 8000852 <__aeabi_dmul+0x24a>
80009dc: ea94 0f0c teq r4, ip
80009e0: d10a bne.n 80009f8 <__aeabi_ddiv+0x19c>
80009e2: ea50 3401 orrs.w r4, r0, r1, lsl #12
80009e6: f47f af34 bne.w 8000852 <__aeabi_dmul+0x24a>
80009ea: ea95 0f0c teq r5, ip
80009ee: f47f af25 bne.w 800083c <__aeabi_dmul+0x234>
80009f2: 4610 mov r0, r2
80009f4: 4619 mov r1, r3
80009f6: e72c b.n 8000852 <__aeabi_dmul+0x24a>
80009f8: ea95 0f0c teq r5, ip
80009fc: d106 bne.n 8000a0c <__aeabi_ddiv+0x1b0>
80009fe: ea52 3503 orrs.w r5, r2, r3, lsl #12
8000a02: f43f aefd beq.w 8000800 <__aeabi_dmul+0x1f8>
8000a06: 4610 mov r0, r2
8000a08: 4619 mov r1, r3
8000a0a: e722 b.n 8000852 <__aeabi_dmul+0x24a>
8000a0c: ea50 0641 orrs.w r6, r0, r1, lsl #1
8000a10: bf18 it ne
8000a12: ea52 0643 orrsne.w r6, r2, r3, lsl #1
8000a16: f47f aec5 bne.w 80007a4 <__aeabi_dmul+0x19c>
8000a1a: ea50 0441 orrs.w r4, r0, r1, lsl #1
8000a1e: f47f af0d bne.w 800083c <__aeabi_dmul+0x234>
8000a22: ea52 0543 orrs.w r5, r2, r3, lsl #1
8000a26: f47f aeeb bne.w 8000800 <__aeabi_dmul+0x1f8>
8000a2a: e712 b.n 8000852 <__aeabi_dmul+0x24a>
08000a2c <__gedf2>:
8000a2c: f04f 3cff mov.w ip, #4294967295
8000a30: e006 b.n 8000a40 <__cmpdf2+0x4>
8000a32: bf00 nop
08000a34 <__ledf2>:
8000a34: f04f 0c01 mov.w ip, #1
8000a38: e002 b.n 8000a40 <__cmpdf2+0x4>
8000a3a: bf00 nop
08000a3c <__cmpdf2>:
8000a3c: f04f 0c01 mov.w ip, #1
8000a40: f84d cd04 str.w ip, [sp, #-4]!
8000a44: ea4f 0c41 mov.w ip, r1, lsl #1
8000a48: ea7f 5c6c mvns.w ip, ip, asr #21
8000a4c: ea4f 0c43 mov.w ip, r3, lsl #1
8000a50: bf18 it ne
8000a52: ea7f 5c6c mvnsne.w ip, ip, asr #21
8000a56: d01b beq.n 8000a90 <__cmpdf2+0x54>
8000a58: b001 add sp, #4
8000a5a: ea50 0c41 orrs.w ip, r0, r1, lsl #1
8000a5e: bf0c ite eq
8000a60: ea52 0c43 orrseq.w ip, r2, r3, lsl #1
8000a64: ea91 0f03 teqne r1, r3
8000a68: bf02 ittt eq
8000a6a: ea90 0f02 teqeq r0, r2
8000a6e: 2000 moveq r0, #0
8000a70: 4770 bxeq lr
8000a72: f110 0f00 cmn.w r0, #0
8000a76: ea91 0f03 teq r1, r3
8000a7a: bf58 it pl
8000a7c: 4299 cmppl r1, r3
8000a7e: bf08 it eq
8000a80: 4290 cmpeq r0, r2
8000a82: bf2c ite cs
8000a84: 17d8 asrcs r0, r3, #31
8000a86: ea6f 70e3 mvncc.w r0, r3, asr #31
8000a8a: f040 0001 orr.w r0, r0, #1
8000a8e: 4770 bx lr
8000a90: ea4f 0c41 mov.w ip, r1, lsl #1
8000a94: ea7f 5c6c mvns.w ip, ip, asr #21
8000a98: d102 bne.n 8000aa0 <__cmpdf2+0x64>
8000a9a: ea50 3c01 orrs.w ip, r0, r1, lsl #12
8000a9e: d107 bne.n 8000ab0 <__cmpdf2+0x74>
8000aa0: ea4f 0c43 mov.w ip, r3, lsl #1
8000aa4: ea7f 5c6c mvns.w ip, ip, asr #21
8000aa8: d1d6 bne.n 8000a58 <__cmpdf2+0x1c>
8000aaa: ea52 3c03 orrs.w ip, r2, r3, lsl #12
8000aae: d0d3 beq.n 8000a58 <__cmpdf2+0x1c>
8000ab0: f85d 0b04 ldr.w r0, [sp], #4
8000ab4: 4770 bx lr
8000ab6: bf00 nop
08000ab8 <__aeabi_cdrcmple>:
8000ab8: 4684 mov ip, r0
8000aba: 4610 mov r0, r2
8000abc: 4662 mov r2, ip
8000abe: 468c mov ip, r1
8000ac0: 4619 mov r1, r3
8000ac2: 4663 mov r3, ip
8000ac4: e000 b.n 8000ac8 <__aeabi_cdcmpeq>
8000ac6: bf00 nop
08000ac8 <__aeabi_cdcmpeq>:
8000ac8: b501 push {r0, lr}
8000aca: f7ff ffb7 bl 8000a3c <__cmpdf2>
8000ace: 2800 cmp r0, #0
8000ad0: bf48 it mi
8000ad2: f110 0f00 cmnmi.w r0, #0
8000ad6: bd01 pop {r0, pc}
08000ad8 <__aeabi_dcmpeq>:
8000ad8: f84d ed08 str.w lr, [sp, #-8]!
8000adc: f7ff fff4 bl 8000ac8 <__aeabi_cdcmpeq>
8000ae0: bf0c ite eq
8000ae2: 2001 moveq r0, #1
8000ae4: 2000 movne r0, #0
8000ae6: f85d fb08 ldr.w pc, [sp], #8
8000aea: bf00 nop
08000aec <__aeabi_dcmplt>:
8000aec: f84d ed08 str.w lr, [sp, #-8]!
8000af0: f7ff ffea bl 8000ac8 <__aeabi_cdcmpeq>
8000af4: bf34 ite cc
8000af6: 2001 movcc r0, #1
8000af8: 2000 movcs r0, #0
8000afa: f85d fb08 ldr.w pc, [sp], #8
8000afe: bf00 nop
08000b00 <__aeabi_dcmple>:
8000b00: f84d ed08 str.w lr, [sp, #-8]!
8000b04: f7ff ffe0 bl 8000ac8 <__aeabi_cdcmpeq>
8000b08: bf94 ite ls
8000b0a: 2001 movls r0, #1
8000b0c: 2000 movhi r0, #0
8000b0e: f85d fb08 ldr.w pc, [sp], #8
8000b12: bf00 nop
08000b14 <__aeabi_dcmpge>:
8000b14: f84d ed08 str.w lr, [sp, #-8]!
8000b18: f7ff ffce bl 8000ab8 <__aeabi_cdrcmple>
8000b1c: bf94 ite ls
8000b1e: 2001 movls r0, #1
8000b20: 2000 movhi r0, #0
8000b22: f85d fb08 ldr.w pc, [sp], #8
8000b26: bf00 nop
08000b28 <__aeabi_dcmpgt>:
8000b28: f84d ed08 str.w lr, [sp, #-8]!
8000b2c: f7ff ffc4 bl 8000ab8 <__aeabi_cdrcmple>
8000b30: bf34 ite cc
8000b32: 2001 movcc r0, #1
8000b34: 2000 movcs r0, #0
8000b36: f85d fb08 ldr.w pc, [sp], #8
8000b3a: bf00 nop
08000b3c <__aeabi_dcmpun>:
8000b3c: ea4f 0c41 mov.w ip, r1, lsl #1
8000b40: ea7f 5c6c mvns.w ip, ip, asr #21
8000b44: d102 bne.n 8000b4c <__aeabi_dcmpun+0x10>
8000b46: ea50 3c01 orrs.w ip, r0, r1, lsl #12
8000b4a: d10a bne.n 8000b62 <__aeabi_dcmpun+0x26>
8000b4c: ea4f 0c43 mov.w ip, r3, lsl #1
8000b50: ea7f 5c6c mvns.w ip, ip, asr #21
8000b54: d102 bne.n 8000b5c <__aeabi_dcmpun+0x20>
8000b56: ea52 3c03 orrs.w ip, r2, r3, lsl #12
8000b5a: d102 bne.n 8000b62 <__aeabi_dcmpun+0x26>
8000b5c: f04f 0000 mov.w r0, #0
8000b60: 4770 bx lr
8000b62: f04f 0001 mov.w r0, #1
8000b66: 4770 bx lr
08000b68 <__aeabi_d2iz>:
8000b68: ea4f 0241 mov.w r2, r1, lsl #1
8000b6c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
8000b70: d215 bcs.n 8000b9e <__aeabi_d2iz+0x36>
8000b72: d511 bpl.n 8000b98 <__aeabi_d2iz+0x30>
8000b74: f46f 7378 mvn.w r3, #992 @ 0x3e0
8000b78: ebb3 5262 subs.w r2, r3, r2, asr #21
8000b7c: d912 bls.n 8000ba4 <__aeabi_d2iz+0x3c>
8000b7e: ea4f 23c1 mov.w r3, r1, lsl #11
8000b82: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8000b86: ea43 5350 orr.w r3, r3, r0, lsr #21
8000b8a: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
8000b8e: fa23 f002 lsr.w r0, r3, r2
8000b92: bf18 it ne
8000b94: 4240 negne r0, r0
8000b96: 4770 bx lr
8000b98: f04f 0000 mov.w r0, #0
8000b9c: 4770 bx lr
8000b9e: ea50 3001 orrs.w r0, r0, r1, lsl #12
8000ba2: d105 bne.n 8000bb0 <__aeabi_d2iz+0x48>
8000ba4: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000
8000ba8: bf08 it eq
8000baa: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000
8000bae: 4770 bx lr
8000bb0: f04f 0000 mov.w r0, #0
8000bb4: 4770 bx lr
8000bb6: bf00 nop
08000bb8 <GC9A01_Select>:
[65] = { 0x0C,0x1E,0x33,0x33,0x3F,0x33,0x33,0x00 },
/* etc. */
};
// helpers pour contrôle des lignes CS/DC
static inline void GC9A01_Select(void) {
8000bb8: b580 push {r7, lr}
8000bba: af00 add r7, sp, #0
HAL_GPIO_WritePin(GC9A01_CS_GPIO_Port, GC9A01_CS_Pin, GPIO_PIN_RESET);
8000bbc: 2200 movs r2, #0
8000bbe: 2101 movs r1, #1
8000bc0: 4802 ldr r0, [pc, #8] @ (8000bcc <GC9A01_Select+0x14>)
8000bc2: f000 ff0f bl 80019e4 <HAL_GPIO_WritePin>
}
8000bc6: bf00 nop
8000bc8: bd80 pop {r7, pc}
8000bca: bf00 nop
8000bcc: 48000400 .word 0x48000400
08000bd0 <GC9A01_Unselect>:
static inline void GC9A01_Unselect(void) {
8000bd0: b580 push {r7, lr}
8000bd2: af00 add r7, sp, #0
HAL_GPIO_WritePin(GC9A01_CS_GPIO_Port, GC9A01_CS_Pin, GPIO_PIN_SET);
8000bd4: 2201 movs r2, #1
8000bd6: 2101 movs r1, #1
8000bd8: 4802 ldr r0, [pc, #8] @ (8000be4 <GC9A01_Unselect+0x14>)
8000bda: f000 ff03 bl 80019e4 <HAL_GPIO_WritePin>
}
8000bde: bf00 nop
8000be0: bd80 pop {r7, pc}
8000be2: bf00 nop
8000be4: 48000400 .word 0x48000400
08000be8 <GC9A01_DC_Command>:
static inline void GC9A01_DC_Command(void) {
8000be8: b580 push {r7, lr}
8000bea: af00 add r7, sp, #0
HAL_GPIO_WritePin(GC9A01_DC_GPIO_Port, GC9A01_DC_Pin, GPIO_PIN_RESET);
8000bec: 2200 movs r2, #0
8000bee: 2102 movs r1, #2
8000bf0: 4802 ldr r0, [pc, #8] @ (8000bfc <GC9A01_DC_Command+0x14>)
8000bf2: f000 fef7 bl 80019e4 <HAL_GPIO_WritePin>
}
8000bf6: bf00 nop
8000bf8: bd80 pop {r7, pc}
8000bfa: bf00 nop
8000bfc: 48000400 .word 0x48000400
08000c00 <GC9A01_DC_Data>:
static inline void GC9A01_DC_Data(void) {
8000c00: b580 push {r7, lr}
8000c02: af00 add r7, sp, #0
HAL_GPIO_WritePin(GC9A01_DC_GPIO_Port, GC9A01_DC_Pin, GPIO_PIN_SET);
8000c04: 2201 movs r2, #1
8000c06: 2102 movs r1, #2
8000c08: 4802 ldr r0, [pc, #8] @ (8000c14 <GC9A01_DC_Data+0x14>)
8000c0a: f000 feeb bl 80019e4 <HAL_GPIO_WritePin>
}
8000c0e: bf00 nop
8000c10: bd80 pop {r7, pc}
8000c12: bf00 nop
8000c14: 48000400 .word 0x48000400
08000c18 <GC9A01_WriteCommand>:
static void GC9A01_WriteCommand(uint8_t cmd) {
8000c18: b580 push {r7, lr}
8000c1a: b082 sub sp, #8
8000c1c: af00 add r7, sp, #0
8000c1e: 4603 mov r3, r0
8000c20: 71fb strb r3, [r7, #7]
GC9A01_DC_Command();
8000c22: f7ff ffe1 bl 8000be8 <GC9A01_DC_Command>
GC9A01_Select();
8000c26: f7ff ffc7 bl 8000bb8 <GC9A01_Select>
HAL_SPI_Transmit(hspi_gc9a01, &cmd, 1, HAL_MAX_DELAY);
8000c2a: 4b07 ldr r3, [pc, #28] @ (8000c48 <GC9A01_WriteCommand+0x30>)
8000c2c: 6818 ldr r0, [r3, #0]
8000c2e: 1df9 adds r1, r7, #7
8000c30: f04f 33ff mov.w r3, #4294967295
8000c34: 2201 movs r2, #1
8000c36: f001 fd9e bl 8002776 <HAL_SPI_Transmit>
GC9A01_Unselect();
8000c3a: f7ff ffc9 bl 8000bd0 <GC9A01_Unselect>
}
8000c3e: bf00 nop
8000c40: 3708 adds r7, #8
8000c42: 46bd mov sp, r7
8000c44: bd80 pop {r7, pc}
8000c46: bf00 nop
8000c48: 200001f0 .word 0x200001f0
08000c4c <GC9A01_WriteData>:
static void GC9A01_WriteData(uint8_t data) {
8000c4c: b580 push {r7, lr}
8000c4e: b082 sub sp, #8
8000c50: af00 add r7, sp, #0
8000c52: 4603 mov r3, r0
8000c54: 71fb strb r3, [r7, #7]
GC9A01_DC_Data();
8000c56: f7ff ffd3 bl 8000c00 <GC9A01_DC_Data>
GC9A01_Select();
8000c5a: f7ff ffad bl 8000bb8 <GC9A01_Select>
HAL_SPI_Transmit(hspi_gc9a01, &data, 1, HAL_MAX_DELAY);
8000c5e: 4b07 ldr r3, [pc, #28] @ (8000c7c <GC9A01_WriteData+0x30>)
8000c60: 6818 ldr r0, [r3, #0]
8000c62: 1df9 adds r1, r7, #7
8000c64: f04f 33ff mov.w r3, #4294967295
8000c68: 2201 movs r2, #1
8000c6a: f001 fd84 bl 8002776 <HAL_SPI_Transmit>
GC9A01_Unselect();
8000c6e: f7ff ffaf bl 8000bd0 <GC9A01_Unselect>
}
8000c72: bf00 nop
8000c74: 3708 adds r7, #8
8000c76: 46bd mov sp, r7
8000c78: bd80 pop {r7, pc}
8000c7a: bf00 nop
8000c7c: 200001f0 .word 0x200001f0
08000c80 <GC9A01_WriteDataBuffer>:
static void GC9A01_WriteDataBuffer(uint8_t *buffer, uint32_t len) {
8000c80: b580 push {r7, lr}
8000c82: b082 sub sp, #8
8000c84: af00 add r7, sp, #0
8000c86: 6078 str r0, [r7, #4]
8000c88: 6039 str r1, [r7, #0]
if (len == 0) return;
8000c8a: 683b ldr r3, [r7, #0]
8000c8c: 2b00 cmp r3, #0
8000c8e: d00f beq.n 8000cb0 <GC9A01_WriteDataBuffer+0x30>
GC9A01_DC_Data();
8000c90: f7ff ffb6 bl 8000c00 <GC9A01_DC_Data>
GC9A01_Select();
8000c94: f7ff ff90 bl 8000bb8 <GC9A01_Select>
HAL_SPI_Transmit(hspi_gc9a01, buffer, len, HAL_MAX_DELAY);
8000c98: 4b07 ldr r3, [pc, #28] @ (8000cb8 <GC9A01_WriteDataBuffer+0x38>)
8000c9a: 6818 ldr r0, [r3, #0]
8000c9c: 683b ldr r3, [r7, #0]
8000c9e: b29a uxth r2, r3
8000ca0: f04f 33ff mov.w r3, #4294967295
8000ca4: 6879 ldr r1, [r7, #4]
8000ca6: f001 fd66 bl 8002776 <HAL_SPI_Transmit>
GC9A01_Unselect();
8000caa: f7ff ff91 bl 8000bd0 <GC9A01_Unselect>
8000cae: e000 b.n 8000cb2 <GC9A01_WriteDataBuffer+0x32>
if (len == 0) return;
8000cb0: bf00 nop
}
8000cb2: 3708 adds r7, #8
8000cb4: 46bd mov sp, r7
8000cb6: bd80 pop {r7, pc}
8000cb8: 200001f0 .word 0x200001f0
08000cbc <GC9A01_SetAddressWindow>:
static void GC9A01_SetAddressWindow(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1) {
8000cbc: b590 push {r4, r7, lr}
8000cbe: b085 sub sp, #20
8000cc0: af00 add r7, sp, #0
8000cc2: 4604 mov r4, r0
8000cc4: 4608 mov r0, r1
8000cc6: 4611 mov r1, r2
8000cc8: 461a mov r2, r3
8000cca: 4623 mov r3, r4
8000ccc: 80fb strh r3, [r7, #6]
8000cce: 4603 mov r3, r0
8000cd0: 80bb strh r3, [r7, #4]
8000cd2: 460b mov r3, r1
8000cd4: 807b strh r3, [r7, #2]
8000cd6: 4613 mov r3, r2
8000cd8: 803b strh r3, [r7, #0]
GC9A01_WriteCommand(GC9A01_CASET);
8000cda: 202a movs r0, #42 @ 0x2a
8000cdc: f7ff ff9c bl 8000c18 <GC9A01_WriteCommand>
uint8_t data_col[4] = { (uint8_t)(x0>>8), (uint8_t)(x0&0xFF), (uint8_t)(x1>>8), (uint8_t)(x1&0xFF) };
8000ce0: 88fb ldrh r3, [r7, #6]
8000ce2: 0a1b lsrs r3, r3, #8
8000ce4: b29b uxth r3, r3
8000ce6: b2db uxtb r3, r3
8000ce8: 733b strb r3, [r7, #12]
8000cea: 88fb ldrh r3, [r7, #6]
8000cec: b2db uxtb r3, r3
8000cee: 737b strb r3, [r7, #13]
8000cf0: 887b ldrh r3, [r7, #2]
8000cf2: 0a1b lsrs r3, r3, #8
8000cf4: b29b uxth r3, r3
8000cf6: b2db uxtb r3, r3
8000cf8: 73bb strb r3, [r7, #14]
8000cfa: 887b ldrh r3, [r7, #2]
8000cfc: b2db uxtb r3, r3
8000cfe: 73fb strb r3, [r7, #15]
GC9A01_WriteDataBuffer(data_col, 4);
8000d00: f107 030c add.w r3, r7, #12
8000d04: 2104 movs r1, #4
8000d06: 4618 mov r0, r3
8000d08: f7ff ffba bl 8000c80 <GC9A01_WriteDataBuffer>
GC9A01_WriteCommand(GC9A01_RASET);
8000d0c: 202b movs r0, #43 @ 0x2b
8000d0e: f7ff ff83 bl 8000c18 <GC9A01_WriteCommand>
uint8_t data_row[4] = { (uint8_t)(y0>>8), (uint8_t)(y0&0xFF), (uint8_t)(y1>>8), (uint8_t)(y1&0xFF) };
8000d12: 88bb ldrh r3, [r7, #4]
8000d14: 0a1b lsrs r3, r3, #8
8000d16: b29b uxth r3, r3
8000d18: b2db uxtb r3, r3
8000d1a: 723b strb r3, [r7, #8]
8000d1c: 88bb ldrh r3, [r7, #4]
8000d1e: b2db uxtb r3, r3
8000d20: 727b strb r3, [r7, #9]
8000d22: 883b ldrh r3, [r7, #0]
8000d24: 0a1b lsrs r3, r3, #8
8000d26: b29b uxth r3, r3
8000d28: b2db uxtb r3, r3
8000d2a: 72bb strb r3, [r7, #10]
8000d2c: 883b ldrh r3, [r7, #0]
8000d2e: b2db uxtb r3, r3
8000d30: 72fb strb r3, [r7, #11]
GC9A01_WriteDataBuffer(data_row, 4);
8000d32: f107 0308 add.w r3, r7, #8
8000d36: 2104 movs r1, #4
8000d38: 4618 mov r0, r3
8000d3a: f7ff ffa1 bl 8000c80 <GC9A01_WriteDataBuffer>
GC9A01_WriteCommand(GC9A01_RAMWR);
8000d3e: 202c movs r0, #44 @ 0x2c
8000d40: f7ff ff6a bl 8000c18 <GC9A01_WriteCommand>
}
8000d44: bf00 nop
8000d46: 3714 adds r7, #20
8000d48: 46bd mov sp, r7
8000d4a: bd90 pop {r4, r7, pc}
08000d4c <GC9A01_Init>:
void GC9A01_Init(SPI_HandleTypeDef *hspi) {
8000d4c: b580 push {r7, lr}
8000d4e: b082 sub sp, #8
8000d50: af00 add r7, sp, #0
8000d52: 6078 str r0, [r7, #4]
hspi_gc9a01 = hspi;
8000d54: 4a1c ldr r2, [pc, #112] @ (8000dc8 <GC9A01_Init+0x7c>)
8000d56: 687b ldr r3, [r7, #4]
8000d58: 6013 str r3, [r2, #0]
GC9A01_Reset();
8000d5a: f000 f837 bl 8000dcc <GC9A01_Reset>
HAL_Delay(120);
8000d5e: 2078 movs r0, #120 @ 0x78
8000d60: f000 fbbc bl 80014dc <HAL_Delay>
GC9A01_WriteCommand(GC9A01_SWRESET);
8000d64: 2001 movs r0, #1
8000d66: f7ff ff57 bl 8000c18 <GC9A01_WriteCommand>
HAL_Delay(150);
8000d6a: 2096 movs r0, #150 @ 0x96
8000d6c: f000 fbb6 bl 80014dc <HAL_Delay>
GC9A01_WriteCommand(GC9A01_SLPOUT); // sortie du mode veille
8000d70: 2011 movs r0, #17
8000d72: f7ff ff51 bl 8000c18 <GC9A01_WriteCommand>
HAL_Delay(120);
8000d76: 2078 movs r0, #120 @ 0x78
8000d78: f000 fbb0 bl 80014dc <HAL_Delay>
// Format pixel RGB565 16-bit
GC9A01_WriteCommand(GC9A01_COLMOD);
8000d7c: 203a movs r0, #58 @ 0x3a
8000d7e: f7ff ff4b bl 8000c18 <GC9A01_WriteCommand>
GC9A01_WriteData(0x55); // 16 bits/pixel
8000d82: 2055 movs r0, #85 @ 0x55
8000d84: f7ff ff62 bl 8000c4c <GC9A01_WriteData>
HAL_Delay(10);
8000d88: 200a movs r0, #10
8000d8a: f000 fba7 bl 80014dc <HAL_Delay>
// Memory Access Control : rotation / orientation
GC9A01_WriteCommand(GC9A01_MADCTL);
8000d8e: 2036 movs r0, #54 @ 0x36
8000d90: f7ff ff42 bl 8000c18 <GC9A01_WriteCommand>
GC9A01_WriteData(0x00); // rotation normale, ajuste si besoin
8000d94: 2000 movs r0, #0
8000d96: f7ff ff59 bl 8000c4c <GC9A01_WriteData>
// Activation de l'écran
GC9A01_WriteCommand(GC9A01_INVON); // inversion couleurs (souvent requis)
8000d9a: 2021 movs r0, #33 @ 0x21
8000d9c: f7ff ff3c bl 8000c18 <GC9A01_WriteCommand>
HAL_Delay(10);
8000da0: 200a movs r0, #10
8000da2: f000 fb9b bl 80014dc <HAL_Delay>
GC9A01_WriteCommand(GC9A01_NORON); // mode normal on
8000da6: 2013 movs r0, #19
8000da8: f7ff ff36 bl 8000c18 <GC9A01_WriteCommand>
HAL_Delay(10);
8000dac: 200a movs r0, #10
8000dae: f000 fb95 bl 80014dc <HAL_Delay>
GC9A01_WriteCommand(GC9A01_DISPON); // allume l'écran
8000db2: 2029 movs r0, #41 @ 0x29
8000db4: f7ff ff30 bl 8000c18 <GC9A01_WriteCommand>
HAL_Delay(100);
8000db8: 2064 movs r0, #100 @ 0x64
8000dba: f000 fb8f bl 80014dc <HAL_Delay>
}
8000dbe: bf00 nop
8000dc0: 3708 adds r7, #8
8000dc2: 46bd mov sp, r7
8000dc4: bd80 pop {r7, pc}
8000dc6: bf00 nop
8000dc8: 200001f0 .word 0x200001f0
08000dcc <GC9A01_Reset>:
void GC9A01_Reset(void) {
8000dcc: b580 push {r7, lr}
8000dce: af00 add r7, sp, #0
HAL_GPIO_WritePin(GC9A01_RST_GPIO_Port, GC9A01_RST_Pin, GPIO_PIN_RESET);
8000dd0: 2200 movs r2, #0
8000dd2: 2104 movs r1, #4
8000dd4: 4807 ldr r0, [pc, #28] @ (8000df4 <GC9A01_Reset+0x28>)
8000dd6: f000 fe05 bl 80019e4 <HAL_GPIO_WritePin>
HAL_Delay(10);
8000dda: 200a movs r0, #10
8000ddc: f000 fb7e bl 80014dc <HAL_Delay>
HAL_GPIO_WritePin(GC9A01_RST_GPIO_Port, GC9A01_RST_Pin, GPIO_PIN_SET);
8000de0: 2201 movs r2, #1
8000de2: 2104 movs r1, #4
8000de4: 4803 ldr r0, [pc, #12] @ (8000df4 <GC9A01_Reset+0x28>)
8000de6: f000 fdfd bl 80019e4 <HAL_GPIO_WritePin>
HAL_Delay(10);
8000dea: 200a movs r0, #10
8000dec: f000 fb76 bl 80014dc <HAL_Delay>
}
8000df0: bf00 nop
8000df2: bd80 pop {r7, pc}
8000df4: 48000400 .word 0x48000400
08000df8 <GC9A01_DisplayOn>:
void GC9A01_DisplayOn(void) { GC9A01_WriteCommand(GC9A01_DISPON); }
8000df8: b580 push {r7, lr}
8000dfa: af00 add r7, sp, #0
8000dfc: 2029 movs r0, #41 @ 0x29
8000dfe: f7ff ff0b bl 8000c18 <GC9A01_WriteCommand>
8000e02: bf00 nop
8000e04: bd80 pop {r7, pc}
...
08000e08 <GC9A01_FillRect>:
case 3: GC9A01_WriteData(0xA8); break;
}
}
// Optimisé : envoie des blocs de pixels pour remplir un rectangle
void GC9A01_FillRect(uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint16_t color) {
8000e08: b590 push {r4, r7, lr}
8000e0a: b087 sub sp, #28
8000e0c: af00 add r7, sp, #0
8000e0e: 4604 mov r4, r0
8000e10: 4608 mov r0, r1
8000e12: 4611 mov r1, r2
8000e14: 461a mov r2, r3
8000e16: 4623 mov r3, r4
8000e18: 80fb strh r3, [r7, #6]
8000e1a: 4603 mov r3, r0
8000e1c: 80bb strh r3, [r7, #4]
8000e1e: 460b mov r3, r1
8000e20: 807b strh r3, [r7, #2]
8000e22: 4613 mov r3, r2
8000e24: 803b strh r3, [r7, #0]
if (x >= GC9A01_WIDTH || y >= GC9A01_HEIGHT) return;
8000e26: 88fb ldrh r3, [r7, #6]
8000e28: 2bef cmp r3, #239 @ 0xef
8000e2a: d866 bhi.n 8000efa <GC9A01_FillRect+0xf2>
8000e2c: 88bb ldrh r3, [r7, #4]
8000e2e: 2bef cmp r3, #239 @ 0xef
8000e30: d863 bhi.n 8000efa <GC9A01_FillRect+0xf2>
if (x + width > GC9A01_WIDTH) width = GC9A01_WIDTH - x;
8000e32: 88fa ldrh r2, [r7, #6]
8000e34: 887b ldrh r3, [r7, #2]
8000e36: 4413 add r3, r2
8000e38: 2bf0 cmp r3, #240 @ 0xf0
8000e3a: dd03 ble.n 8000e44 <GC9A01_FillRect+0x3c>
8000e3c: 88fb ldrh r3, [r7, #6]
8000e3e: f1c3 03f0 rsb r3, r3, #240 @ 0xf0
8000e42: 807b strh r3, [r7, #2]
if (y + height > GC9A01_HEIGHT) height = GC9A01_HEIGHT - y;
8000e44: 88ba ldrh r2, [r7, #4]
8000e46: 883b ldrh r3, [r7, #0]
8000e48: 4413 add r3, r2
8000e4a: 2bf0 cmp r3, #240 @ 0xf0
8000e4c: dd03 ble.n 8000e56 <GC9A01_FillRect+0x4e>
8000e4e: 88bb ldrh r3, [r7, #4]
8000e50: f1c3 03f0 rsb r3, r3, #240 @ 0xf0
8000e54: 803b strh r3, [r7, #0]
GC9A01_SetAddressWindow(x, y, x + width - 1, y + height - 1);
8000e56: 88fa ldrh r2, [r7, #6]
8000e58: 887b ldrh r3, [r7, #2]
8000e5a: 4413 add r3, r2
8000e5c: b29b uxth r3, r3
8000e5e: 3b01 subs r3, #1
8000e60: b29c uxth r4, r3
8000e62: 88ba ldrh r2, [r7, #4]
8000e64: 883b ldrh r3, [r7, #0]
8000e66: 4413 add r3, r2
8000e68: b29b uxth r3, r3
8000e6a: 3b01 subs r3, #1
8000e6c: b29b uxth r3, r3
8000e6e: 88b9 ldrh r1, [r7, #4]
8000e70: 88f8 ldrh r0, [r7, #6]
8000e72: 4622 mov r2, r4
8000e74: f7ff ff22 bl 8000cbc <GC9A01_SetAddressWindow>
static uint8_t data[PIX_BUF * 2];
uint8_t high = color >> 8;
8000e78: 8d3b ldrh r3, [r7, #40] @ 0x28
8000e7a: 0a1b lsrs r3, r3, #8
8000e7c: b29b uxth r3, r3
8000e7e: 73fb strb r3, [r7, #15]
uint8_t low = color & 0xFF;
8000e80: 8d3b ldrh r3, [r7, #40] @ 0x28
8000e82: 73bb strb r3, [r7, #14]
for (uint32_t i = 0; i < PIX_BUF; ++i) {
8000e84: 2300 movs r3, #0
8000e86: 617b str r3, [r7, #20]
8000e88: e00d b.n 8000ea6 <GC9A01_FillRect+0x9e>
data[2*i] = high;
8000e8a: 697b ldr r3, [r7, #20]
8000e8c: 005b lsls r3, r3, #1
8000e8e: 491d ldr r1, [pc, #116] @ (8000f04 <GC9A01_FillRect+0xfc>)
8000e90: 7bfa ldrb r2, [r7, #15]
8000e92: 54ca strb r2, [r1, r3]
data[2*i + 1] = low;
8000e94: 697b ldr r3, [r7, #20]
8000e96: 005b lsls r3, r3, #1
8000e98: 3301 adds r3, #1
8000e9a: 491a ldr r1, [pc, #104] @ (8000f04 <GC9A01_FillRect+0xfc>)
8000e9c: 7bba ldrb r2, [r7, #14]
8000e9e: 54ca strb r2, [r1, r3]
for (uint32_t i = 0; i < PIX_BUF; ++i) {
8000ea0: 697b ldr r3, [r7, #20]
8000ea2: 3301 adds r3, #1
8000ea4: 617b str r3, [r7, #20]
8000ea6: 697b ldr r3, [r7, #20]
8000ea8: f5b3 7f00 cmp.w r3, #512 @ 0x200
8000eac: d3ed bcc.n 8000e8a <GC9A01_FillRect+0x82>
}
uint32_t total = (uint32_t)width * height;
8000eae: 887b ldrh r3, [r7, #2]
8000eb0: 883a ldrh r2, [r7, #0]
8000eb2: fb02 f303 mul.w r3, r2, r3
8000eb6: 613b str r3, [r7, #16]
GC9A01_DC_Data();
8000eb8: f7ff fea2 bl 8000c00 <GC9A01_DC_Data>
GC9A01_Select();
8000ebc: f7ff fe7c bl 8000bb8 <GC9A01_Select>
while (total) {
8000ec0: e015 b.n 8000eee <GC9A01_FillRect+0xe6>
uint32_t chunk = (total > PIX_BUF) ? PIX_BUF : total;
8000ec2: 693b ldr r3, [r7, #16]
8000ec4: f5b3 7f00 cmp.w r3, #512 @ 0x200
8000ec8: bf28 it cs
8000eca: f44f 7300 movcs.w r3, #512 @ 0x200
8000ece: 60bb str r3, [r7, #8]
HAL_SPI_Transmit(hspi_gc9a01, data, chunk * 2, HAL_MAX_DELAY);
8000ed0: 4b0d ldr r3, [pc, #52] @ (8000f08 <GC9A01_FillRect+0x100>)
8000ed2: 6818 ldr r0, [r3, #0]
8000ed4: 68bb ldr r3, [r7, #8]
8000ed6: b29b uxth r3, r3
8000ed8: 005b lsls r3, r3, #1
8000eda: b29a uxth r2, r3
8000edc: f04f 33ff mov.w r3, #4294967295
8000ee0: 4908 ldr r1, [pc, #32] @ (8000f04 <GC9A01_FillRect+0xfc>)
8000ee2: f001 fc48 bl 8002776 <HAL_SPI_Transmit>
total -= chunk;
8000ee6: 693a ldr r2, [r7, #16]
8000ee8: 68bb ldr r3, [r7, #8]
8000eea: 1ad3 subs r3, r2, r3
8000eec: 613b str r3, [r7, #16]
while (total) {
8000eee: 693b ldr r3, [r7, #16]
8000ef0: 2b00 cmp r3, #0
8000ef2: d1e6 bne.n 8000ec2 <GC9A01_FillRect+0xba>
}
GC9A01_Unselect();
8000ef4: f7ff fe6c bl 8000bd0 <GC9A01_Unselect>
8000ef8: e000 b.n 8000efc <GC9A01_FillRect+0xf4>
if (x >= GC9A01_WIDTH || y >= GC9A01_HEIGHT) return;
8000efa: bf00 nop
}
8000efc: 371c adds r7, #28
8000efe: 46bd mov sp, r7
8000f00: bd90 pop {r4, r7, pc}
8000f02: bf00 nop
8000f04: 200001f4 .word 0x200001f4
8000f08: 200001f0 .word 0x200001f0
08000f0c <GC9A01_FillScreen>:
void GC9A01_FillScreen(uint16_t color) {
8000f0c: b580 push {r7, lr}
8000f0e: b084 sub sp, #16
8000f10: af02 add r7, sp, #8
8000f12: 4603 mov r3, r0
8000f14: 80fb strh r3, [r7, #6]
GC9A01_FillRect(0, 0, GC9A01_WIDTH, GC9A01_HEIGHT, color);
8000f16: 88fb ldrh r3, [r7, #6]
8000f18: 9300 str r3, [sp, #0]
8000f1a: 23f0 movs r3, #240 @ 0xf0
8000f1c: 22f0 movs r2, #240 @ 0xf0
8000f1e: 2100 movs r1, #0
8000f20: 2000 movs r0, #0
8000f22: f7ff ff71 bl 8000e08 <GC9A01_FillRect>
}
8000f26: bf00 nop
8000f28: 3708 adds r7, #8
8000f2a: 46bd mov sp, r7
8000f2c: bd80 pop {r7, pc}
...
08000f30 <main>:
void SystemClock_Config(void);
static void MX_GPIO_Init(void);
static void MX_SPI1_Init(void);
int main(void)
{
8000f30: b580 push {r7, lr}
8000f32: af00 add r7, sp, #0
HAL_Init();
8000f34: f000 fa56 bl 80013e4 <HAL_Init>
SystemClock_Config();
8000f38: f000 f87a bl 8001030 <SystemClock_Config>
MX_GPIO_Init();
8000f3c: f000 f848 bl 8000fd0 <MX_GPIO_Init>
MX_SPI1_Init();
8000f40: f000 f80e bl 8000f60 <MX_SPI1_Init>
// Initialisation écran GC9A01
GC9A01_Init(&hspi1);
8000f44: 4805 ldr r0, [pc, #20] @ (8000f5c <main+0x2c>)
8000f46: f7ff ff01 bl 8000d4c <GC9A01_Init>
// Allumer l'écran
GC9A01_DisplayOn();
8000f4a: f7ff ff55 bl 8000df8 <GC9A01_DisplayOn>
// Test simple : écran rouge
GC9A01_FillScreen(GC9A01_RED);
8000f4e: f44f 4078 mov.w r0, #63488 @ 0xf800
8000f52: f7ff ffdb bl 8000f0c <GC9A01_FillScreen>
while(1)
8000f56: bf00 nop
8000f58: e7fd b.n 8000f56 <main+0x26>
8000f5a: bf00 nop
8000f5c: 200005f4 .word 0x200005f4
08000f60 <MX_SPI1_Init>:
}
}
// ----------- Configuration SPI1 -----------
static void MX_SPI1_Init(void)
{
8000f60: b580 push {r7, lr}
8000f62: af00 add r7, sp, #0
hspi1.Instance = SPI1;
8000f64: 4b18 ldr r3, [pc, #96] @ (8000fc8 <MX_SPI1_Init+0x68>)
8000f66: 4a19 ldr r2, [pc, #100] @ (8000fcc <MX_SPI1_Init+0x6c>)
8000f68: 601a str r2, [r3, #0]
hspi1.Init.Mode = SPI_MODE_MASTER;
8000f6a: 4b17 ldr r3, [pc, #92] @ (8000fc8 <MX_SPI1_Init+0x68>)
8000f6c: f44f 7282 mov.w r2, #260 @ 0x104
8000f70: 605a str r2, [r3, #4]
hspi1.Init.Direction = SPI_DIRECTION_1LINE; // ou 2LINES si câblé full duplex
8000f72: 4b15 ldr r3, [pc, #84] @ (8000fc8 <MX_SPI1_Init+0x68>)
8000f74: f44f 4200 mov.w r2, #32768 @ 0x8000
8000f78: 609a str r2, [r3, #8]
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
8000f7a: 4b13 ldr r3, [pc, #76] @ (8000fc8 <MX_SPI1_Init+0x68>)
8000f7c: f44f 62e0 mov.w r2, #1792 @ 0x700
8000f80: 60da str r2, [r3, #12]
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
8000f82: 4b11 ldr r3, [pc, #68] @ (8000fc8 <MX_SPI1_Init+0x68>)
8000f84: 2200 movs r2, #0
8000f86: 611a str r2, [r3, #16]
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
8000f88: 4b0f ldr r3, [pc, #60] @ (8000fc8 <MX_SPI1_Init+0x68>)
8000f8a: 2200 movs r2, #0
8000f8c: 615a str r2, [r3, #20]
hspi1.Init.NSS = SPI_NSS_SOFT;
8000f8e: 4b0e ldr r3, [pc, #56] @ (8000fc8 <MX_SPI1_Init+0x68>)
8000f90: f44f 7200 mov.w r2, #512 @ 0x200
8000f94: 619a str r2, [r3, #24]
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8; // Ajuste selon ton horloge
8000f96: 4b0c ldr r3, [pc, #48] @ (8000fc8 <MX_SPI1_Init+0x68>)
8000f98: 2210 movs r2, #16
8000f9a: 61da str r2, [r3, #28]
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
8000f9c: 4b0a ldr r3, [pc, #40] @ (8000fc8 <MX_SPI1_Init+0x68>)
8000f9e: 2200 movs r2, #0
8000fa0: 621a str r2, [r3, #32]
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
8000fa2: 4b09 ldr r3, [pc, #36] @ (8000fc8 <MX_SPI1_Init+0x68>)
8000fa4: 2200 movs r2, #0
8000fa6: 625a str r2, [r3, #36] @ 0x24
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8000fa8: 4b07 ldr r3, [pc, #28] @ (8000fc8 <MX_SPI1_Init+0x68>)
8000faa: 2200 movs r2, #0
8000fac: 629a str r2, [r3, #40] @ 0x28
hspi1.Init.CRCPolynomial = 10;
8000fae: 4b06 ldr r3, [pc, #24] @ (8000fc8 <MX_SPI1_Init+0x68>)
8000fb0: 220a movs r2, #10
8000fb2: 62da str r2, [r3, #44] @ 0x2c
if (HAL_SPI_Init(&hspi1) != HAL_OK)
8000fb4: 4804 ldr r0, [pc, #16] @ (8000fc8 <MX_SPI1_Init+0x68>)
8000fb6: f001 fb3b bl 8002630 <HAL_SPI_Init>
8000fba: 4603 mov r3, r0
8000fbc: 2b00 cmp r3, #0
8000fbe: d001 beq.n 8000fc4 <MX_SPI1_Init+0x64>
{
Error_Handler();
8000fc0: f000 f872 bl 80010a8 <Error_Handler>
}
}
8000fc4: bf00 nop
8000fc6: bd80 pop {r7, pc}
8000fc8: 200005f4 .word 0x200005f4
8000fcc: 40013000 .word 0x40013000
08000fd0 <MX_GPIO_Init>:
// ----------- Configuration GPIO (CS, DC, RST) -----------
static void MX_GPIO_Init(void)
{
8000fd0: b580 push {r7, lr}
8000fd2: b086 sub sp, #24
8000fd4: af00 add r7, sp, #0
__HAL_RCC_GPIOB_CLK_ENABLE();
8000fd6: 4b14 ldr r3, [pc, #80] @ (8001028 <MX_GPIO_Init+0x58>)
8000fd8: 6cdb ldr r3, [r3, #76] @ 0x4c
8000fda: 4a13 ldr r2, [pc, #76] @ (8001028 <MX_GPIO_Init+0x58>)
8000fdc: f043 0302 orr.w r3, r3, #2
8000fe0: 64d3 str r3, [r2, #76] @ 0x4c
8000fe2: 4b11 ldr r3, [pc, #68] @ (8001028 <MX_GPIO_Init+0x58>)
8000fe4: 6cdb ldr r3, [r3, #76] @ 0x4c
8000fe6: f003 0302 and.w r3, r3, #2
8000fea: 603b str r3, [r7, #0]
8000fec: 683b ldr r3, [r7, #0]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000fee: 1d3b adds r3, r7, #4
8000ff0: 2200 movs r2, #0
8000ff2: 601a str r2, [r3, #0]
8000ff4: 605a str r2, [r3, #4]
8000ff6: 609a str r2, [r3, #8]
8000ff8: 60da str r2, [r3, #12]
8000ffa: 611a str r2, [r3, #16]
// CS, DC, RST pins en sortie
GPIO_InitStruct.Pin = GC9A01_CS_Pin | GC9A01_DC_Pin | GC9A01_RST_Pin;
8000ffc: 2307 movs r3, #7
8000ffe: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001000: 2301 movs r3, #1
8001002: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001004: 2300 movs r3, #0
8001006: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001008: 2300 movs r3, #0
800100a: 613b str r3, [r7, #16]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800100c: 1d3b adds r3, r7, #4
800100e: 4619 mov r1, r3
8001010: 4806 ldr r0, [pc, #24] @ (800102c <MX_GPIO_Init+0x5c>)
8001012: f000 fb6d bl 80016f0 <HAL_GPIO_Init>
// Mettre CS, DC, RST à 1 par défaut (CS inactif)
HAL_GPIO_WritePin(GPIOB, GC9A01_CS_Pin | GC9A01_DC_Pin | GC9A01_RST_Pin, GPIO_PIN_SET);
8001016: 2201 movs r2, #1
8001018: 2107 movs r1, #7
800101a: 4804 ldr r0, [pc, #16] @ (800102c <MX_GPIO_Init+0x5c>)
800101c: f000 fce2 bl 80019e4 <HAL_GPIO_WritePin>
}
8001020: bf00 nop
8001022: 3718 adds r7, #24
8001024: 46bd mov sp, r7
8001026: bd80 pop {r7, pc}
8001028: 40021000 .word 0x40021000
800102c: 48000400 .word 0x48000400
08001030 <SystemClock_Config>:
// ----------- Configuration horloge (exemple) -----------
void SystemClock_Config(void)
{
8001030: b580 push {r7, lr}
8001032: b096 sub sp, #88 @ 0x58
8001034: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8001036: f107 0314 add.w r3, r7, #20
800103a: 2244 movs r2, #68 @ 0x44
800103c: 2100 movs r1, #0
800103e: 4618 mov r0, r3
8001040: f002 fbcf bl 80037e2 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8001044: 463b mov r3, r7
8001046: 2200 movs r2, #0
8001048: 601a str r2, [r3, #0]
800104a: 605a str r2, [r3, #4]
800104c: 609a str r2, [r3, #8]
800104e: 60da str r2, [r3, #12]
8001050: 611a str r2, [r3, #16]
// Configuration de l'oscillateur
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
8001052: 2302 movs r3, #2
8001054: 617b str r3, [r7, #20]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8001056: f44f 7380 mov.w r3, #256 @ 0x100
800105a: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
800105c: 2340 movs r3, #64 @ 0x40
800105e: 627b str r3, [r7, #36] @ 0x24
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
8001060: 2300 movs r3, #0
8001062: 63fb str r3, [r7, #60] @ 0x3c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8001064: f107 0314 add.w r3, r7, #20
8001068: 4618 mov r0, r3
800106a: f000 fce1 bl 8001a30 <HAL_RCC_OscConfig>
800106e: 4603 mov r3, r0
8001070: 2b00 cmp r3, #0
8001072: d001 beq.n 8001078 <SystemClock_Config+0x48>
{
Error_Handler();
8001074: f000 f818 bl 80010a8 <Error_Handler>
}
// Configuration des horloges CPU, AHB et APB
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8001078: 230f movs r3, #15
800107a: 603b str r3, [r7, #0]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
800107c: 2301 movs r3, #1
800107e: 607b str r3, [r7, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8001080: 2300 movs r3, #0
8001082: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
8001084: 2300 movs r3, #0
8001086: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8001088: 2300 movs r3, #0
800108a: 613b str r3, [r7, #16]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
800108c: 463b mov r3, r7
800108e: 2100 movs r1, #0
8001090: 4618 mov r0, r3
8001092: f001 f8e1 bl 8002258 <HAL_RCC_ClockConfig>
8001096: 4603 mov r3, r0
8001098: 2b00 cmp r3, #0
800109a: d001 beq.n 80010a0 <SystemClock_Config+0x70>
{
Error_Handler();
800109c: f000 f804 bl 80010a8 <Error_Handler>
}
}
80010a0: bf00 nop
80010a2: 3758 adds r7, #88 @ 0x58
80010a4: 46bd mov sp, r7
80010a6: bd80 pop {r7, pc}
080010a8 <Error_Handler>:
// En cas d'erreur
void Error_Handler(void)
{
80010a8: b480 push {r7}
80010aa: af00 add r7, sp, #0
while(1)
80010ac: bf00 nop
80010ae: e7fd b.n 80010ac <Error_Handler+0x4>
080010b0 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80010b0: b480 push {r7}
80010b2: b083 sub sp, #12
80010b4: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80010b6: 4b0f ldr r3, [pc, #60] @ (80010f4 <HAL_MspInit+0x44>)
80010b8: 6e1b ldr r3, [r3, #96] @ 0x60
80010ba: 4a0e ldr r2, [pc, #56] @ (80010f4 <HAL_MspInit+0x44>)
80010bc: f043 0301 orr.w r3, r3, #1
80010c0: 6613 str r3, [r2, #96] @ 0x60
80010c2: 4b0c ldr r3, [pc, #48] @ (80010f4 <HAL_MspInit+0x44>)
80010c4: 6e1b ldr r3, [r3, #96] @ 0x60
80010c6: f003 0301 and.w r3, r3, #1
80010ca: 607b str r3, [r7, #4]
80010cc: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
80010ce: 4b09 ldr r3, [pc, #36] @ (80010f4 <HAL_MspInit+0x44>)
80010d0: 6d9b ldr r3, [r3, #88] @ 0x58
80010d2: 4a08 ldr r2, [pc, #32] @ (80010f4 <HAL_MspInit+0x44>)
80010d4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80010d8: 6593 str r3, [r2, #88] @ 0x58
80010da: 4b06 ldr r3, [pc, #24] @ (80010f4 <HAL_MspInit+0x44>)
80010dc: 6d9b ldr r3, [r3, #88] @ 0x58
80010de: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80010e2: 603b str r3, [r7, #0]
80010e4: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
80010e6: bf00 nop
80010e8: 370c adds r7, #12
80010ea: 46bd mov sp, r7
80010ec: f85d 7b04 ldr.w r7, [sp], #4
80010f0: 4770 bx lr
80010f2: bf00 nop
80010f4: 40021000 .word 0x40021000
080010f8 <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
80010f8: b580 push {r7, lr}
80010fa: b08a sub sp, #40 @ 0x28
80010fc: af00 add r7, sp, #0
80010fe: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001100: f107 0314 add.w r3, r7, #20
8001104: 2200 movs r2, #0
8001106: 601a str r2, [r3, #0]
8001108: 605a str r2, [r3, #4]
800110a: 609a str r2, [r3, #8]
800110c: 60da str r2, [r3, #12]
800110e: 611a str r2, [r3, #16]
if(hspi->Instance==SPI1)
8001110: 687b ldr r3, [r7, #4]
8001112: 681b ldr r3, [r3, #0]
8001114: 4a18 ldr r2, [pc, #96] @ (8001178 <HAL_SPI_MspInit+0x80>)
8001116: 4293 cmp r3, r2
8001118: d129 bne.n 800116e <HAL_SPI_MspInit+0x76>
{
/* USER CODE BEGIN SPI1_MspInit 0 */
/* USER CODE END SPI1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI1_CLK_ENABLE();
800111a: 4b18 ldr r3, [pc, #96] @ (800117c <HAL_SPI_MspInit+0x84>)
800111c: 6e1b ldr r3, [r3, #96] @ 0x60
800111e: 4a17 ldr r2, [pc, #92] @ (800117c <HAL_SPI_MspInit+0x84>)
8001120: f443 5380 orr.w r3, r3, #4096 @ 0x1000
8001124: 6613 str r3, [r2, #96] @ 0x60
8001126: 4b15 ldr r3, [pc, #84] @ (800117c <HAL_SPI_MspInit+0x84>)
8001128: 6e1b ldr r3, [r3, #96] @ 0x60
800112a: f403 5380 and.w r3, r3, #4096 @ 0x1000
800112e: 613b str r3, [r7, #16]
8001130: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001132: 4b12 ldr r3, [pc, #72] @ (800117c <HAL_SPI_MspInit+0x84>)
8001134: 6cdb ldr r3, [r3, #76] @ 0x4c
8001136: 4a11 ldr r2, [pc, #68] @ (800117c <HAL_SPI_MspInit+0x84>)
8001138: f043 0301 orr.w r3, r3, #1
800113c: 64d3 str r3, [r2, #76] @ 0x4c
800113e: 4b0f ldr r3, [pc, #60] @ (800117c <HAL_SPI_MspInit+0x84>)
8001140: 6cdb ldr r3, [r3, #76] @ 0x4c
8001142: f003 0301 and.w r3, r3, #1
8001146: 60fb str r3, [r7, #12]
8001148: 68fb ldr r3, [r7, #12]
/**SPI1 GPIO Configuration
PA1 ------> SPI1_SCK
PA11 ------> SPI1_MISO
PA12 ------> SPI1_MOSI
*/
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_11|GPIO_PIN_12;
800114a: f641 0302 movw r3, #6146 @ 0x1802
800114e: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001150: 2302 movs r3, #2
8001152: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001154: 2300 movs r3, #0
8001156: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001158: 2303 movs r3, #3
800115a: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
800115c: 2305 movs r3, #5
800115e: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001160: f107 0314 add.w r3, r7, #20
8001164: 4619 mov r1, r3
8001166: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
800116a: f000 fac1 bl 80016f0 <HAL_GPIO_Init>
/* USER CODE END SPI1_MspInit 1 */
}
}
800116e: bf00 nop
8001170: 3728 adds r7, #40 @ 0x28
8001172: 46bd mov sp, r7
8001174: bd80 pop {r7, pc}
8001176: bf00 nop
8001178: 40013000 .word 0x40013000
800117c: 40021000 .word 0x40021000
08001180 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001180: b480 push {r7}
8001182: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8001184: bf00 nop
8001186: e7fd b.n 8001184 <NMI_Handler+0x4>
08001188 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8001188: b480 push {r7}
800118a: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
800118c: bf00 nop
800118e: e7fd b.n 800118c <HardFault_Handler+0x4>
08001190 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8001190: b480 push {r7}
8001192: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001194: bf00 nop
8001196: e7fd b.n 8001194 <MemManage_Handler+0x4>
08001198 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8001198: b480 push {r7}
800119a: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
800119c: bf00 nop
800119e: e7fd b.n 800119c <BusFault_Handler+0x4>
080011a0 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
80011a0: b480 push {r7}
80011a2: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
80011a4: bf00 nop
80011a6: e7fd b.n 80011a4 <UsageFault_Handler+0x4>
080011a8 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
80011a8: b480 push {r7}
80011aa: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
80011ac: bf00 nop
80011ae: 46bd mov sp, r7
80011b0: f85d 7b04 ldr.w r7, [sp], #4
80011b4: 4770 bx lr
080011b6 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
80011b6: b480 push {r7}
80011b8: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
80011ba: bf00 nop
80011bc: 46bd mov sp, r7
80011be: f85d 7b04 ldr.w r7, [sp], #4
80011c2: 4770 bx lr
080011c4 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
80011c4: b480 push {r7}
80011c6: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
80011c8: bf00 nop
80011ca: 46bd mov sp, r7
80011cc: f85d 7b04 ldr.w r7, [sp], #4
80011d0: 4770 bx lr
080011d2 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
80011d2: b580 push {r7, lr}
80011d4: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
80011d6: f000 f961 bl 800149c <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
80011da: bf00 nop
80011dc: bd80 pop {r7, pc}
080011de <_getpid>:
void initialise_monitor_handles()
{
}
int _getpid(void)
{
80011de: b480 push {r7}
80011e0: af00 add r7, sp, #0
return 1;
80011e2: 2301 movs r3, #1
}
80011e4: 4618 mov r0, r3
80011e6: 46bd mov sp, r7
80011e8: f85d 7b04 ldr.w r7, [sp], #4
80011ec: 4770 bx lr
080011ee <_kill>:
int _kill(int pid, int sig)
{
80011ee: b580 push {r7, lr}
80011f0: b082 sub sp, #8
80011f2: af00 add r7, sp, #0
80011f4: 6078 str r0, [r7, #4]
80011f6: 6039 str r1, [r7, #0]
(void)pid;
(void)sig;
errno = EINVAL;
80011f8: f002 fb46 bl 8003888 <__errno>
80011fc: 4603 mov r3, r0
80011fe: 2216 movs r2, #22
8001200: 601a str r2, [r3, #0]
return -1;
8001202: f04f 33ff mov.w r3, #4294967295
}
8001206: 4618 mov r0, r3
8001208: 3708 adds r7, #8
800120a: 46bd mov sp, r7
800120c: bd80 pop {r7, pc}
0800120e <_exit>:
void _exit (int status)
{
800120e: b580 push {r7, lr}
8001210: b082 sub sp, #8
8001212: af00 add r7, sp, #0
8001214: 6078 str r0, [r7, #4]
_kill(status, -1);
8001216: f04f 31ff mov.w r1, #4294967295
800121a: 6878 ldr r0, [r7, #4]
800121c: f7ff ffe7 bl 80011ee <_kill>
while (1) {} /* Make sure we hang here */
8001220: bf00 nop
8001222: e7fd b.n 8001220 <_exit+0x12>
08001224 <_read>:
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
8001224: b580 push {r7, lr}
8001226: b086 sub sp, #24
8001228: af00 add r7, sp, #0
800122a: 60f8 str r0, [r7, #12]
800122c: 60b9 str r1, [r7, #8]
800122e: 607a str r2, [r7, #4]
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
8001230: 2300 movs r3, #0
8001232: 617b str r3, [r7, #20]
8001234: e00a b.n 800124c <_read+0x28>
{
*ptr++ = __io_getchar();
8001236: f3af 8000 nop.w
800123a: 4601 mov r1, r0
800123c: 68bb ldr r3, [r7, #8]
800123e: 1c5a adds r2, r3, #1
8001240: 60ba str r2, [r7, #8]
8001242: b2ca uxtb r2, r1
8001244: 701a strb r2, [r3, #0]
for (DataIdx = 0; DataIdx < len; DataIdx++)
8001246: 697b ldr r3, [r7, #20]
8001248: 3301 adds r3, #1
800124a: 617b str r3, [r7, #20]
800124c: 697a ldr r2, [r7, #20]
800124e: 687b ldr r3, [r7, #4]
8001250: 429a cmp r2, r3
8001252: dbf0 blt.n 8001236 <_read+0x12>
}
return len;
8001254: 687b ldr r3, [r7, #4]
}
8001256: 4618 mov r0, r3
8001258: 3718 adds r7, #24
800125a: 46bd mov sp, r7
800125c: bd80 pop {r7, pc}
0800125e <_write>:
__attribute__((weak)) int _write(int file, char *ptr, int len)
{
800125e: b580 push {r7, lr}
8001260: b086 sub sp, #24
8001262: af00 add r7, sp, #0
8001264: 60f8 str r0, [r7, #12]
8001266: 60b9 str r1, [r7, #8]
8001268: 607a str r2, [r7, #4]
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
800126a: 2300 movs r3, #0
800126c: 617b str r3, [r7, #20]
800126e: e009 b.n 8001284 <_write+0x26>
{
__io_putchar(*ptr++);
8001270: 68bb ldr r3, [r7, #8]
8001272: 1c5a adds r2, r3, #1
8001274: 60ba str r2, [r7, #8]
8001276: 781b ldrb r3, [r3, #0]
8001278: 4618 mov r0, r3
800127a: f3af 8000 nop.w
for (DataIdx = 0; DataIdx < len; DataIdx++)
800127e: 697b ldr r3, [r7, #20]
8001280: 3301 adds r3, #1
8001282: 617b str r3, [r7, #20]
8001284: 697a ldr r2, [r7, #20]
8001286: 687b ldr r3, [r7, #4]
8001288: 429a cmp r2, r3
800128a: dbf1 blt.n 8001270 <_write+0x12>
}
return len;
800128c: 687b ldr r3, [r7, #4]
}
800128e: 4618 mov r0, r3
8001290: 3718 adds r7, #24
8001292: 46bd mov sp, r7
8001294: bd80 pop {r7, pc}
08001296 <_close>:
int _close(int file)
{
8001296: b480 push {r7}
8001298: b083 sub sp, #12
800129a: af00 add r7, sp, #0
800129c: 6078 str r0, [r7, #4]
(void)file;
return -1;
800129e: f04f 33ff mov.w r3, #4294967295
}
80012a2: 4618 mov r0, r3
80012a4: 370c adds r7, #12
80012a6: 46bd mov sp, r7
80012a8: f85d 7b04 ldr.w r7, [sp], #4
80012ac: 4770 bx lr
080012ae <_fstat>:
int _fstat(int file, struct stat *st)
{
80012ae: b480 push {r7}
80012b0: b083 sub sp, #12
80012b2: af00 add r7, sp, #0
80012b4: 6078 str r0, [r7, #4]
80012b6: 6039 str r1, [r7, #0]
(void)file;
st->st_mode = S_IFCHR;
80012b8: 683b ldr r3, [r7, #0]
80012ba: f44f 5200 mov.w r2, #8192 @ 0x2000
80012be: 605a str r2, [r3, #4]
return 0;
80012c0: 2300 movs r3, #0
}
80012c2: 4618 mov r0, r3
80012c4: 370c adds r7, #12
80012c6: 46bd mov sp, r7
80012c8: f85d 7b04 ldr.w r7, [sp], #4
80012cc: 4770 bx lr
080012ce <_isatty>:
int _isatty(int file)
{
80012ce: b480 push {r7}
80012d0: b083 sub sp, #12
80012d2: af00 add r7, sp, #0
80012d4: 6078 str r0, [r7, #4]
(void)file;
return 1;
80012d6: 2301 movs r3, #1
}
80012d8: 4618 mov r0, r3
80012da: 370c adds r7, #12
80012dc: 46bd mov sp, r7
80012de: f85d 7b04 ldr.w r7, [sp], #4
80012e2: 4770 bx lr
080012e4 <_lseek>:
int _lseek(int file, int ptr, int dir)
{
80012e4: b480 push {r7}
80012e6: b085 sub sp, #20
80012e8: af00 add r7, sp, #0
80012ea: 60f8 str r0, [r7, #12]
80012ec: 60b9 str r1, [r7, #8]
80012ee: 607a str r2, [r7, #4]
(void)file;
(void)ptr;
(void)dir;
return 0;
80012f0: 2300 movs r3, #0
}
80012f2: 4618 mov r0, r3
80012f4: 3714 adds r7, #20
80012f6: 46bd mov sp, r7
80012f8: f85d 7b04 ldr.w r7, [sp], #4
80012fc: 4770 bx lr
...
08001300 <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
8001300: b580 push {r7, lr}
8001302: b086 sub sp, #24
8001304: af00 add r7, sp, #0
8001306: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
8001308: 4a14 ldr r2, [pc, #80] @ (800135c <_sbrk+0x5c>)
800130a: 4b15 ldr r3, [pc, #84] @ (8001360 <_sbrk+0x60>)
800130c: 1ad3 subs r3, r2, r3
800130e: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
8001310: 697b ldr r3, [r7, #20]
8001312: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
8001314: 4b13 ldr r3, [pc, #76] @ (8001364 <_sbrk+0x64>)
8001316: 681b ldr r3, [r3, #0]
8001318: 2b00 cmp r3, #0
800131a: d102 bne.n 8001322 <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
800131c: 4b11 ldr r3, [pc, #68] @ (8001364 <_sbrk+0x64>)
800131e: 4a12 ldr r2, [pc, #72] @ (8001368 <_sbrk+0x68>)
8001320: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
8001322: 4b10 ldr r3, [pc, #64] @ (8001364 <_sbrk+0x64>)
8001324: 681a ldr r2, [r3, #0]
8001326: 687b ldr r3, [r7, #4]
8001328: 4413 add r3, r2
800132a: 693a ldr r2, [r7, #16]
800132c: 429a cmp r2, r3
800132e: d207 bcs.n 8001340 <_sbrk+0x40>
{
errno = ENOMEM;
8001330: f002 faaa bl 8003888 <__errno>
8001334: 4603 mov r3, r0
8001336: 220c movs r2, #12
8001338: 601a str r2, [r3, #0]
return (void *)-1;
800133a: f04f 33ff mov.w r3, #4294967295
800133e: e009 b.n 8001354 <_sbrk+0x54>
}
prev_heap_end = __sbrk_heap_end;
8001340: 4b08 ldr r3, [pc, #32] @ (8001364 <_sbrk+0x64>)
8001342: 681b ldr r3, [r3, #0]
8001344: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
8001346: 4b07 ldr r3, [pc, #28] @ (8001364 <_sbrk+0x64>)
8001348: 681a ldr r2, [r3, #0]
800134a: 687b ldr r3, [r7, #4]
800134c: 4413 add r3, r2
800134e: 4a05 ldr r2, [pc, #20] @ (8001364 <_sbrk+0x64>)
8001350: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
8001352: 68fb ldr r3, [r7, #12]
}
8001354: 4618 mov r0, r3
8001356: 3718 adds r7, #24
8001358: 46bd mov sp, r7
800135a: bd80 pop {r7, pc}
800135c: 20020000 .word 0x20020000
8001360: 00000800 .word 0x00000800
8001364: 20000658 .word 0x20000658
8001368: 200007b0 .word 0x200007b0
0800136c <SystemInit>:
* @brief Setup the microcontroller system.
* @retval None
*/
void SystemInit(void)
{
800136c: b480 push {r7}
800136e: af00 add r7, sp, #0
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
#endif
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
8001370: 4b06 ldr r3, [pc, #24] @ (800138c <SystemInit+0x20>)
8001372: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8001376: 4a05 ldr r2, [pc, #20] @ (800138c <SystemInit+0x20>)
8001378: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
800137c: f8c2 3088 str.w r3, [r2, #136] @ 0x88
#endif
}
8001380: bf00 nop
8001382: 46bd mov sp, r7
8001384: f85d 7b04 ldr.w r7, [sp], #4
8001388: 4770 bx lr
800138a: bf00 nop
800138c: e000ed00 .word 0xe000ed00
08001390 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
8001390: f8df d034 ldr.w sp, [pc, #52] @ 80013c8 <LoopForever+0x2>
/* Call the clock system initialization function.*/
bl SystemInit
8001394: f7ff ffea bl 800136c <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8001398: 480c ldr r0, [pc, #48] @ (80013cc <LoopForever+0x6>)
ldr r1, =_edata
800139a: 490d ldr r1, [pc, #52] @ (80013d0 <LoopForever+0xa>)
ldr r2, =_sidata
800139c: 4a0d ldr r2, [pc, #52] @ (80013d4 <LoopForever+0xe>)
movs r3, #0
800139e: 2300 movs r3, #0
b LoopCopyDataInit
80013a0: e002 b.n 80013a8 <LoopCopyDataInit>
080013a2 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
80013a2: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
80013a4: 50c4 str r4, [r0, r3]
adds r3, r3, #4
80013a6: 3304 adds r3, #4
080013a8 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
80013a8: 18c4 adds r4, r0, r3
cmp r4, r1
80013aa: 428c cmp r4, r1
bcc CopyDataInit
80013ac: d3f9 bcc.n 80013a2 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
80013ae: 4a0a ldr r2, [pc, #40] @ (80013d8 <LoopForever+0x12>)
ldr r4, =_ebss
80013b0: 4c0a ldr r4, [pc, #40] @ (80013dc <LoopForever+0x16>)
movs r3, #0
80013b2: 2300 movs r3, #0
b LoopFillZerobss
80013b4: e001 b.n 80013ba <LoopFillZerobss>
080013b6 <FillZerobss>:
FillZerobss:
str r3, [r2]
80013b6: 6013 str r3, [r2, #0]
adds r2, r2, #4
80013b8: 3204 adds r2, #4
080013ba <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
80013ba: 42a2 cmp r2, r4
bcc FillZerobss
80013bc: d3fb bcc.n 80013b6 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
80013be: f002 fa69 bl 8003894 <__libc_init_array>
/* Call the application's entry point.*/
bl main
80013c2: f7ff fdb5 bl 8000f30 <main>
080013c6 <LoopForever>:
LoopForever:
b LoopForever
80013c6: e7fe b.n 80013c6 <LoopForever>
ldr sp, =_estack /* Set stack pointer */
80013c8: 20020000 .word 0x20020000
ldr r0, =_sdata
80013cc: 20000000 .word 0x20000000
ldr r1, =_edata
80013d0: 200001d4 .word 0x200001d4
ldr r2, =_sidata
80013d4: 08005a0c .word 0x08005a0c
ldr r2, =_sbss
80013d8: 200001d4 .word 0x200001d4
ldr r4, =_ebss
80013dc: 200007ac .word 0x200007ac
080013e0 <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80013e0: e7fe b.n 80013e0 <ADC1_IRQHandler>
...
080013e4 <HAL_Init>:
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80013e4: b580 push {r7, lr}
80013e6: b082 sub sp, #8
80013e8: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
80013ea: 2300 movs r3, #0
80013ec: 71fb strb r3, [r7, #7]
#if (DATA_CACHE_ENABLE == 0)
__HAL_FLASH_DATA_CACHE_DISABLE();
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
80013ee: 4b0c ldr r3, [pc, #48] @ (8001420 <HAL_Init+0x3c>)
80013f0: 681b ldr r3, [r3, #0]
80013f2: 4a0b ldr r2, [pc, #44] @ (8001420 <HAL_Init+0x3c>)
80013f4: f443 7380 orr.w r3, r3, #256 @ 0x100
80013f8: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
80013fa: 2003 movs r0, #3
80013fc: f000 f944 bl 8001688 <HAL_NVIC_SetPriorityGrouping>
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
8001400: 2000 movs r0, #0
8001402: f000 f80f bl 8001424 <HAL_InitTick>
8001406: 4603 mov r3, r0
8001408: 2b00 cmp r3, #0
800140a: d002 beq.n 8001412 <HAL_Init+0x2e>
{
status = HAL_ERROR;
800140c: 2301 movs r3, #1
800140e: 71fb strb r3, [r7, #7]
8001410: e001 b.n 8001416 <HAL_Init+0x32>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
8001412: f7ff fe4d bl 80010b0 <HAL_MspInit>
}
/* Return function status */
return status;
8001416: 79fb ldrb r3, [r7, #7]
}
8001418: 4618 mov r0, r3
800141a: 3708 adds r7, #8
800141c: 46bd mov sp, r7
800141e: bd80 pop {r7, pc}
8001420: 40022000 .word 0x40022000
08001424 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8001424: b580 push {r7, lr}
8001426: b084 sub sp, #16
8001428: af00 add r7, sp, #0
800142a: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
800142c: 2300 movs r3, #0
800142e: 73fb strb r3, [r7, #15]
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
if ((uint32_t)uwTickFreq != 0U)
8001430: 4b17 ldr r3, [pc, #92] @ (8001490 <HAL_InitTick+0x6c>)
8001432: 781b ldrb r3, [r3, #0]
8001434: 2b00 cmp r3, #0
8001436: d023 beq.n 8001480 <HAL_InitTick+0x5c>
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
8001438: 4b16 ldr r3, [pc, #88] @ (8001494 <HAL_InitTick+0x70>)
800143a: 681a ldr r2, [r3, #0]
800143c: 4b14 ldr r3, [pc, #80] @ (8001490 <HAL_InitTick+0x6c>)
800143e: 781b ldrb r3, [r3, #0]
8001440: 4619 mov r1, r3
8001442: f44f 737a mov.w r3, #1000 @ 0x3e8
8001446: fbb3 f3f1 udiv r3, r3, r1
800144a: fbb2 f3f3 udiv r3, r2, r3
800144e: 4618 mov r0, r3
8001450: f000 f941 bl 80016d6 <HAL_SYSTICK_Config>
8001454: 4603 mov r3, r0
8001456: 2b00 cmp r3, #0
8001458: d10f bne.n 800147a <HAL_InitTick+0x56>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
800145a: 687b ldr r3, [r7, #4]
800145c: 2b0f cmp r3, #15
800145e: d809 bhi.n 8001474 <HAL_InitTick+0x50>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8001460: 2200 movs r2, #0
8001462: 6879 ldr r1, [r7, #4]
8001464: f04f 30ff mov.w r0, #4294967295
8001468: f000 f919 bl 800169e <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
800146c: 4a0a ldr r2, [pc, #40] @ (8001498 <HAL_InitTick+0x74>)
800146e: 687b ldr r3, [r7, #4]
8001470: 6013 str r3, [r2, #0]
8001472: e007 b.n 8001484 <HAL_InitTick+0x60>
}
else
{
status = HAL_ERROR;
8001474: 2301 movs r3, #1
8001476: 73fb strb r3, [r7, #15]
8001478: e004 b.n 8001484 <HAL_InitTick+0x60>
}
}
else
{
status = HAL_ERROR;
800147a: 2301 movs r3, #1
800147c: 73fb strb r3, [r7, #15]
800147e: e001 b.n 8001484 <HAL_InitTick+0x60>
}
}
else
{
status = HAL_ERROR;
8001480: 2301 movs r3, #1
8001482: 73fb strb r3, [r7, #15]
}
/* Return function status */
return status;
8001484: 7bfb ldrb r3, [r7, #15]
}
8001486: 4618 mov r0, r3
8001488: 3710 adds r7, #16
800148a: 46bd mov sp, r7
800148c: bd80 pop {r7, pc}
800148e: bf00 nop
8001490: 20000008 .word 0x20000008
8001494: 20000000 .word 0x20000000
8001498: 20000004 .word 0x20000004
0800149c <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
800149c: b480 push {r7}
800149e: af00 add r7, sp, #0
uwTick += (uint32_t)uwTickFreq;
80014a0: 4b06 ldr r3, [pc, #24] @ (80014bc <HAL_IncTick+0x20>)
80014a2: 781b ldrb r3, [r3, #0]
80014a4: 461a mov r2, r3
80014a6: 4b06 ldr r3, [pc, #24] @ (80014c0 <HAL_IncTick+0x24>)
80014a8: 681b ldr r3, [r3, #0]
80014aa: 4413 add r3, r2
80014ac: 4a04 ldr r2, [pc, #16] @ (80014c0 <HAL_IncTick+0x24>)
80014ae: 6013 str r3, [r2, #0]
}
80014b0: bf00 nop
80014b2: 46bd mov sp, r7
80014b4: f85d 7b04 ldr.w r7, [sp], #4
80014b8: 4770 bx lr
80014ba: bf00 nop
80014bc: 20000008 .word 0x20000008
80014c0: 2000065c .word 0x2000065c
080014c4 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80014c4: b480 push {r7}
80014c6: af00 add r7, sp, #0
return uwTick;
80014c8: 4b03 ldr r3, [pc, #12] @ (80014d8 <HAL_GetTick+0x14>)
80014ca: 681b ldr r3, [r3, #0]
}
80014cc: 4618 mov r0, r3
80014ce: 46bd mov sp, r7
80014d0: f85d 7b04 ldr.w r7, [sp], #4
80014d4: 4770 bx lr
80014d6: bf00 nop
80014d8: 2000065c .word 0x2000065c
080014dc <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
80014dc: b580 push {r7, lr}
80014de: b084 sub sp, #16
80014e0: af00 add r7, sp, #0
80014e2: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
80014e4: f7ff ffee bl 80014c4 <HAL_GetTick>
80014e8: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
80014ea: 687b ldr r3, [r7, #4]
80014ec: 60fb str r3, [r7, #12]
/* Add a period to guaranty minimum wait */
if (wait < HAL_MAX_DELAY)
80014ee: 68fb ldr r3, [r7, #12]
80014f0: f1b3 3fff cmp.w r3, #4294967295
80014f4: d005 beq.n 8001502 <HAL_Delay+0x26>
{
wait += (uint32_t)uwTickFreq;
80014f6: 4b0a ldr r3, [pc, #40] @ (8001520 <HAL_Delay+0x44>)
80014f8: 781b ldrb r3, [r3, #0]
80014fa: 461a mov r2, r3
80014fc: 68fb ldr r3, [r7, #12]
80014fe: 4413 add r3, r2
8001500: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
8001502: bf00 nop
8001504: f7ff ffde bl 80014c4 <HAL_GetTick>
8001508: 4602 mov r2, r0
800150a: 68bb ldr r3, [r7, #8]
800150c: 1ad3 subs r3, r2, r3
800150e: 68fa ldr r2, [r7, #12]
8001510: 429a cmp r2, r3
8001512: d8f7 bhi.n 8001504 <HAL_Delay+0x28>
{
}
}
8001514: bf00 nop
8001516: bf00 nop
8001518: 3710 adds r7, #16
800151a: 46bd mov sp, r7
800151c: bd80 pop {r7, pc}
800151e: bf00 nop
8001520: 20000008 .word 0x20000008
08001524 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001524: b480 push {r7}
8001526: b085 sub sp, #20
8001528: af00 add r7, sp, #0
800152a: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
800152c: 687b ldr r3, [r7, #4]
800152e: f003 0307 and.w r3, r3, #7
8001532: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8001534: 4b0c ldr r3, [pc, #48] @ (8001568 <__NVIC_SetPriorityGrouping+0x44>)
8001536: 68db ldr r3, [r3, #12]
8001538: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
800153a: 68ba ldr r2, [r7, #8]
800153c: f64f 03ff movw r3, #63743 @ 0xf8ff
8001540: 4013 ands r3, r2
8001542: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8001544: 68fb ldr r3, [r7, #12]
8001546: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8001548: 68bb ldr r3, [r7, #8]
800154a: 4313 orrs r3, r2
reg_value = (reg_value |
800154c: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8001550: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8001554: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8001556: 4a04 ldr r2, [pc, #16] @ (8001568 <__NVIC_SetPriorityGrouping+0x44>)
8001558: 68bb ldr r3, [r7, #8]
800155a: 60d3 str r3, [r2, #12]
}
800155c: bf00 nop
800155e: 3714 adds r7, #20
8001560: 46bd mov sp, r7
8001562: f85d 7b04 ldr.w r7, [sp], #4
8001566: 4770 bx lr
8001568: e000ed00 .word 0xe000ed00
0800156c <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
800156c: b480 push {r7}
800156e: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8001570: 4b04 ldr r3, [pc, #16] @ (8001584 <__NVIC_GetPriorityGrouping+0x18>)
8001572: 68db ldr r3, [r3, #12]
8001574: 0a1b lsrs r3, r3, #8
8001576: f003 0307 and.w r3, r3, #7
}
800157a: 4618 mov r0, r3
800157c: 46bd mov sp, r7
800157e: f85d 7b04 ldr.w r7, [sp], #4
8001582: 4770 bx lr
8001584: e000ed00 .word 0xe000ed00
08001588 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8001588: b480 push {r7}
800158a: b083 sub sp, #12
800158c: af00 add r7, sp, #0
800158e: 4603 mov r3, r0
8001590: 6039 str r1, [r7, #0]
8001592: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8001594: f997 3007 ldrsb.w r3, [r7, #7]
8001598: 2b00 cmp r3, #0
800159a: db0a blt.n 80015b2 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800159c: 683b ldr r3, [r7, #0]
800159e: b2da uxtb r2, r3
80015a0: 490c ldr r1, [pc, #48] @ (80015d4 <__NVIC_SetPriority+0x4c>)
80015a2: f997 3007 ldrsb.w r3, [r7, #7]
80015a6: 0112 lsls r2, r2, #4
80015a8: b2d2 uxtb r2, r2
80015aa: 440b add r3, r1
80015ac: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
80015b0: e00a b.n 80015c8 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80015b2: 683b ldr r3, [r7, #0]
80015b4: b2da uxtb r2, r3
80015b6: 4908 ldr r1, [pc, #32] @ (80015d8 <__NVIC_SetPriority+0x50>)
80015b8: 79fb ldrb r3, [r7, #7]
80015ba: f003 030f and.w r3, r3, #15
80015be: 3b04 subs r3, #4
80015c0: 0112 lsls r2, r2, #4
80015c2: b2d2 uxtb r2, r2
80015c4: 440b add r3, r1
80015c6: 761a strb r2, [r3, #24]
}
80015c8: bf00 nop
80015ca: 370c adds r7, #12
80015cc: 46bd mov sp, r7
80015ce: f85d 7b04 ldr.w r7, [sp], #4
80015d2: 4770 bx lr
80015d4: e000e100 .word 0xe000e100
80015d8: e000ed00 .word 0xe000ed00
080015dc <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80015dc: b480 push {r7}
80015de: b089 sub sp, #36 @ 0x24
80015e0: af00 add r7, sp, #0
80015e2: 60f8 str r0, [r7, #12]
80015e4: 60b9 str r1, [r7, #8]
80015e6: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80015e8: 68fb ldr r3, [r7, #12]
80015ea: f003 0307 and.w r3, r3, #7
80015ee: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80015f0: 69fb ldr r3, [r7, #28]
80015f2: f1c3 0307 rsb r3, r3, #7
80015f6: 2b04 cmp r3, #4
80015f8: bf28 it cs
80015fa: 2304 movcs r3, #4
80015fc: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80015fe: 69fb ldr r3, [r7, #28]
8001600: 3304 adds r3, #4
8001602: 2b06 cmp r3, #6
8001604: d902 bls.n 800160c <NVIC_EncodePriority+0x30>
8001606: 69fb ldr r3, [r7, #28]
8001608: 3b03 subs r3, #3
800160a: e000 b.n 800160e <NVIC_EncodePriority+0x32>
800160c: 2300 movs r3, #0
800160e: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001610: f04f 32ff mov.w r2, #4294967295
8001614: 69bb ldr r3, [r7, #24]
8001616: fa02 f303 lsl.w r3, r2, r3
800161a: 43da mvns r2, r3
800161c: 68bb ldr r3, [r7, #8]
800161e: 401a ands r2, r3
8001620: 697b ldr r3, [r7, #20]
8001622: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8001624: f04f 31ff mov.w r1, #4294967295
8001628: 697b ldr r3, [r7, #20]
800162a: fa01 f303 lsl.w r3, r1, r3
800162e: 43d9 mvns r1, r3
8001630: 687b ldr r3, [r7, #4]
8001632: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001634: 4313 orrs r3, r2
);
}
8001636: 4618 mov r0, r3
8001638: 3724 adds r7, #36 @ 0x24
800163a: 46bd mov sp, r7
800163c: f85d 7b04 ldr.w r7, [sp], #4
8001640: 4770 bx lr
...
08001644 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8001644: b580 push {r7, lr}
8001646: b082 sub sp, #8
8001648: af00 add r7, sp, #0
800164a: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
800164c: 687b ldr r3, [r7, #4]
800164e: 3b01 subs r3, #1
8001650: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8001654: d301 bcc.n 800165a <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8001656: 2301 movs r3, #1
8001658: e00f b.n 800167a <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
800165a: 4a0a ldr r2, [pc, #40] @ (8001684 <SysTick_Config+0x40>)
800165c: 687b ldr r3, [r7, #4]
800165e: 3b01 subs r3, #1
8001660: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8001662: 210f movs r1, #15
8001664: f04f 30ff mov.w r0, #4294967295
8001668: f7ff ff8e bl 8001588 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
800166c: 4b05 ldr r3, [pc, #20] @ (8001684 <SysTick_Config+0x40>)
800166e: 2200 movs r2, #0
8001670: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8001672: 4b04 ldr r3, [pc, #16] @ (8001684 <SysTick_Config+0x40>)
8001674: 2207 movs r2, #7
8001676: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8001678: 2300 movs r3, #0
}
800167a: 4618 mov r0, r3
800167c: 3708 adds r7, #8
800167e: 46bd mov sp, r7
8001680: bd80 pop {r7, pc}
8001682: bf00 nop
8001684: e000e010 .word 0xe000e010
08001688 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001688: b580 push {r7, lr}
800168a: b082 sub sp, #8
800168c: af00 add r7, sp, #0
800168e: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8001690: 6878 ldr r0, [r7, #4]
8001692: f7ff ff47 bl 8001524 <__NVIC_SetPriorityGrouping>
}
8001696: bf00 nop
8001698: 3708 adds r7, #8
800169a: 46bd mov sp, r7
800169c: bd80 pop {r7, pc}
0800169e <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
800169e: b580 push {r7, lr}
80016a0: b086 sub sp, #24
80016a2: af00 add r7, sp, #0
80016a4: 4603 mov r3, r0
80016a6: 60b9 str r1, [r7, #8]
80016a8: 607a str r2, [r7, #4]
80016aa: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
80016ac: 2300 movs r3, #0
80016ae: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
80016b0: f7ff ff5c bl 800156c <__NVIC_GetPriorityGrouping>
80016b4: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
80016b6: 687a ldr r2, [r7, #4]
80016b8: 68b9 ldr r1, [r7, #8]
80016ba: 6978 ldr r0, [r7, #20]
80016bc: f7ff ff8e bl 80015dc <NVIC_EncodePriority>
80016c0: 4602 mov r2, r0
80016c2: f997 300f ldrsb.w r3, [r7, #15]
80016c6: 4611 mov r1, r2
80016c8: 4618 mov r0, r3
80016ca: f7ff ff5d bl 8001588 <__NVIC_SetPriority>
}
80016ce: bf00 nop
80016d0: 3718 adds r7, #24
80016d2: 46bd mov sp, r7
80016d4: bd80 pop {r7, pc}
080016d6 <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80016d6: b580 push {r7, lr}
80016d8: b082 sub sp, #8
80016da: af00 add r7, sp, #0
80016dc: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
80016de: 6878 ldr r0, [r7, #4]
80016e0: f7ff ffb0 bl 8001644 <SysTick_Config>
80016e4: 4603 mov r3, r0
}
80016e6: 4618 mov r0, r3
80016e8: 3708 adds r7, #8
80016ea: 46bd mov sp, r7
80016ec: bd80 pop {r7, pc}
...
080016f0 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80016f0: b480 push {r7}
80016f2: b087 sub sp, #28
80016f4: af00 add r7, sp, #0
80016f6: 6078 str r0, [r7, #4]
80016f8: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
80016fa: 2300 movs r3, #0
80016fc: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
80016fe: e154 b.n 80019aa <HAL_GPIO_Init+0x2ba>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
8001700: 683b ldr r3, [r7, #0]
8001702: 681a ldr r2, [r3, #0]
8001704: 2101 movs r1, #1
8001706: 697b ldr r3, [r7, #20]
8001708: fa01 f303 lsl.w r3, r1, r3
800170c: 4013 ands r3, r2
800170e: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8001710: 68fb ldr r3, [r7, #12]
8001712: 2b00 cmp r3, #0
8001714: f000 8146 beq.w 80019a4 <HAL_GPIO_Init+0x2b4>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8001718: 683b ldr r3, [r7, #0]
800171a: 685b ldr r3, [r3, #4]
800171c: f003 0303 and.w r3, r3, #3
8001720: 2b01 cmp r3, #1
8001722: d005 beq.n 8001730 <HAL_GPIO_Init+0x40>
8001724: 683b ldr r3, [r7, #0]
8001726: 685b ldr r3, [r3, #4]
8001728: f003 0303 and.w r3, r3, #3
800172c: 2b02 cmp r3, #2
800172e: d130 bne.n 8001792 <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8001730: 687b ldr r3, [r7, #4]
8001732: 689b ldr r3, [r3, #8]
8001734: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
8001736: 697b ldr r3, [r7, #20]
8001738: 005b lsls r3, r3, #1
800173a: 2203 movs r2, #3
800173c: fa02 f303 lsl.w r3, r2, r3
8001740: 43db mvns r3, r3
8001742: 693a ldr r2, [r7, #16]
8001744: 4013 ands r3, r2
8001746: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
8001748: 683b ldr r3, [r7, #0]
800174a: 68da ldr r2, [r3, #12]
800174c: 697b ldr r3, [r7, #20]
800174e: 005b lsls r3, r3, #1
8001750: fa02 f303 lsl.w r3, r2, r3
8001754: 693a ldr r2, [r7, #16]
8001756: 4313 orrs r3, r2
8001758: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
800175a: 687b ldr r3, [r7, #4]
800175c: 693a ldr r2, [r7, #16]
800175e: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001760: 687b ldr r3, [r7, #4]
8001762: 685b ldr r3, [r3, #4]
8001764: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT0 << position) ;
8001766: 2201 movs r2, #1
8001768: 697b ldr r3, [r7, #20]
800176a: fa02 f303 lsl.w r3, r2, r3
800176e: 43db mvns r3, r3
8001770: 693a ldr r2, [r7, #16]
8001772: 4013 ands r3, r2
8001774: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8001776: 683b ldr r3, [r7, #0]
8001778: 685b ldr r3, [r3, #4]
800177a: 091b lsrs r3, r3, #4
800177c: f003 0201 and.w r2, r3, #1
8001780: 697b ldr r3, [r7, #20]
8001782: fa02 f303 lsl.w r3, r2, r3
8001786: 693a ldr r2, [r7, #16]
8001788: 4313 orrs r3, r2
800178a: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
800178c: 687b ldr r3, [r7, #4]
800178e: 693a ldr r2, [r7, #16]
8001790: 605a str r2, [r3, #4]
}
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
/* Activate the Pull-up or Pull down resistor for the current IO */
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8001792: 683b ldr r3, [r7, #0]
8001794: 685b ldr r3, [r3, #4]
8001796: f003 0303 and.w r3, r3, #3
800179a: 2b03 cmp r3, #3
800179c: d017 beq.n 80017ce <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
temp = GPIOx->PUPDR;
800179e: 687b ldr r3, [r7, #4]
80017a0: 68db ldr r3, [r3, #12]
80017a2: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
80017a4: 697b ldr r3, [r7, #20]
80017a6: 005b lsls r3, r3, #1
80017a8: 2203 movs r2, #3
80017aa: fa02 f303 lsl.w r3, r2, r3
80017ae: 43db mvns r3, r3
80017b0: 693a ldr r2, [r7, #16]
80017b2: 4013 ands r3, r2
80017b4: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2U));
80017b6: 683b ldr r3, [r7, #0]
80017b8: 689a ldr r2, [r3, #8]
80017ba: 697b ldr r3, [r7, #20]
80017bc: 005b lsls r3, r3, #1
80017be: fa02 f303 lsl.w r3, r2, r3
80017c2: 693a ldr r2, [r7, #16]
80017c4: 4313 orrs r3, r2
80017c6: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
80017c8: 687b ldr r3, [r7, #4]
80017ca: 693a ldr r2, [r7, #16]
80017cc: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80017ce: 683b ldr r3, [r7, #0]
80017d0: 685b ldr r3, [r3, #4]
80017d2: f003 0303 and.w r3, r3, #3
80017d6: 2b02 cmp r3, #2
80017d8: d123 bne.n 8001822 <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
80017da: 697b ldr r3, [r7, #20]
80017dc: 08da lsrs r2, r3, #3
80017de: 687b ldr r3, [r7, #4]
80017e0: 3208 adds r2, #8
80017e2: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80017e6: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
80017e8: 697b ldr r3, [r7, #20]
80017ea: f003 0307 and.w r3, r3, #7
80017ee: 009b lsls r3, r3, #2
80017f0: 220f movs r2, #15
80017f2: fa02 f303 lsl.w r3, r2, r3
80017f6: 43db mvns r3, r3
80017f8: 693a ldr r2, [r7, #16]
80017fa: 4013 ands r3, r2
80017fc: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
80017fe: 683b ldr r3, [r7, #0]
8001800: 691a ldr r2, [r3, #16]
8001802: 697b ldr r3, [r7, #20]
8001804: f003 0307 and.w r3, r3, #7
8001808: 009b lsls r3, r3, #2
800180a: fa02 f303 lsl.w r3, r2, r3
800180e: 693a ldr r2, [r7, #16]
8001810: 4313 orrs r3, r2
8001812: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
8001814: 697b ldr r3, [r7, #20]
8001816: 08da lsrs r2, r3, #3
8001818: 687b ldr r3, [r7, #4]
800181a: 3208 adds r2, #8
800181c: 6939 ldr r1, [r7, #16]
800181e: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8001822: 687b ldr r3, [r7, #4]
8001824: 681b ldr r3, [r3, #0]
8001826: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
8001828: 697b ldr r3, [r7, #20]
800182a: 005b lsls r3, r3, #1
800182c: 2203 movs r2, #3
800182e: fa02 f303 lsl.w r3, r2, r3
8001832: 43db mvns r3, r3
8001834: 693a ldr r2, [r7, #16]
8001836: 4013 ands r3, r2
8001838: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
800183a: 683b ldr r3, [r7, #0]
800183c: 685b ldr r3, [r3, #4]
800183e: f003 0203 and.w r2, r3, #3
8001842: 697b ldr r3, [r7, #20]
8001844: 005b lsls r3, r3, #1
8001846: fa02 f303 lsl.w r3, r2, r3
800184a: 693a ldr r2, [r7, #16]
800184c: 4313 orrs r3, r2
800184e: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8001850: 687b ldr r3, [r7, #4]
8001852: 693a ldr r2, [r7, #16]
8001854: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8001856: 683b ldr r3, [r7, #0]
8001858: 685b ldr r3, [r3, #4]
800185a: f403 3340 and.w r3, r3, #196608 @ 0x30000
800185e: 2b00 cmp r3, #0
8001860: f000 80a0 beq.w 80019a4 <HAL_GPIO_Init+0x2b4>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001864: 4b58 ldr r3, [pc, #352] @ (80019c8 <HAL_GPIO_Init+0x2d8>)
8001866: 6e1b ldr r3, [r3, #96] @ 0x60
8001868: 4a57 ldr r2, [pc, #348] @ (80019c8 <HAL_GPIO_Init+0x2d8>)
800186a: f043 0301 orr.w r3, r3, #1
800186e: 6613 str r3, [r2, #96] @ 0x60
8001870: 4b55 ldr r3, [pc, #340] @ (80019c8 <HAL_GPIO_Init+0x2d8>)
8001872: 6e1b ldr r3, [r3, #96] @ 0x60
8001874: f003 0301 and.w r3, r3, #1
8001878: 60bb str r3, [r7, #8]
800187a: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
800187c: 4a53 ldr r2, [pc, #332] @ (80019cc <HAL_GPIO_Init+0x2dc>)
800187e: 697b ldr r3, [r7, #20]
8001880: 089b lsrs r3, r3, #2
8001882: 3302 adds r3, #2
8001884: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001888: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
800188a: 697b ldr r3, [r7, #20]
800188c: f003 0303 and.w r3, r3, #3
8001890: 009b lsls r3, r3, #2
8001892: 220f movs r2, #15
8001894: fa02 f303 lsl.w r3, r2, r3
8001898: 43db mvns r3, r3
800189a: 693a ldr r2, [r7, #16]
800189c: 4013 ands r3, r2
800189e: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
80018a0: 687b ldr r3, [r7, #4]
80018a2: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
80018a6: d019 beq.n 80018dc <HAL_GPIO_Init+0x1ec>
80018a8: 687b ldr r3, [r7, #4]
80018aa: 4a49 ldr r2, [pc, #292] @ (80019d0 <HAL_GPIO_Init+0x2e0>)
80018ac: 4293 cmp r3, r2
80018ae: d013 beq.n 80018d8 <HAL_GPIO_Init+0x1e8>
80018b0: 687b ldr r3, [r7, #4]
80018b2: 4a48 ldr r2, [pc, #288] @ (80019d4 <HAL_GPIO_Init+0x2e4>)
80018b4: 4293 cmp r3, r2
80018b6: d00d beq.n 80018d4 <HAL_GPIO_Init+0x1e4>
80018b8: 687b ldr r3, [r7, #4]
80018ba: 4a47 ldr r2, [pc, #284] @ (80019d8 <HAL_GPIO_Init+0x2e8>)
80018bc: 4293 cmp r3, r2
80018be: d007 beq.n 80018d0 <HAL_GPIO_Init+0x1e0>
80018c0: 687b ldr r3, [r7, #4]
80018c2: 4a46 ldr r2, [pc, #280] @ (80019dc <HAL_GPIO_Init+0x2ec>)
80018c4: 4293 cmp r3, r2
80018c6: d101 bne.n 80018cc <HAL_GPIO_Init+0x1dc>
80018c8: 2304 movs r3, #4
80018ca: e008 b.n 80018de <HAL_GPIO_Init+0x1ee>
80018cc: 2307 movs r3, #7
80018ce: e006 b.n 80018de <HAL_GPIO_Init+0x1ee>
80018d0: 2303 movs r3, #3
80018d2: e004 b.n 80018de <HAL_GPIO_Init+0x1ee>
80018d4: 2302 movs r3, #2
80018d6: e002 b.n 80018de <HAL_GPIO_Init+0x1ee>
80018d8: 2301 movs r3, #1
80018da: e000 b.n 80018de <HAL_GPIO_Init+0x1ee>
80018dc: 2300 movs r3, #0
80018de: 697a ldr r2, [r7, #20]
80018e0: f002 0203 and.w r2, r2, #3
80018e4: 0092 lsls r2, r2, #2
80018e6: 4093 lsls r3, r2
80018e8: 693a ldr r2, [r7, #16]
80018ea: 4313 orrs r3, r2
80018ec: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
80018ee: 4937 ldr r1, [pc, #220] @ (80019cc <HAL_GPIO_Init+0x2dc>)
80018f0: 697b ldr r3, [r7, #20]
80018f2: 089b lsrs r3, r3, #2
80018f4: 3302 adds r3, #2
80018f6: 693a ldr r2, [r7, #16]
80018f8: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
80018fc: 4b38 ldr r3, [pc, #224] @ (80019e0 <HAL_GPIO_Init+0x2f0>)
80018fe: 689b ldr r3, [r3, #8]
8001900: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001902: 68fb ldr r3, [r7, #12]
8001904: 43db mvns r3, r3
8001906: 693a ldr r2, [r7, #16]
8001908: 4013 ands r3, r2
800190a: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
800190c: 683b ldr r3, [r7, #0]
800190e: 685b ldr r3, [r3, #4]
8001910: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8001914: 2b00 cmp r3, #0
8001916: d003 beq.n 8001920 <HAL_GPIO_Init+0x230>
{
temp |= iocurrent;
8001918: 693a ldr r2, [r7, #16]
800191a: 68fb ldr r3, [r7, #12]
800191c: 4313 orrs r3, r2
800191e: 613b str r3, [r7, #16]
}
EXTI->RTSR1 = temp;
8001920: 4a2f ldr r2, [pc, #188] @ (80019e0 <HAL_GPIO_Init+0x2f0>)
8001922: 693b ldr r3, [r7, #16]
8001924: 6093 str r3, [r2, #8]
temp = EXTI->FTSR1;
8001926: 4b2e ldr r3, [pc, #184] @ (80019e0 <HAL_GPIO_Init+0x2f0>)
8001928: 68db ldr r3, [r3, #12]
800192a: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800192c: 68fb ldr r3, [r7, #12]
800192e: 43db mvns r3, r3
8001930: 693a ldr r2, [r7, #16]
8001932: 4013 ands r3, r2
8001934: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8001936: 683b ldr r3, [r7, #0]
8001938: 685b ldr r3, [r3, #4]
800193a: f403 1300 and.w r3, r3, #2097152 @ 0x200000
800193e: 2b00 cmp r3, #0
8001940: d003 beq.n 800194a <HAL_GPIO_Init+0x25a>
{
temp |= iocurrent;
8001942: 693a ldr r2, [r7, #16]
8001944: 68fb ldr r3, [r7, #12]
8001946: 4313 orrs r3, r2
8001948: 613b str r3, [r7, #16]
}
EXTI->FTSR1 = temp;
800194a: 4a25 ldr r2, [pc, #148] @ (80019e0 <HAL_GPIO_Init+0x2f0>)
800194c: 693b ldr r3, [r7, #16]
800194e: 60d3 str r3, [r2, #12]
/* Clear EXTI line configuration */
temp = EXTI->EMR1;
8001950: 4b23 ldr r3, [pc, #140] @ (80019e0 <HAL_GPIO_Init+0x2f0>)
8001952: 685b ldr r3, [r3, #4]
8001954: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001956: 68fb ldr r3, [r7, #12]
8001958: 43db mvns r3, r3
800195a: 693a ldr r2, [r7, #16]
800195c: 4013 ands r3, r2
800195e: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8001960: 683b ldr r3, [r7, #0]
8001962: 685b ldr r3, [r3, #4]
8001964: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001968: 2b00 cmp r3, #0
800196a: d003 beq.n 8001974 <HAL_GPIO_Init+0x284>
{
temp |= iocurrent;
800196c: 693a ldr r2, [r7, #16]
800196e: 68fb ldr r3, [r7, #12]
8001970: 4313 orrs r3, r2
8001972: 613b str r3, [r7, #16]
}
EXTI->EMR1 = temp;
8001974: 4a1a ldr r2, [pc, #104] @ (80019e0 <HAL_GPIO_Init+0x2f0>)
8001976: 693b ldr r3, [r7, #16]
8001978: 6053 str r3, [r2, #4]
temp = EXTI->IMR1;
800197a: 4b19 ldr r3, [pc, #100] @ (80019e0 <HAL_GPIO_Init+0x2f0>)
800197c: 681b ldr r3, [r3, #0]
800197e: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001980: 68fb ldr r3, [r7, #12]
8001982: 43db mvns r3, r3
8001984: 693a ldr r2, [r7, #16]
8001986: 4013 ands r3, r2
8001988: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
800198a: 683b ldr r3, [r7, #0]
800198c: 685b ldr r3, [r3, #4]
800198e: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001992: 2b00 cmp r3, #0
8001994: d003 beq.n 800199e <HAL_GPIO_Init+0x2ae>
{
temp |= iocurrent;
8001996: 693a ldr r2, [r7, #16]
8001998: 68fb ldr r3, [r7, #12]
800199a: 4313 orrs r3, r2
800199c: 613b str r3, [r7, #16]
}
EXTI->IMR1 = temp;
800199e: 4a10 ldr r2, [pc, #64] @ (80019e0 <HAL_GPIO_Init+0x2f0>)
80019a0: 693b ldr r3, [r7, #16]
80019a2: 6013 str r3, [r2, #0]
}
}
position++;
80019a4: 697b ldr r3, [r7, #20]
80019a6: 3301 adds r3, #1
80019a8: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
80019aa: 683b ldr r3, [r7, #0]
80019ac: 681a ldr r2, [r3, #0]
80019ae: 697b ldr r3, [r7, #20]
80019b0: fa22 f303 lsr.w r3, r2, r3
80019b4: 2b00 cmp r3, #0
80019b6: f47f aea3 bne.w 8001700 <HAL_GPIO_Init+0x10>
}
}
80019ba: bf00 nop
80019bc: bf00 nop
80019be: 371c adds r7, #28
80019c0: 46bd mov sp, r7
80019c2: f85d 7b04 ldr.w r7, [sp], #4
80019c6: 4770 bx lr
80019c8: 40021000 .word 0x40021000
80019cc: 40010000 .word 0x40010000
80019d0: 48000400 .word 0x48000400
80019d4: 48000800 .word 0x48000800
80019d8: 48000c00 .word 0x48000c00
80019dc: 48001000 .word 0x48001000
80019e0: 40010400 .word 0x40010400
080019e4 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
80019e4: b480 push {r7}
80019e6: b083 sub sp, #12
80019e8: af00 add r7, sp, #0
80019ea: 6078 str r0, [r7, #4]
80019ec: 460b mov r3, r1
80019ee: 807b strh r3, [r7, #2]
80019f0: 4613 mov r3, r2
80019f2: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
80019f4: 787b ldrb r3, [r7, #1]
80019f6: 2b00 cmp r3, #0
80019f8: d003 beq.n 8001a02 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
80019fa: 887a ldrh r2, [r7, #2]
80019fc: 687b ldr r3, [r7, #4]
80019fe: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
8001a00: e002 b.n 8001a08 <HAL_GPIO_WritePin+0x24>
GPIOx->BRR = (uint32_t)GPIO_Pin;
8001a02: 887a ldrh r2, [r7, #2]
8001a04: 687b ldr r3, [r7, #4]
8001a06: 629a str r2, [r3, #40] @ 0x28
}
8001a08: bf00 nop
8001a0a: 370c adds r7, #12
8001a0c: 46bd mov sp, r7
8001a0e: f85d 7b04 ldr.w r7, [sp], #4
8001a12: 4770 bx lr
08001a14 <HAL_PWREx_GetVoltageRange>:
* @brief Return Voltage Scaling Range.
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
* or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
*/
uint32_t HAL_PWREx_GetVoltageRange(void)
{
8001a14: b480 push {r7}
8001a16: af00 add r7, sp, #0
else
{
return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
}
#else
return (PWR->CR1 & PWR_CR1_VOS);
8001a18: 4b04 ldr r3, [pc, #16] @ (8001a2c <HAL_PWREx_GetVoltageRange+0x18>)
8001a1a: 681b ldr r3, [r3, #0]
8001a1c: f403 63c0 and.w r3, r3, #1536 @ 0x600
#endif
}
8001a20: 4618 mov r0, r3
8001a22: 46bd mov sp, r7
8001a24: f85d 7b04 ldr.w r7, [sp], #4
8001a28: 4770 bx lr
8001a2a: bf00 nop
8001a2c: 40007000 .word 0x40007000
08001a30 <HAL_RCC_OscConfig>:
* @note If HSE failed to start, HSE should be disabled before recalling
HAL_RCC_OscConfig().
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8001a30: b580 push {r7, lr}
8001a32: b088 sub sp, #32
8001a34: af00 add r7, sp, #0
8001a36: 6078 str r0, [r7, #4]
uint32_t tickstart;
HAL_StatusTypeDef status;
uint32_t sysclk_source, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8001a38: 687b ldr r3, [r7, #4]
8001a3a: 2b00 cmp r3, #0
8001a3c: d102 bne.n 8001a44 <HAL_RCC_OscConfig+0x14>
{
return HAL_ERROR;
8001a3e: 2301 movs r3, #1
8001a40: f000 bc02 b.w 8002248 <HAL_RCC_OscConfig+0x818>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
8001a44: 4b96 ldr r3, [pc, #600] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001a46: 689b ldr r3, [r3, #8]
8001a48: f003 030c and.w r3, r3, #12
8001a4c: 61bb str r3, [r7, #24]
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
8001a4e: 4b94 ldr r3, [pc, #592] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001a50: 68db ldr r3, [r3, #12]
8001a52: f003 0303 and.w r3, r3, #3
8001a56: 617b str r3, [r7, #20]
/*----------------------------- MSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
8001a58: 687b ldr r3, [r7, #4]
8001a5a: 681b ldr r3, [r3, #0]
8001a5c: f003 0310 and.w r3, r3, #16
8001a60: 2b00 cmp r3, #0
8001a62: f000 80e4 beq.w 8001c2e <HAL_RCC_OscConfig+0x1fe>
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
8001a66: 69bb ldr r3, [r7, #24]
8001a68: 2b00 cmp r3, #0
8001a6a: d007 beq.n 8001a7c <HAL_RCC_OscConfig+0x4c>
8001a6c: 69bb ldr r3, [r7, #24]
8001a6e: 2b0c cmp r3, #12
8001a70: f040 808b bne.w 8001b8a <HAL_RCC_OscConfig+0x15a>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))
8001a74: 697b ldr r3, [r7, #20]
8001a76: 2b01 cmp r3, #1
8001a78: f040 8087 bne.w 8001b8a <HAL_RCC_OscConfig+0x15a>
{
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
8001a7c: 4b88 ldr r3, [pc, #544] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001a7e: 681b ldr r3, [r3, #0]
8001a80: f003 0302 and.w r3, r3, #2
8001a84: 2b00 cmp r3, #0
8001a86: d005 beq.n 8001a94 <HAL_RCC_OscConfig+0x64>
8001a88: 687b ldr r3, [r7, #4]
8001a8a: 699b ldr r3, [r3, #24]
8001a8c: 2b00 cmp r3, #0
8001a8e: d101 bne.n 8001a94 <HAL_RCC_OscConfig+0x64>
{
return HAL_ERROR;
8001a90: 2301 movs r3, #1
8001a92: e3d9 b.n 8002248 <HAL_RCC_OscConfig+0x818>
else
{
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
8001a94: 687b ldr r3, [r7, #4]
8001a96: 6a1a ldr r2, [r3, #32]
8001a98: 4b81 ldr r3, [pc, #516] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001a9a: 681b ldr r3, [r3, #0]
8001a9c: f003 0308 and.w r3, r3, #8
8001aa0: 2b00 cmp r3, #0
8001aa2: d004 beq.n 8001aae <HAL_RCC_OscConfig+0x7e>
8001aa4: 4b7e ldr r3, [pc, #504] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001aa6: 681b ldr r3, [r3, #0]
8001aa8: f003 03f0 and.w r3, r3, #240 @ 0xf0
8001aac: e005 b.n 8001aba <HAL_RCC_OscConfig+0x8a>
8001aae: 4b7c ldr r3, [pc, #496] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001ab0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8001ab4: 091b lsrs r3, r3, #4
8001ab6: f003 03f0 and.w r3, r3, #240 @ 0xf0
8001aba: 4293 cmp r3, r2
8001abc: d223 bcs.n 8001b06 <HAL_RCC_OscConfig+0xd6>
{
/* First increase number of wait states update if necessary */
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
8001abe: 687b ldr r3, [r7, #4]
8001ac0: 6a1b ldr r3, [r3, #32]
8001ac2: 4618 mov r0, r3
8001ac4: f000 fd54 bl 8002570 <RCC_SetFlashLatencyFromMSIRange>
8001ac8: 4603 mov r3, r0
8001aca: 2b00 cmp r3, #0
8001acc: d001 beq.n 8001ad2 <HAL_RCC_OscConfig+0xa2>
{
return HAL_ERROR;
8001ace: 2301 movs r3, #1
8001ad0: e3ba b.n 8002248 <HAL_RCC_OscConfig+0x818>
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
8001ad2: 4b73 ldr r3, [pc, #460] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001ad4: 681b ldr r3, [r3, #0]
8001ad6: 4a72 ldr r2, [pc, #456] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001ad8: f043 0308 orr.w r3, r3, #8
8001adc: 6013 str r3, [r2, #0]
8001ade: 4b70 ldr r3, [pc, #448] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001ae0: 681b ldr r3, [r3, #0]
8001ae2: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8001ae6: 687b ldr r3, [r7, #4]
8001ae8: 6a1b ldr r3, [r3, #32]
8001aea: 496d ldr r1, [pc, #436] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001aec: 4313 orrs r3, r2
8001aee: 600b str r3, [r1, #0]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8001af0: 4b6b ldr r3, [pc, #428] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001af2: 685b ldr r3, [r3, #4]
8001af4: f423 427f bic.w r2, r3, #65280 @ 0xff00
8001af8: 687b ldr r3, [r7, #4]
8001afa: 69db ldr r3, [r3, #28]
8001afc: 021b lsls r3, r3, #8
8001afe: 4968 ldr r1, [pc, #416] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001b00: 4313 orrs r3, r2
8001b02: 604b str r3, [r1, #4]
8001b04: e025 b.n 8001b52 <HAL_RCC_OscConfig+0x122>
}
else
{
/* Else, keep current flash latency while decreasing applies */
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
8001b06: 4b66 ldr r3, [pc, #408] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001b08: 681b ldr r3, [r3, #0]
8001b0a: 4a65 ldr r2, [pc, #404] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001b0c: f043 0308 orr.w r3, r3, #8
8001b10: 6013 str r3, [r2, #0]
8001b12: 4b63 ldr r3, [pc, #396] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001b14: 681b ldr r3, [r3, #0]
8001b16: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8001b1a: 687b ldr r3, [r7, #4]
8001b1c: 6a1b ldr r3, [r3, #32]
8001b1e: 4960 ldr r1, [pc, #384] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001b20: 4313 orrs r3, r2
8001b22: 600b str r3, [r1, #0]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8001b24: 4b5e ldr r3, [pc, #376] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001b26: 685b ldr r3, [r3, #4]
8001b28: f423 427f bic.w r2, r3, #65280 @ 0xff00
8001b2c: 687b ldr r3, [r7, #4]
8001b2e: 69db ldr r3, [r3, #28]
8001b30: 021b lsls r3, r3, #8
8001b32: 495b ldr r1, [pc, #364] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001b34: 4313 orrs r3, r2
8001b36: 604b str r3, [r1, #4]
/* Decrease number of wait states update if necessary */
/* Only possible when MSI is the System clock source */
if(sysclk_source == RCC_CFGR_SWS_MSI)
8001b38: 69bb ldr r3, [r7, #24]
8001b3a: 2b00 cmp r3, #0
8001b3c: d109 bne.n 8001b52 <HAL_RCC_OscConfig+0x122>
{
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
8001b3e: 687b ldr r3, [r7, #4]
8001b40: 6a1b ldr r3, [r3, #32]
8001b42: 4618 mov r0, r3
8001b44: f000 fd14 bl 8002570 <RCC_SetFlashLatencyFromMSIRange>
8001b48: 4603 mov r3, r0
8001b4a: 2b00 cmp r3, #0
8001b4c: d001 beq.n 8001b52 <HAL_RCC_OscConfig+0x122>
{
return HAL_ERROR;
8001b4e: 2301 movs r3, #1
8001b50: e37a b.n 8002248 <HAL_RCC_OscConfig+0x818>
}
}
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
8001b52: f000 fc81 bl 8002458 <HAL_RCC_GetSysClockFreq>
8001b56: 4602 mov r2, r0
8001b58: 4b51 ldr r3, [pc, #324] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001b5a: 689b ldr r3, [r3, #8]
8001b5c: 091b lsrs r3, r3, #4
8001b5e: f003 030f and.w r3, r3, #15
8001b62: 4950 ldr r1, [pc, #320] @ (8001ca4 <HAL_RCC_OscConfig+0x274>)
8001b64: 5ccb ldrb r3, [r1, r3]
8001b66: f003 031f and.w r3, r3, #31
8001b6a: fa22 f303 lsr.w r3, r2, r3
8001b6e: 4a4e ldr r2, [pc, #312] @ (8001ca8 <HAL_RCC_OscConfig+0x278>)
8001b70: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
8001b72: 4b4e ldr r3, [pc, #312] @ (8001cac <HAL_RCC_OscConfig+0x27c>)
8001b74: 681b ldr r3, [r3, #0]
8001b76: 4618 mov r0, r3
8001b78: f7ff fc54 bl 8001424 <HAL_InitTick>
8001b7c: 4603 mov r3, r0
8001b7e: 73fb strb r3, [r7, #15]
if(status != HAL_OK)
8001b80: 7bfb ldrb r3, [r7, #15]
8001b82: 2b00 cmp r3, #0
8001b84: d052 beq.n 8001c2c <HAL_RCC_OscConfig+0x1fc>
{
return status;
8001b86: 7bfb ldrb r3, [r7, #15]
8001b88: e35e b.n 8002248 <HAL_RCC_OscConfig+0x818>
}
}
else
{
/* Check the MSI State */
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
8001b8a: 687b ldr r3, [r7, #4]
8001b8c: 699b ldr r3, [r3, #24]
8001b8e: 2b00 cmp r3, #0
8001b90: d032 beq.n 8001bf8 <HAL_RCC_OscConfig+0x1c8>
{
/* Enable the Internal High Speed oscillator (MSI). */
__HAL_RCC_MSI_ENABLE();
8001b92: 4b43 ldr r3, [pc, #268] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001b94: 681b ldr r3, [r3, #0]
8001b96: 4a42 ldr r2, [pc, #264] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001b98: f043 0301 orr.w r3, r3, #1
8001b9c: 6013 str r3, [r2, #0]
/* Get timeout */
tickstart = HAL_GetTick();
8001b9e: f7ff fc91 bl 80014c4 <HAL_GetTick>
8001ba2: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
8001ba4: e008 b.n 8001bb8 <HAL_RCC_OscConfig+0x188>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
8001ba6: f7ff fc8d bl 80014c4 <HAL_GetTick>
8001baa: 4602 mov r2, r0
8001bac: 693b ldr r3, [r7, #16]
8001bae: 1ad3 subs r3, r2, r3
8001bb0: 2b02 cmp r3, #2
8001bb2: d901 bls.n 8001bb8 <HAL_RCC_OscConfig+0x188>
{
return HAL_TIMEOUT;
8001bb4: 2303 movs r3, #3
8001bb6: e347 b.n 8002248 <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
8001bb8: 4b39 ldr r3, [pc, #228] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001bba: 681b ldr r3, [r3, #0]
8001bbc: f003 0302 and.w r3, r3, #2
8001bc0: 2b00 cmp r3, #0
8001bc2: d0f0 beq.n 8001ba6 <HAL_RCC_OscConfig+0x176>
}
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
8001bc4: 4b36 ldr r3, [pc, #216] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001bc6: 681b ldr r3, [r3, #0]
8001bc8: 4a35 ldr r2, [pc, #212] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001bca: f043 0308 orr.w r3, r3, #8
8001bce: 6013 str r3, [r2, #0]
8001bd0: 4b33 ldr r3, [pc, #204] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001bd2: 681b ldr r3, [r3, #0]
8001bd4: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8001bd8: 687b ldr r3, [r7, #4]
8001bda: 6a1b ldr r3, [r3, #32]
8001bdc: 4930 ldr r1, [pc, #192] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001bde: 4313 orrs r3, r2
8001be0: 600b str r3, [r1, #0]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8001be2: 4b2f ldr r3, [pc, #188] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001be4: 685b ldr r3, [r3, #4]
8001be6: f423 427f bic.w r2, r3, #65280 @ 0xff00
8001bea: 687b ldr r3, [r7, #4]
8001bec: 69db ldr r3, [r3, #28]
8001bee: 021b lsls r3, r3, #8
8001bf0: 492b ldr r1, [pc, #172] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001bf2: 4313 orrs r3, r2
8001bf4: 604b str r3, [r1, #4]
8001bf6: e01a b.n 8001c2e <HAL_RCC_OscConfig+0x1fe>
}
else
{
/* Disable the Internal High Speed oscillator (MSI). */
__HAL_RCC_MSI_DISABLE();
8001bf8: 4b29 ldr r3, [pc, #164] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001bfa: 681b ldr r3, [r3, #0]
8001bfc: 4a28 ldr r2, [pc, #160] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001bfe: f023 0301 bic.w r3, r3, #1
8001c02: 6013 str r3, [r2, #0]
/* Get timeout */
tickstart = HAL_GetTick();
8001c04: f7ff fc5e bl 80014c4 <HAL_GetTick>
8001c08: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
8001c0a: e008 b.n 8001c1e <HAL_RCC_OscConfig+0x1ee>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
8001c0c: f7ff fc5a bl 80014c4 <HAL_GetTick>
8001c10: 4602 mov r2, r0
8001c12: 693b ldr r3, [r7, #16]
8001c14: 1ad3 subs r3, r2, r3
8001c16: 2b02 cmp r3, #2
8001c18: d901 bls.n 8001c1e <HAL_RCC_OscConfig+0x1ee>
{
return HAL_TIMEOUT;
8001c1a: 2303 movs r3, #3
8001c1c: e314 b.n 8002248 <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
8001c1e: 4b20 ldr r3, [pc, #128] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001c20: 681b ldr r3, [r3, #0]
8001c22: f003 0302 and.w r3, r3, #2
8001c26: 2b00 cmp r3, #0
8001c28: d1f0 bne.n 8001c0c <HAL_RCC_OscConfig+0x1dc>
8001c2a: e000 b.n 8001c2e <HAL_RCC_OscConfig+0x1fe>
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
8001c2c: bf00 nop
}
}
}
}
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8001c2e: 687b ldr r3, [r7, #4]
8001c30: 681b ldr r3, [r3, #0]
8001c32: f003 0301 and.w r3, r3, #1
8001c36: 2b00 cmp r3, #0
8001c38: d073 beq.n 8001d22 <HAL_RCC_OscConfig+0x2f2>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((sysclk_source == RCC_CFGR_SWS_HSE) ||
8001c3a: 69bb ldr r3, [r7, #24]
8001c3c: 2b08 cmp r3, #8
8001c3e: d005 beq.n 8001c4c <HAL_RCC_OscConfig+0x21c>
8001c40: 69bb ldr r3, [r7, #24]
8001c42: 2b0c cmp r3, #12
8001c44: d10e bne.n 8001c64 <HAL_RCC_OscConfig+0x234>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))
8001c46: 697b ldr r3, [r7, #20]
8001c48: 2b03 cmp r3, #3
8001c4a: d10b bne.n 8001c64 <HAL_RCC_OscConfig+0x234>
{
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001c4c: 4b14 ldr r3, [pc, #80] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001c4e: 681b ldr r3, [r3, #0]
8001c50: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001c54: 2b00 cmp r3, #0
8001c56: d063 beq.n 8001d20 <HAL_RCC_OscConfig+0x2f0>
8001c58: 687b ldr r3, [r7, #4]
8001c5a: 685b ldr r3, [r3, #4]
8001c5c: 2b00 cmp r3, #0
8001c5e: d15f bne.n 8001d20 <HAL_RCC_OscConfig+0x2f0>
{
return HAL_ERROR;
8001c60: 2301 movs r3, #1
8001c62: e2f1 b.n 8002248 <HAL_RCC_OscConfig+0x818>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8001c64: 687b ldr r3, [r7, #4]
8001c66: 685b ldr r3, [r3, #4]
8001c68: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8001c6c: d106 bne.n 8001c7c <HAL_RCC_OscConfig+0x24c>
8001c6e: 4b0c ldr r3, [pc, #48] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001c70: 681b ldr r3, [r3, #0]
8001c72: 4a0b ldr r2, [pc, #44] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001c74: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001c78: 6013 str r3, [r2, #0]
8001c7a: e025 b.n 8001cc8 <HAL_RCC_OscConfig+0x298>
8001c7c: 687b ldr r3, [r7, #4]
8001c7e: 685b ldr r3, [r3, #4]
8001c80: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8001c84: d114 bne.n 8001cb0 <HAL_RCC_OscConfig+0x280>
8001c86: 4b06 ldr r3, [pc, #24] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001c88: 681b ldr r3, [r3, #0]
8001c8a: 4a05 ldr r2, [pc, #20] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001c8c: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8001c90: 6013 str r3, [r2, #0]
8001c92: 4b03 ldr r3, [pc, #12] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001c94: 681b ldr r3, [r3, #0]
8001c96: 4a02 ldr r2, [pc, #8] @ (8001ca0 <HAL_RCC_OscConfig+0x270>)
8001c98: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001c9c: 6013 str r3, [r2, #0]
8001c9e: e013 b.n 8001cc8 <HAL_RCC_OscConfig+0x298>
8001ca0: 40021000 .word 0x40021000
8001ca4: 08005648 .word 0x08005648
8001ca8: 20000000 .word 0x20000000
8001cac: 20000004 .word 0x20000004
8001cb0: 4ba0 ldr r3, [pc, #640] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001cb2: 681b ldr r3, [r3, #0]
8001cb4: 4a9f ldr r2, [pc, #636] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001cb6: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8001cba: 6013 str r3, [r2, #0]
8001cbc: 4b9d ldr r3, [pc, #628] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001cbe: 681b ldr r3, [r3, #0]
8001cc0: 4a9c ldr r2, [pc, #624] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001cc2: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8001cc6: 6013 str r3, [r2, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8001cc8: 687b ldr r3, [r7, #4]
8001cca: 685b ldr r3, [r3, #4]
8001ccc: 2b00 cmp r3, #0
8001cce: d013 beq.n 8001cf8 <HAL_RCC_OscConfig+0x2c8>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001cd0: f7ff fbf8 bl 80014c4 <HAL_GetTick>
8001cd4: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8001cd6: e008 b.n 8001cea <HAL_RCC_OscConfig+0x2ba>
{
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8001cd8: f7ff fbf4 bl 80014c4 <HAL_GetTick>
8001cdc: 4602 mov r2, r0
8001cde: 693b ldr r3, [r7, #16]
8001ce0: 1ad3 subs r3, r2, r3
8001ce2: 2b64 cmp r3, #100 @ 0x64
8001ce4: d901 bls.n 8001cea <HAL_RCC_OscConfig+0x2ba>
{
return HAL_TIMEOUT;
8001ce6: 2303 movs r3, #3
8001ce8: e2ae b.n 8002248 <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8001cea: 4b92 ldr r3, [pc, #584] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001cec: 681b ldr r3, [r3, #0]
8001cee: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001cf2: 2b00 cmp r3, #0
8001cf4: d0f0 beq.n 8001cd8 <HAL_RCC_OscConfig+0x2a8>
8001cf6: e014 b.n 8001d22 <HAL_RCC_OscConfig+0x2f2>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001cf8: f7ff fbe4 bl 80014c4 <HAL_GetTick>
8001cfc: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
8001cfe: e008 b.n 8001d12 <HAL_RCC_OscConfig+0x2e2>
{
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8001d00: f7ff fbe0 bl 80014c4 <HAL_GetTick>
8001d04: 4602 mov r2, r0
8001d06: 693b ldr r3, [r7, #16]
8001d08: 1ad3 subs r3, r2, r3
8001d0a: 2b64 cmp r3, #100 @ 0x64
8001d0c: d901 bls.n 8001d12 <HAL_RCC_OscConfig+0x2e2>
{
return HAL_TIMEOUT;
8001d0e: 2303 movs r3, #3
8001d10: e29a b.n 8002248 <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
8001d12: 4b88 ldr r3, [pc, #544] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001d14: 681b ldr r3, [r3, #0]
8001d16: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001d1a: 2b00 cmp r3, #0
8001d1c: d1f0 bne.n 8001d00 <HAL_RCC_OscConfig+0x2d0>
8001d1e: e000 b.n 8001d22 <HAL_RCC_OscConfig+0x2f2>
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001d20: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8001d22: 687b ldr r3, [r7, #4]
8001d24: 681b ldr r3, [r3, #0]
8001d26: f003 0302 and.w r3, r3, #2
8001d2a: 2b00 cmp r3, #0
8001d2c: d060 beq.n 8001df0 <HAL_RCC_OscConfig+0x3c0>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((sysclk_source == RCC_CFGR_SWS_HSI) ||
8001d2e: 69bb ldr r3, [r7, #24]
8001d30: 2b04 cmp r3, #4
8001d32: d005 beq.n 8001d40 <HAL_RCC_OscConfig+0x310>
8001d34: 69bb ldr r3, [r7, #24]
8001d36: 2b0c cmp r3, #12
8001d38: d119 bne.n 8001d6e <HAL_RCC_OscConfig+0x33e>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))
8001d3a: 697b ldr r3, [r7, #20]
8001d3c: 2b02 cmp r3, #2
8001d3e: d116 bne.n 8001d6e <HAL_RCC_OscConfig+0x33e>
{
/* When HSI is used as system clock it will not be disabled */
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8001d40: 4b7c ldr r3, [pc, #496] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001d42: 681b ldr r3, [r3, #0]
8001d44: f403 6380 and.w r3, r3, #1024 @ 0x400
8001d48: 2b00 cmp r3, #0
8001d4a: d005 beq.n 8001d58 <HAL_RCC_OscConfig+0x328>
8001d4c: 687b ldr r3, [r7, #4]
8001d4e: 68db ldr r3, [r3, #12]
8001d50: 2b00 cmp r3, #0
8001d52: d101 bne.n 8001d58 <HAL_RCC_OscConfig+0x328>
{
return HAL_ERROR;
8001d54: 2301 movs r3, #1
8001d56: e277 b.n 8002248 <HAL_RCC_OscConfig+0x818>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001d58: 4b76 ldr r3, [pc, #472] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001d5a: 685b ldr r3, [r3, #4]
8001d5c: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000
8001d60: 687b ldr r3, [r7, #4]
8001d62: 691b ldr r3, [r3, #16]
8001d64: 061b lsls r3, r3, #24
8001d66: 4973 ldr r1, [pc, #460] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001d68: 4313 orrs r3, r2
8001d6a: 604b str r3, [r1, #4]
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8001d6c: e040 b.n 8001df0 <HAL_RCC_OscConfig+0x3c0>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8001d6e: 687b ldr r3, [r7, #4]
8001d70: 68db ldr r3, [r3, #12]
8001d72: 2b00 cmp r3, #0
8001d74: d023 beq.n 8001dbe <HAL_RCC_OscConfig+0x38e>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8001d76: 4b6f ldr r3, [pc, #444] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001d78: 681b ldr r3, [r3, #0]
8001d7a: 4a6e ldr r2, [pc, #440] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001d7c: f443 7380 orr.w r3, r3, #256 @ 0x100
8001d80: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001d82: f7ff fb9f bl 80014c4 <HAL_GetTick>
8001d86: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8001d88: e008 b.n 8001d9c <HAL_RCC_OscConfig+0x36c>
{
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8001d8a: f7ff fb9b bl 80014c4 <HAL_GetTick>
8001d8e: 4602 mov r2, r0
8001d90: 693b ldr r3, [r7, #16]
8001d92: 1ad3 subs r3, r2, r3
8001d94: 2b02 cmp r3, #2
8001d96: d901 bls.n 8001d9c <HAL_RCC_OscConfig+0x36c>
{
return HAL_TIMEOUT;
8001d98: 2303 movs r3, #3
8001d9a: e255 b.n 8002248 <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8001d9c: 4b65 ldr r3, [pc, #404] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001d9e: 681b ldr r3, [r3, #0]
8001da0: f403 6380 and.w r3, r3, #1024 @ 0x400
8001da4: 2b00 cmp r3, #0
8001da6: d0f0 beq.n 8001d8a <HAL_RCC_OscConfig+0x35a>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001da8: 4b62 ldr r3, [pc, #392] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001daa: 685b ldr r3, [r3, #4]
8001dac: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000
8001db0: 687b ldr r3, [r7, #4]
8001db2: 691b ldr r3, [r3, #16]
8001db4: 061b lsls r3, r3, #24
8001db6: 495f ldr r1, [pc, #380] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001db8: 4313 orrs r3, r2
8001dba: 604b str r3, [r1, #4]
8001dbc: e018 b.n 8001df0 <HAL_RCC_OscConfig+0x3c0>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8001dbe: 4b5d ldr r3, [pc, #372] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001dc0: 681b ldr r3, [r3, #0]
8001dc2: 4a5c ldr r2, [pc, #368] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001dc4: f423 7380 bic.w r3, r3, #256 @ 0x100
8001dc8: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001dca: f7ff fb7b bl 80014c4 <HAL_GetTick>
8001dce: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8001dd0: e008 b.n 8001de4 <HAL_RCC_OscConfig+0x3b4>
{
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8001dd2: f7ff fb77 bl 80014c4 <HAL_GetTick>
8001dd6: 4602 mov r2, r0
8001dd8: 693b ldr r3, [r7, #16]
8001dda: 1ad3 subs r3, r2, r3
8001ddc: 2b02 cmp r3, #2
8001dde: d901 bls.n 8001de4 <HAL_RCC_OscConfig+0x3b4>
{
return HAL_TIMEOUT;
8001de0: 2303 movs r3, #3
8001de2: e231 b.n 8002248 <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8001de4: 4b53 ldr r3, [pc, #332] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001de6: 681b ldr r3, [r3, #0]
8001de8: f403 6380 and.w r3, r3, #1024 @ 0x400
8001dec: 2b00 cmp r3, #0
8001dee: d1f0 bne.n 8001dd2 <HAL_RCC_OscConfig+0x3a2>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8001df0: 687b ldr r3, [r7, #4]
8001df2: 681b ldr r3, [r3, #0]
8001df4: f003 0308 and.w r3, r3, #8
8001df8: 2b00 cmp r3, #0
8001dfa: d03c beq.n 8001e76 <HAL_RCC_OscConfig+0x446>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8001dfc: 687b ldr r3, [r7, #4]
8001dfe: 695b ldr r3, [r3, #20]
8001e00: 2b00 cmp r3, #0
8001e02: d01c beq.n 8001e3e <HAL_RCC_OscConfig+0x40e>
MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);
}
#endif /* RCC_CSR_LSIPREDIV */
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001e04: 4b4b ldr r3, [pc, #300] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001e06: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8001e0a: 4a4a ldr r2, [pc, #296] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001e0c: f043 0301 orr.w r3, r3, #1
8001e10: f8c2 3094 str.w r3, [r2, #148] @ 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001e14: f7ff fb56 bl 80014c4 <HAL_GetTick>
8001e18: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8001e1a: e008 b.n 8001e2e <HAL_RCC_OscConfig+0x3fe>
{
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8001e1c: f7ff fb52 bl 80014c4 <HAL_GetTick>
8001e20: 4602 mov r2, r0
8001e22: 693b ldr r3, [r7, #16]
8001e24: 1ad3 subs r3, r2, r3
8001e26: 2b02 cmp r3, #2
8001e28: d901 bls.n 8001e2e <HAL_RCC_OscConfig+0x3fe>
{
return HAL_TIMEOUT;
8001e2a: 2303 movs r3, #3
8001e2c: e20c b.n 8002248 <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8001e2e: 4b41 ldr r3, [pc, #260] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001e30: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8001e34: f003 0302 and.w r3, r3, #2
8001e38: 2b00 cmp r3, #0
8001e3a: d0ef beq.n 8001e1c <HAL_RCC_OscConfig+0x3ec>
8001e3c: e01b b.n 8001e76 <HAL_RCC_OscConfig+0x446>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8001e3e: 4b3d ldr r3, [pc, #244] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001e40: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8001e44: 4a3b ldr r2, [pc, #236] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001e46: f023 0301 bic.w r3, r3, #1
8001e4a: f8c2 3094 str.w r3, [r2, #148] @ 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001e4e: f7ff fb39 bl 80014c4 <HAL_GetTick>
8001e52: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8001e54: e008 b.n 8001e68 <HAL_RCC_OscConfig+0x438>
{
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8001e56: f7ff fb35 bl 80014c4 <HAL_GetTick>
8001e5a: 4602 mov r2, r0
8001e5c: 693b ldr r3, [r7, #16]
8001e5e: 1ad3 subs r3, r2, r3
8001e60: 2b02 cmp r3, #2
8001e62: d901 bls.n 8001e68 <HAL_RCC_OscConfig+0x438>
{
return HAL_TIMEOUT;
8001e64: 2303 movs r3, #3
8001e66: e1ef b.n 8002248 <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8001e68: 4b32 ldr r3, [pc, #200] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001e6a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8001e6e: f003 0302 and.w r3, r3, #2
8001e72: 2b00 cmp r3, #0
8001e74: d1ef bne.n 8001e56 <HAL_RCC_OscConfig+0x426>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8001e76: 687b ldr r3, [r7, #4]
8001e78: 681b ldr r3, [r3, #0]
8001e7a: f003 0304 and.w r3, r3, #4
8001e7e: 2b00 cmp r3, #0
8001e80: f000 80a6 beq.w 8001fd0 <HAL_RCC_OscConfig+0x5a0>
{
FlagStatus pwrclkchanged = RESET;
8001e84: 2300 movs r3, #0
8001e86: 77fb strb r3, [r7, #31]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
8001e88: 4b2a ldr r3, [pc, #168] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001e8a: 6d9b ldr r3, [r3, #88] @ 0x58
8001e8c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001e90: 2b00 cmp r3, #0
8001e92: d10d bne.n 8001eb0 <HAL_RCC_OscConfig+0x480>
{
__HAL_RCC_PWR_CLK_ENABLE();
8001e94: 4b27 ldr r3, [pc, #156] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001e96: 6d9b ldr r3, [r3, #88] @ 0x58
8001e98: 4a26 ldr r2, [pc, #152] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001e9a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001e9e: 6593 str r3, [r2, #88] @ 0x58
8001ea0: 4b24 ldr r3, [pc, #144] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001ea2: 6d9b ldr r3, [r3, #88] @ 0x58
8001ea4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001ea8: 60bb str r3, [r7, #8]
8001eaa: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8001eac: 2301 movs r3, #1
8001eae: 77fb strb r3, [r7, #31]
}
if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8001eb0: 4b21 ldr r3, [pc, #132] @ (8001f38 <HAL_RCC_OscConfig+0x508>)
8001eb2: 681b ldr r3, [r3, #0]
8001eb4: f403 7380 and.w r3, r3, #256 @ 0x100
8001eb8: 2b00 cmp r3, #0
8001eba: d118 bne.n 8001eee <HAL_RCC_OscConfig+0x4be>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8001ebc: 4b1e ldr r3, [pc, #120] @ (8001f38 <HAL_RCC_OscConfig+0x508>)
8001ebe: 681b ldr r3, [r3, #0]
8001ec0: 4a1d ldr r2, [pc, #116] @ (8001f38 <HAL_RCC_OscConfig+0x508>)
8001ec2: f443 7380 orr.w r3, r3, #256 @ 0x100
8001ec6: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8001ec8: f7ff fafc bl 80014c4 <HAL_GetTick>
8001ecc: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8001ece: e008 b.n 8001ee2 <HAL_RCC_OscConfig+0x4b2>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001ed0: f7ff faf8 bl 80014c4 <HAL_GetTick>
8001ed4: 4602 mov r2, r0
8001ed6: 693b ldr r3, [r7, #16]
8001ed8: 1ad3 subs r3, r2, r3
8001eda: 2b02 cmp r3, #2
8001edc: d901 bls.n 8001ee2 <HAL_RCC_OscConfig+0x4b2>
{
return HAL_TIMEOUT;
8001ede: 2303 movs r3, #3
8001ee0: e1b2 b.n 8002248 <HAL_RCC_OscConfig+0x818>
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8001ee2: 4b15 ldr r3, [pc, #84] @ (8001f38 <HAL_RCC_OscConfig+0x508>)
8001ee4: 681b ldr r3, [r3, #0]
8001ee6: f403 7380 and.w r3, r3, #256 @ 0x100
8001eea: 2b00 cmp r3, #0
8001eec: d0f0 beq.n 8001ed0 <HAL_RCC_OscConfig+0x4a0>
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
}
#else
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8001eee: 687b ldr r3, [r7, #4]
8001ef0: 689b ldr r3, [r3, #8]
8001ef2: 2b01 cmp r3, #1
8001ef4: d108 bne.n 8001f08 <HAL_RCC_OscConfig+0x4d8>
8001ef6: 4b0f ldr r3, [pc, #60] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001ef8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8001efc: 4a0d ldr r2, [pc, #52] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001efe: f043 0301 orr.w r3, r3, #1
8001f02: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8001f06: e029 b.n 8001f5c <HAL_RCC_OscConfig+0x52c>
8001f08: 687b ldr r3, [r7, #4]
8001f0a: 689b ldr r3, [r3, #8]
8001f0c: 2b05 cmp r3, #5
8001f0e: d115 bne.n 8001f3c <HAL_RCC_OscConfig+0x50c>
8001f10: 4b08 ldr r3, [pc, #32] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001f12: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8001f16: 4a07 ldr r2, [pc, #28] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001f18: f043 0304 orr.w r3, r3, #4
8001f1c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8001f20: 4b04 ldr r3, [pc, #16] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001f22: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8001f26: 4a03 ldr r2, [pc, #12] @ (8001f34 <HAL_RCC_OscConfig+0x504>)
8001f28: f043 0301 orr.w r3, r3, #1
8001f2c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8001f30: e014 b.n 8001f5c <HAL_RCC_OscConfig+0x52c>
8001f32: bf00 nop
8001f34: 40021000 .word 0x40021000
8001f38: 40007000 .word 0x40007000
8001f3c: 4b9a ldr r3, [pc, #616] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8001f3e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8001f42: 4a99 ldr r2, [pc, #612] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8001f44: f023 0301 bic.w r3, r3, #1
8001f48: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8001f4c: 4b96 ldr r3, [pc, #600] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8001f4e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8001f52: 4a95 ldr r2, [pc, #596] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8001f54: f023 0304 bic.w r3, r3, #4
8001f58: f8c2 3090 str.w r3, [r2, #144] @ 0x90
#endif /* RCC_BDCR_LSESYSDIS */
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8001f5c: 687b ldr r3, [r7, #4]
8001f5e: 689b ldr r3, [r3, #8]
8001f60: 2b00 cmp r3, #0
8001f62: d016 beq.n 8001f92 <HAL_RCC_OscConfig+0x562>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001f64: f7ff faae bl 80014c4 <HAL_GetTick>
8001f68: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8001f6a: e00a b.n 8001f82 <HAL_RCC_OscConfig+0x552>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8001f6c: f7ff faaa bl 80014c4 <HAL_GetTick>
8001f70: 4602 mov r2, r0
8001f72: 693b ldr r3, [r7, #16]
8001f74: 1ad3 subs r3, r2, r3
8001f76: f241 3288 movw r2, #5000 @ 0x1388
8001f7a: 4293 cmp r3, r2
8001f7c: d901 bls.n 8001f82 <HAL_RCC_OscConfig+0x552>
{
return HAL_TIMEOUT;
8001f7e: 2303 movs r3, #3
8001f80: e162 b.n 8002248 <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8001f82: 4b89 ldr r3, [pc, #548] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8001f84: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8001f88: f003 0302 and.w r3, r3, #2
8001f8c: 2b00 cmp r3, #0
8001f8e: d0ed beq.n 8001f6c <HAL_RCC_OscConfig+0x53c>
8001f90: e015 b.n 8001fbe <HAL_RCC_OscConfig+0x58e>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001f92: f7ff fa97 bl 80014c4 <HAL_GetTick>
8001f96: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8001f98: e00a b.n 8001fb0 <HAL_RCC_OscConfig+0x580>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8001f9a: f7ff fa93 bl 80014c4 <HAL_GetTick>
8001f9e: 4602 mov r2, r0
8001fa0: 693b ldr r3, [r7, #16]
8001fa2: 1ad3 subs r3, r2, r3
8001fa4: f241 3288 movw r2, #5000 @ 0x1388
8001fa8: 4293 cmp r3, r2
8001faa: d901 bls.n 8001fb0 <HAL_RCC_OscConfig+0x580>
{
return HAL_TIMEOUT;
8001fac: 2303 movs r3, #3
8001fae: e14b b.n 8002248 <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8001fb0: 4b7d ldr r3, [pc, #500] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8001fb2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8001fb6: f003 0302 and.w r3, r3, #2
8001fba: 2b00 cmp r3, #0
8001fbc: d1ed bne.n 8001f9a <HAL_RCC_OscConfig+0x56a>
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
#endif /* RCC_BDCR_LSESYSDIS */
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8001fbe: 7ffb ldrb r3, [r7, #31]
8001fc0: 2b01 cmp r3, #1
8001fc2: d105 bne.n 8001fd0 <HAL_RCC_OscConfig+0x5a0>
{
__HAL_RCC_PWR_CLK_DISABLE();
8001fc4: 4b78 ldr r3, [pc, #480] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8001fc6: 6d9b ldr r3, [r3, #88] @ 0x58
8001fc8: 4a77 ldr r2, [pc, #476] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8001fca: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8001fce: 6593 str r3, [r2, #88] @ 0x58
}
}
#if defined(RCC_HSI48_SUPPORT)
/*------------------------------ HSI48 Configuration -----------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
8001fd0: 687b ldr r3, [r7, #4]
8001fd2: 681b ldr r3, [r3, #0]
8001fd4: f003 0320 and.w r3, r3, #32
8001fd8: 2b00 cmp r3, #0
8001fda: d03c beq.n 8002056 <HAL_RCC_OscConfig+0x626>
{
/* Check the parameters */
assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
/* Check the LSI State */
if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
8001fdc: 687b ldr r3, [r7, #4]
8001fde: 6a5b ldr r3, [r3, #36] @ 0x24
8001fe0: 2b00 cmp r3, #0
8001fe2: d01c beq.n 800201e <HAL_RCC_OscConfig+0x5ee>
{
/* Enable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_ENABLE();
8001fe4: 4b70 ldr r3, [pc, #448] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8001fe6: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
8001fea: 4a6f ldr r2, [pc, #444] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8001fec: f043 0301 orr.w r3, r3, #1
8001ff0: f8c2 3098 str.w r3, [r2, #152] @ 0x98
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001ff4: f7ff fa66 bl 80014c4 <HAL_GetTick>
8001ff8: 6138 str r0, [r7, #16]
/* Wait till HSI48 is ready */
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
8001ffa: e008 b.n 800200e <HAL_RCC_OscConfig+0x5de>
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
8001ffc: f7ff fa62 bl 80014c4 <HAL_GetTick>
8002000: 4602 mov r2, r0
8002002: 693b ldr r3, [r7, #16]
8002004: 1ad3 subs r3, r2, r3
8002006: 2b02 cmp r3, #2
8002008: d901 bls.n 800200e <HAL_RCC_OscConfig+0x5de>
{
return HAL_TIMEOUT;
800200a: 2303 movs r3, #3
800200c: e11c b.n 8002248 <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
800200e: 4b66 ldr r3, [pc, #408] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8002010: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
8002014: f003 0302 and.w r3, r3, #2
8002018: 2b00 cmp r3, #0
800201a: d0ef beq.n 8001ffc <HAL_RCC_OscConfig+0x5cc>
800201c: e01b b.n 8002056 <HAL_RCC_OscConfig+0x626>
}
}
else
{
/* Disable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_DISABLE();
800201e: 4b62 ldr r3, [pc, #392] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8002020: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
8002024: 4a60 ldr r2, [pc, #384] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8002026: f023 0301 bic.w r3, r3, #1
800202a: f8c2 3098 str.w r3, [r2, #152] @ 0x98
/* Get Start Tick*/
tickstart = HAL_GetTick();
800202e: f7ff fa49 bl 80014c4 <HAL_GetTick>
8002032: 6138 str r0, [r7, #16]
/* Wait till HSI48 is disabled */
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
8002034: e008 b.n 8002048 <HAL_RCC_OscConfig+0x618>
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
8002036: f7ff fa45 bl 80014c4 <HAL_GetTick>
800203a: 4602 mov r2, r0
800203c: 693b ldr r3, [r7, #16]
800203e: 1ad3 subs r3, r2, r3
8002040: 2b02 cmp r3, #2
8002042: d901 bls.n 8002048 <HAL_RCC_OscConfig+0x618>
{
return HAL_TIMEOUT;
8002044: 2303 movs r3, #3
8002046: e0ff b.n 8002248 <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
8002048: 4b57 ldr r3, [pc, #348] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
800204a: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
800204e: f003 0302 and.w r3, r3, #2
8002052: 2b00 cmp r3, #0
8002054: d1ef bne.n 8002036 <HAL_RCC_OscConfig+0x606>
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
8002056: 687b ldr r3, [r7, #4]
8002058: 6a9b ldr r3, [r3, #40] @ 0x28
800205a: 2b00 cmp r3, #0
800205c: f000 80f3 beq.w 8002246 <HAL_RCC_OscConfig+0x816>
{
/* PLL On ? */
if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
8002060: 687b ldr r3, [r7, #4]
8002062: 6a9b ldr r3, [r3, #40] @ 0x28
8002064: 2b02 cmp r3, #2
8002066: f040 80c9 bne.w 80021fc <HAL_RCC_OscConfig+0x7cc>
#endif /* RCC_PLLP_SUPPORT */
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Do nothing if PLL configuration is the unchanged */
pll_config = RCC->PLLCFGR;
800206a: 4b4f ldr r3, [pc, #316] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
800206c: 68db ldr r3, [r3, #12]
800206e: 617b str r3, [r7, #20]
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002070: 697b ldr r3, [r7, #20]
8002072: f003 0203 and.w r2, r3, #3
8002076: 687b ldr r3, [r7, #4]
8002078: 6adb ldr r3, [r3, #44] @ 0x2c
800207a: 429a cmp r2, r3
800207c: d12c bne.n 80020d8 <HAL_RCC_OscConfig+0x6a8>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
800207e: 697b ldr r3, [r7, #20]
8002080: f003 0270 and.w r2, r3, #112 @ 0x70
8002084: 687b ldr r3, [r7, #4]
8002086: 6b1b ldr r3, [r3, #48] @ 0x30
8002088: 3b01 subs r3, #1
800208a: 011b lsls r3, r3, #4
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800208c: 429a cmp r2, r3
800208e: d123 bne.n 80020d8 <HAL_RCC_OscConfig+0x6a8>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8002090: 697b ldr r3, [r7, #20]
8002092: f403 42fe and.w r2, r3, #32512 @ 0x7f00
8002096: 687b ldr r3, [r7, #4]
8002098: 6b5b ldr r3, [r3, #52] @ 0x34
800209a: 021b lsls r3, r3, #8
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
800209c: 429a cmp r2, r3
800209e: d11b bne.n 80020d8 <HAL_RCC_OscConfig+0x6a8>
#if defined(RCC_PLLP_SUPPORT)
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
(READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
80020a0: 697b ldr r3, [r7, #20]
80020a2: f003 4278 and.w r2, r3, #4160749568 @ 0xf8000000
80020a6: 687b ldr r3, [r7, #4]
80020a8: 6b9b ldr r3, [r3, #56] @ 0x38
80020aa: 06db lsls r3, r3, #27
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
80020ac: 429a cmp r2, r3
80020ae: d113 bne.n 80020d8 <HAL_RCC_OscConfig+0x6a8>
#else
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
#endif
#endif
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
80020b0: 697b ldr r3, [r7, #20]
80020b2: f403 02c0 and.w r2, r3, #6291456 @ 0x600000
80020b6: 687b ldr r3, [r7, #4]
80020b8: 6bdb ldr r3, [r3, #60] @ 0x3c
80020ba: 085b lsrs r3, r3, #1
80020bc: 3b01 subs r3, #1
80020be: 055b lsls r3, r3, #21
(READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
80020c0: 429a cmp r2, r3
80020c2: d109 bne.n 80020d8 <HAL_RCC_OscConfig+0x6a8>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
80020c4: 697b ldr r3, [r7, #20]
80020c6: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000
80020ca: 687b ldr r3, [r7, #4]
80020cc: 6c1b ldr r3, [r3, #64] @ 0x40
80020ce: 085b lsrs r3, r3, #1
80020d0: 3b01 subs r3, #1
80020d2: 065b lsls r3, r3, #25
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
80020d4: 429a cmp r2, r3
80020d6: d06b beq.n 80021b0 <HAL_RCC_OscConfig+0x780>
{
/* Check if the PLL is used as system clock or not */
if(sysclk_source != RCC_CFGR_SWS_PLL)
80020d8: 69bb ldr r3, [r7, #24]
80020da: 2b0c cmp r3, #12
80020dc: d062 beq.n 80021a4 <HAL_RCC_OscConfig+0x774>
{
#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT)
/* Check if main PLL can be updated */
/* Not possible if the source is shared by other enabled PLLSAIx */
if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
80020de: 4b32 ldr r3, [pc, #200] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
80020e0: 681b ldr r3, [r3, #0]
80020e2: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
80020e6: 2b00 cmp r3, #0
80020e8: d001 beq.n 80020ee <HAL_RCC_OscConfig+0x6be>
#if defined(RCC_PLLSAI2_SUPPORT)
|| (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U)
#endif
)
{
return HAL_ERROR;
80020ea: 2301 movs r3, #1
80020ec: e0ac b.n 8002248 <HAL_RCC_OscConfig+0x818>
}
else
#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80020ee: 4b2e ldr r3, [pc, #184] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
80020f0: 681b ldr r3, [r3, #0]
80020f2: 4a2d ldr r2, [pc, #180] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
80020f4: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
80020f8: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80020fa: f7ff f9e3 bl 80014c4 <HAL_GetTick>
80020fe: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8002100: e008 b.n 8002114 <HAL_RCC_OscConfig+0x6e4>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002102: f7ff f9df bl 80014c4 <HAL_GetTick>
8002106: 4602 mov r2, r0
8002108: 693b ldr r3, [r7, #16]
800210a: 1ad3 subs r3, r2, r3
800210c: 2b02 cmp r3, #2
800210e: d901 bls.n 8002114 <HAL_RCC_OscConfig+0x6e4>
{
return HAL_TIMEOUT;
8002110: 2303 movs r3, #3
8002112: e099 b.n 8002248 <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8002114: 4b24 ldr r3, [pc, #144] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8002116: 681b ldr r3, [r3, #0]
8002118: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800211c: 2b00 cmp r3, #0
800211e: d1f0 bne.n 8002102 <HAL_RCC_OscConfig+0x6d2>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
#if defined(RCC_PLLP_SUPPORT)
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8002120: 4b21 ldr r3, [pc, #132] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8002122: 68da ldr r2, [r3, #12]
8002124: 4b21 ldr r3, [pc, #132] @ (80021ac <HAL_RCC_OscConfig+0x77c>)
8002126: 4013 ands r3, r2
8002128: 687a ldr r2, [r7, #4]
800212a: 6ad1 ldr r1, [r2, #44] @ 0x2c
800212c: 687a ldr r2, [r7, #4]
800212e: 6b12 ldr r2, [r2, #48] @ 0x30
8002130: 3a01 subs r2, #1
8002132: 0112 lsls r2, r2, #4
8002134: 4311 orrs r1, r2
8002136: 687a ldr r2, [r7, #4]
8002138: 6b52 ldr r2, [r2, #52] @ 0x34
800213a: 0212 lsls r2, r2, #8
800213c: 4311 orrs r1, r2
800213e: 687a ldr r2, [r7, #4]
8002140: 6bd2 ldr r2, [r2, #60] @ 0x3c
8002142: 0852 lsrs r2, r2, #1
8002144: 3a01 subs r2, #1
8002146: 0552 lsls r2, r2, #21
8002148: 4311 orrs r1, r2
800214a: 687a ldr r2, [r7, #4]
800214c: 6c12 ldr r2, [r2, #64] @ 0x40
800214e: 0852 lsrs r2, r2, #1
8002150: 3a01 subs r2, #1
8002152: 0652 lsls r2, r2, #25
8002154: 4311 orrs r1, r2
8002156: 687a ldr r2, [r7, #4]
8002158: 6b92 ldr r2, [r2, #56] @ 0x38
800215a: 06d2 lsls r2, r2, #27
800215c: 430a orrs r2, r1
800215e: 4912 ldr r1, [pc, #72] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8002160: 4313 orrs r3, r2
8002162: 60cb str r3, [r1, #12]
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
#endif
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8002164: 4b10 ldr r3, [pc, #64] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8002166: 681b ldr r3, [r3, #0]
8002168: 4a0f ldr r2, [pc, #60] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
800216a: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
800216e: 6013 str r3, [r2, #0]
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
8002170: 4b0d ldr r3, [pc, #52] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8002172: 68db ldr r3, [r3, #12]
8002174: 4a0c ldr r2, [pc, #48] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8002176: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
800217a: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800217c: f7ff f9a2 bl 80014c4 <HAL_GetTick>
8002180: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8002182: e008 b.n 8002196 <HAL_RCC_OscConfig+0x766>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002184: f7ff f99e bl 80014c4 <HAL_GetTick>
8002188: 4602 mov r2, r0
800218a: 693b ldr r3, [r7, #16]
800218c: 1ad3 subs r3, r2, r3
800218e: 2b02 cmp r3, #2
8002190: d901 bls.n 8002196 <HAL_RCC_OscConfig+0x766>
{
return HAL_TIMEOUT;
8002192: 2303 movs r3, #3
8002194: e058 b.n 8002248 <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8002196: 4b04 ldr r3, [pc, #16] @ (80021a8 <HAL_RCC_OscConfig+0x778>)
8002198: 681b ldr r3, [r3, #0]
800219a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800219e: 2b00 cmp r3, #0
80021a0: d0f0 beq.n 8002184 <HAL_RCC_OscConfig+0x754>
if(sysclk_source != RCC_CFGR_SWS_PLL)
80021a2: e050 b.n 8002246 <HAL_RCC_OscConfig+0x816>
}
}
else
{
/* PLL is already used as System core clock */
return HAL_ERROR;
80021a4: 2301 movs r3, #1
80021a6: e04f b.n 8002248 <HAL_RCC_OscConfig+0x818>
80021a8: 40021000 .word 0x40021000
80021ac: 019d808c .word 0x019d808c
}
else
{
/* PLL configuration is unchanged */
/* Re-enable PLL if it was disabled (ie. low power mode) */
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
80021b0: 4b27 ldr r3, [pc, #156] @ (8002250 <HAL_RCC_OscConfig+0x820>)
80021b2: 681b ldr r3, [r3, #0]
80021b4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80021b8: 2b00 cmp r3, #0
80021ba: d144 bne.n 8002246 <HAL_RCC_OscConfig+0x816>
{
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80021bc: 4b24 ldr r3, [pc, #144] @ (8002250 <HAL_RCC_OscConfig+0x820>)
80021be: 681b ldr r3, [r3, #0]
80021c0: 4a23 ldr r2, [pc, #140] @ (8002250 <HAL_RCC_OscConfig+0x820>)
80021c2: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
80021c6: 6013 str r3, [r2, #0]
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
80021c8: 4b21 ldr r3, [pc, #132] @ (8002250 <HAL_RCC_OscConfig+0x820>)
80021ca: 68db ldr r3, [r3, #12]
80021cc: 4a20 ldr r2, [pc, #128] @ (8002250 <HAL_RCC_OscConfig+0x820>)
80021ce: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
80021d2: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80021d4: f7ff f976 bl 80014c4 <HAL_GetTick>
80021d8: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
80021da: e008 b.n 80021ee <HAL_RCC_OscConfig+0x7be>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80021dc: f7ff f972 bl 80014c4 <HAL_GetTick>
80021e0: 4602 mov r2, r0
80021e2: 693b ldr r3, [r7, #16]
80021e4: 1ad3 subs r3, r2, r3
80021e6: 2b02 cmp r3, #2
80021e8: d901 bls.n 80021ee <HAL_RCC_OscConfig+0x7be>
{
return HAL_TIMEOUT;
80021ea: 2303 movs r3, #3
80021ec: e02c b.n 8002248 <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
80021ee: 4b18 ldr r3, [pc, #96] @ (8002250 <HAL_RCC_OscConfig+0x820>)
80021f0: 681b ldr r3, [r3, #0]
80021f2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80021f6: 2b00 cmp r3, #0
80021f8: d0f0 beq.n 80021dc <HAL_RCC_OscConfig+0x7ac>
80021fa: e024 b.n 8002246 <HAL_RCC_OscConfig+0x816>
}
}
else
{
/* Check that PLL is not used as system clock or not */
if(sysclk_source != RCC_CFGR_SWS_PLL)
80021fc: 69bb ldr r3, [r7, #24]
80021fe: 2b0c cmp r3, #12
8002200: d01f beq.n 8002242 <HAL_RCC_OscConfig+0x812>
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002202: 4b13 ldr r3, [pc, #76] @ (8002250 <HAL_RCC_OscConfig+0x820>)
8002204: 681b ldr r3, [r3, #0]
8002206: 4a12 ldr r2, [pc, #72] @ (8002250 <HAL_RCC_OscConfig+0x820>)
8002208: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
800220c: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800220e: f7ff f959 bl 80014c4 <HAL_GetTick>
8002212: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8002214: e008 b.n 8002228 <HAL_RCC_OscConfig+0x7f8>
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002216: f7ff f955 bl 80014c4 <HAL_GetTick>
800221a: 4602 mov r2, r0
800221c: 693b ldr r3, [r7, #16]
800221e: 1ad3 subs r3, r2, r3
8002220: 2b02 cmp r3, #2
8002222: d901 bls.n 8002228 <HAL_RCC_OscConfig+0x7f8>
{
return HAL_TIMEOUT;
8002224: 2303 movs r3, #3
8002226: e00f b.n 8002248 <HAL_RCC_OscConfig+0x818>
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8002228: 4b09 ldr r3, [pc, #36] @ (8002250 <HAL_RCC_OscConfig+0x820>)
800222a: 681b ldr r3, [r3, #0]
800222c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002230: 2b00 cmp r3, #0
8002232: d1f0 bne.n 8002216 <HAL_RCC_OscConfig+0x7e6>
}
/* Unselect main PLL clock source and disable main PLL outputs to save power */
#if defined(RCC_PLLSAI2_SUPPORT)
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
#elif defined(RCC_PLLSAI1_SUPPORT)
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI2CLK);
8002234: 4b06 ldr r3, [pc, #24] @ (8002250 <HAL_RCC_OscConfig+0x820>)
8002236: 68da ldr r2, [r3, #12]
8002238: 4905 ldr r1, [pc, #20] @ (8002250 <HAL_RCC_OscConfig+0x820>)
800223a: 4b06 ldr r3, [pc, #24] @ (8002254 <HAL_RCC_OscConfig+0x824>)
800223c: 4013 ands r3, r2
800223e: 60cb str r3, [r1, #12]
8002240: e001 b.n 8002246 <HAL_RCC_OscConfig+0x816>
#endif /* RCC_PLLSAI2_SUPPORT */
}
else
{
/* PLL is already used as System core clock */
return HAL_ERROR;
8002242: 2301 movs r3, #1
8002244: e000 b.n 8002248 <HAL_RCC_OscConfig+0x818>
}
}
}
return HAL_OK;
8002246: 2300 movs r3, #0
}
8002248: 4618 mov r0, r3
800224a: 3720 adds r7, #32
800224c: 46bd mov sp, r7
800224e: bd80 pop {r7, pc}
8002250: 40021000 .word 0x40021000
8002254: feeefffc .word 0xfeeefffc
08002258 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8002258: b580 push {r7, lr}
800225a: b084 sub sp, #16
800225c: af00 add r7, sp, #0
800225e: 6078 str r0, [r7, #4]
8002260: 6039 str r1, [r7, #0]
uint32_t hpre = RCC_SYSCLK_DIV1;
#endif
HAL_StatusTypeDef status;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8002262: 687b ldr r3, [r7, #4]
8002264: 2b00 cmp r3, #0
8002266: d101 bne.n 800226c <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8002268: 2301 movs r3, #1
800226a: e0e7 b.n 800243c <HAL_RCC_ClockConfig+0x1e4>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
800226c: 4b75 ldr r3, [pc, #468] @ (8002444 <HAL_RCC_ClockConfig+0x1ec>)
800226e: 681b ldr r3, [r3, #0]
8002270: f003 0307 and.w r3, r3, #7
8002274: 683a ldr r2, [r7, #0]
8002276: 429a cmp r2, r3
8002278: d910 bls.n 800229c <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800227a: 4b72 ldr r3, [pc, #456] @ (8002444 <HAL_RCC_ClockConfig+0x1ec>)
800227c: 681b ldr r3, [r3, #0]
800227e: f023 0207 bic.w r2, r3, #7
8002282: 4970 ldr r1, [pc, #448] @ (8002444 <HAL_RCC_ClockConfig+0x1ec>)
8002284: 683b ldr r3, [r7, #0]
8002286: 4313 orrs r3, r2
8002288: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
800228a: 4b6e ldr r3, [pc, #440] @ (8002444 <HAL_RCC_ClockConfig+0x1ec>)
800228c: 681b ldr r3, [r3, #0]
800228e: f003 0307 and.w r3, r3, #7
8002292: 683a ldr r2, [r7, #0]
8002294: 429a cmp r2, r3
8002296: d001 beq.n 800229c <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
8002298: 2301 movs r3, #1
800229a: e0cf b.n 800243c <HAL_RCC_ClockConfig+0x1e4>
}
}
/*----------------- HCLK Configuration prior to SYSCLK----------------------*/
/* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
800229c: 687b ldr r3, [r7, #4]
800229e: 681b ldr r3, [r3, #0]
80022a0: f003 0302 and.w r3, r3, #2
80022a4: 2b00 cmp r3, #0
80022a6: d010 beq.n 80022ca <HAL_RCC_ClockConfig+0x72>
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
80022a8: 687b ldr r3, [r7, #4]
80022aa: 689a ldr r2, [r3, #8]
80022ac: 4b66 ldr r3, [pc, #408] @ (8002448 <HAL_RCC_ClockConfig+0x1f0>)
80022ae: 689b ldr r3, [r3, #8]
80022b0: f003 03f0 and.w r3, r3, #240 @ 0xf0
80022b4: 429a cmp r2, r3
80022b6: d908 bls.n 80022ca <HAL_RCC_ClockConfig+0x72>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
80022b8: 4b63 ldr r3, [pc, #396] @ (8002448 <HAL_RCC_ClockConfig+0x1f0>)
80022ba: 689b ldr r3, [r3, #8]
80022bc: f023 02f0 bic.w r2, r3, #240 @ 0xf0
80022c0: 687b ldr r3, [r7, #4]
80022c2: 689b ldr r3, [r3, #8]
80022c4: 4960 ldr r1, [pc, #384] @ (8002448 <HAL_RCC_ClockConfig+0x1f0>)
80022c6: 4313 orrs r3, r2
80022c8: 608b str r3, [r1, #8]
}
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
80022ca: 687b ldr r3, [r7, #4]
80022cc: 681b ldr r3, [r3, #0]
80022ce: f003 0301 and.w r3, r3, #1
80022d2: 2b00 cmp r3, #0
80022d4: d04c beq.n 8002370 <HAL_RCC_ClockConfig+0x118>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* PLL is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
80022d6: 687b ldr r3, [r7, #4]
80022d8: 685b ldr r3, [r3, #4]
80022da: 2b03 cmp r3, #3
80022dc: d107 bne.n 80022ee <HAL_RCC_ClockConfig+0x96>
{
/* Check the PLL ready flag */
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
80022de: 4b5a ldr r3, [pc, #360] @ (8002448 <HAL_RCC_ClockConfig+0x1f0>)
80022e0: 681b ldr r3, [r3, #0]
80022e2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80022e6: 2b00 cmp r3, #0
80022e8: d121 bne.n 800232e <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
80022ea: 2301 movs r3, #1
80022ec: e0a6 b.n 800243c <HAL_RCC_ClockConfig+0x1e4>
#endif
}
else
{
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
80022ee: 687b ldr r3, [r7, #4]
80022f0: 685b ldr r3, [r3, #4]
80022f2: 2b02 cmp r3, #2
80022f4: d107 bne.n 8002306 <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
80022f6: 4b54 ldr r3, [pc, #336] @ (8002448 <HAL_RCC_ClockConfig+0x1f0>)
80022f8: 681b ldr r3, [r3, #0]
80022fa: f403 3300 and.w r3, r3, #131072 @ 0x20000
80022fe: 2b00 cmp r3, #0
8002300: d115 bne.n 800232e <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
8002302: 2301 movs r3, #1
8002304: e09a b.n 800243c <HAL_RCC_ClockConfig+0x1e4>
}
}
/* MSI is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
8002306: 687b ldr r3, [r7, #4]
8002308: 685b ldr r3, [r3, #4]
800230a: 2b00 cmp r3, #0
800230c: d107 bne.n 800231e <HAL_RCC_ClockConfig+0xc6>
{
/* Check the MSI ready flag */
if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
800230e: 4b4e ldr r3, [pc, #312] @ (8002448 <HAL_RCC_ClockConfig+0x1f0>)
8002310: 681b ldr r3, [r3, #0]
8002312: f003 0302 and.w r3, r3, #2
8002316: 2b00 cmp r3, #0
8002318: d109 bne.n 800232e <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
800231a: 2301 movs r3, #1
800231c: e08e b.n 800243c <HAL_RCC_ClockConfig+0x1e4>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
800231e: 4b4a ldr r3, [pc, #296] @ (8002448 <HAL_RCC_ClockConfig+0x1f0>)
8002320: 681b ldr r3, [r3, #0]
8002322: f403 6380 and.w r3, r3, #1024 @ 0x400
8002326: 2b00 cmp r3, #0
8002328: d101 bne.n 800232e <HAL_RCC_ClockConfig+0xd6>
{
return HAL_ERROR;
800232a: 2301 movs r3, #1
800232c: e086 b.n 800243c <HAL_RCC_ClockConfig+0x1e4>
}
#endif
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
800232e: 4b46 ldr r3, [pc, #280] @ (8002448 <HAL_RCC_ClockConfig+0x1f0>)
8002330: 689b ldr r3, [r3, #8]
8002332: f023 0203 bic.w r2, r3, #3
8002336: 687b ldr r3, [r7, #4]
8002338: 685b ldr r3, [r3, #4]
800233a: 4943 ldr r1, [pc, #268] @ (8002448 <HAL_RCC_ClockConfig+0x1f0>)
800233c: 4313 orrs r3, r2
800233e: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002340: f7ff f8c0 bl 80014c4 <HAL_GetTick>
8002344: 60f8 str r0, [r7, #12]
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8002346: e00a b.n 800235e <HAL_RCC_ClockConfig+0x106>
{
if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8002348: f7ff f8bc bl 80014c4 <HAL_GetTick>
800234c: 4602 mov r2, r0
800234e: 68fb ldr r3, [r7, #12]
8002350: 1ad3 subs r3, r2, r3
8002352: f241 3288 movw r2, #5000 @ 0x1388
8002356: 4293 cmp r3, r2
8002358: d901 bls.n 800235e <HAL_RCC_ClockConfig+0x106>
{
return HAL_TIMEOUT;
800235a: 2303 movs r3, #3
800235c: e06e b.n 800243c <HAL_RCC_ClockConfig+0x1e4>
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800235e: 4b3a ldr r3, [pc, #232] @ (8002448 <HAL_RCC_ClockConfig+0x1f0>)
8002360: 689b ldr r3, [r3, #8]
8002362: f003 020c and.w r2, r3, #12
8002366: 687b ldr r3, [r7, #4]
8002368: 685b ldr r3, [r3, #4]
800236a: 009b lsls r3, r3, #2
800236c: 429a cmp r2, r3
800236e: d1eb bne.n 8002348 <HAL_RCC_ClockConfig+0xf0>
}
#endif
/*----------------- HCLK Configuration after SYSCLK-------------------------*/
/* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002370: 687b ldr r3, [r7, #4]
8002372: 681b ldr r3, [r3, #0]
8002374: f003 0302 and.w r3, r3, #2
8002378: 2b00 cmp r3, #0
800237a: d010 beq.n 800239e <HAL_RCC_ClockConfig+0x146>
{
if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
800237c: 687b ldr r3, [r7, #4]
800237e: 689a ldr r2, [r3, #8]
8002380: 4b31 ldr r3, [pc, #196] @ (8002448 <HAL_RCC_ClockConfig+0x1f0>)
8002382: 689b ldr r3, [r3, #8]
8002384: f003 03f0 and.w r3, r3, #240 @ 0xf0
8002388: 429a cmp r2, r3
800238a: d208 bcs.n 800239e <HAL_RCC_ClockConfig+0x146>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
800238c: 4b2e ldr r3, [pc, #184] @ (8002448 <HAL_RCC_ClockConfig+0x1f0>)
800238e: 689b ldr r3, [r3, #8]
8002390: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8002394: 687b ldr r3, [r7, #4]
8002396: 689b ldr r3, [r3, #8]
8002398: 492b ldr r1, [pc, #172] @ (8002448 <HAL_RCC_ClockConfig+0x1f0>)
800239a: 4313 orrs r3, r2
800239c: 608b str r3, [r1, #8]
}
}
/* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */
if(FLatency < __HAL_FLASH_GET_LATENCY())
800239e: 4b29 ldr r3, [pc, #164] @ (8002444 <HAL_RCC_ClockConfig+0x1ec>)
80023a0: 681b ldr r3, [r3, #0]
80023a2: f003 0307 and.w r3, r3, #7
80023a6: 683a ldr r2, [r7, #0]
80023a8: 429a cmp r2, r3
80023aa: d210 bcs.n 80023ce <HAL_RCC_ClockConfig+0x176>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80023ac: 4b25 ldr r3, [pc, #148] @ (8002444 <HAL_RCC_ClockConfig+0x1ec>)
80023ae: 681b ldr r3, [r3, #0]
80023b0: f023 0207 bic.w r2, r3, #7
80023b4: 4923 ldr r1, [pc, #140] @ (8002444 <HAL_RCC_ClockConfig+0x1ec>)
80023b6: 683b ldr r3, [r7, #0]
80023b8: 4313 orrs r3, r2
80023ba: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80023bc: 4b21 ldr r3, [pc, #132] @ (8002444 <HAL_RCC_ClockConfig+0x1ec>)
80023be: 681b ldr r3, [r3, #0]
80023c0: f003 0307 and.w r3, r3, #7
80023c4: 683a ldr r2, [r7, #0]
80023c6: 429a cmp r2, r3
80023c8: d001 beq.n 80023ce <HAL_RCC_ClockConfig+0x176>
{
return HAL_ERROR;
80023ca: 2301 movs r3, #1
80023cc: e036 b.n 800243c <HAL_RCC_ClockConfig+0x1e4>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80023ce: 687b ldr r3, [r7, #4]
80023d0: 681b ldr r3, [r3, #0]
80023d2: f003 0304 and.w r3, r3, #4
80023d6: 2b00 cmp r3, #0
80023d8: d008 beq.n 80023ec <HAL_RCC_ClockConfig+0x194>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
80023da: 4b1b ldr r3, [pc, #108] @ (8002448 <HAL_RCC_ClockConfig+0x1f0>)
80023dc: 689b ldr r3, [r3, #8]
80023de: f423 62e0 bic.w r2, r3, #1792 @ 0x700
80023e2: 687b ldr r3, [r7, #4]
80023e4: 68db ldr r3, [r3, #12]
80023e6: 4918 ldr r1, [pc, #96] @ (8002448 <HAL_RCC_ClockConfig+0x1f0>)
80023e8: 4313 orrs r3, r2
80023ea: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80023ec: 687b ldr r3, [r7, #4]
80023ee: 681b ldr r3, [r3, #0]
80023f0: f003 0308 and.w r3, r3, #8
80023f4: 2b00 cmp r3, #0
80023f6: d009 beq.n 800240c <HAL_RCC_ClockConfig+0x1b4>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
80023f8: 4b13 ldr r3, [pc, #76] @ (8002448 <HAL_RCC_ClockConfig+0x1f0>)
80023fa: 689b ldr r3, [r3, #8]
80023fc: f423 5260 bic.w r2, r3, #14336 @ 0x3800
8002400: 687b ldr r3, [r7, #4]
8002402: 691b ldr r3, [r3, #16]
8002404: 00db lsls r3, r3, #3
8002406: 4910 ldr r1, [pc, #64] @ (8002448 <HAL_RCC_ClockConfig+0x1f0>)
8002408: 4313 orrs r3, r2
800240a: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
800240c: f000 f824 bl 8002458 <HAL_RCC_GetSysClockFreq>
8002410: 4602 mov r2, r0
8002412: 4b0d ldr r3, [pc, #52] @ (8002448 <HAL_RCC_ClockConfig+0x1f0>)
8002414: 689b ldr r3, [r3, #8]
8002416: 091b lsrs r3, r3, #4
8002418: f003 030f and.w r3, r3, #15
800241c: 490b ldr r1, [pc, #44] @ (800244c <HAL_RCC_ClockConfig+0x1f4>)
800241e: 5ccb ldrb r3, [r1, r3]
8002420: f003 031f and.w r3, r3, #31
8002424: fa22 f303 lsr.w r3, r2, r3
8002428: 4a09 ldr r2, [pc, #36] @ (8002450 <HAL_RCC_ClockConfig+0x1f8>)
800242a: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
800242c: 4b09 ldr r3, [pc, #36] @ (8002454 <HAL_RCC_ClockConfig+0x1fc>)
800242e: 681b ldr r3, [r3, #0]
8002430: 4618 mov r0, r3
8002432: f7fe fff7 bl 8001424 <HAL_InitTick>
8002436: 4603 mov r3, r0
8002438: 72fb strb r3, [r7, #11]
return status;
800243a: 7afb ldrb r3, [r7, #11]
}
800243c: 4618 mov r0, r3
800243e: 3710 adds r7, #16
8002440: 46bd mov sp, r7
8002442: bd80 pop {r7, pc}
8002444: 40022000 .word 0x40022000
8002448: 40021000 .word 0x40021000
800244c: 08005648 .word 0x08005648
8002450: 20000000 .word 0x20000000
8002454: 20000004 .word 0x20000004
08002458 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8002458: b480 push {r7}
800245a: b089 sub sp, #36 @ 0x24
800245c: af00 add r7, sp, #0
uint32_t msirange = 0U, sysclockfreq = 0U;
800245e: 2300 movs r3, #0
8002460: 61fb str r3, [r7, #28]
8002462: 2300 movs r3, #0
8002464: 61bb str r3, [r7, #24]
uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */
uint32_t sysclk_source, pll_oscsource;
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
8002466: 4b3e ldr r3, [pc, #248] @ (8002560 <HAL_RCC_GetSysClockFreq+0x108>)
8002468: 689b ldr r3, [r3, #8]
800246a: f003 030c and.w r3, r3, #12
800246e: 613b str r3, [r7, #16]
pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
8002470: 4b3b ldr r3, [pc, #236] @ (8002560 <HAL_RCC_GetSysClockFreq+0x108>)
8002472: 68db ldr r3, [r3, #12]
8002474: f003 0303 and.w r3, r3, #3
8002478: 60fb str r3, [r7, #12]
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
800247a: 693b ldr r3, [r7, #16]
800247c: 2b00 cmp r3, #0
800247e: d005 beq.n 800248c <HAL_RCC_GetSysClockFreq+0x34>
8002480: 693b ldr r3, [r7, #16]
8002482: 2b0c cmp r3, #12
8002484: d121 bne.n 80024ca <HAL_RCC_GetSysClockFreq+0x72>
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
8002486: 68fb ldr r3, [r7, #12]
8002488: 2b01 cmp r3, #1
800248a: d11e bne.n 80024ca <HAL_RCC_GetSysClockFreq+0x72>
{
/* MSI or PLL with MSI source used as system clock source */
/* Get SYSCLK source */
if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
800248c: 4b34 ldr r3, [pc, #208] @ (8002560 <HAL_RCC_GetSysClockFreq+0x108>)
800248e: 681b ldr r3, [r3, #0]
8002490: f003 0308 and.w r3, r3, #8
8002494: 2b00 cmp r3, #0
8002496: d107 bne.n 80024a8 <HAL_RCC_GetSysClockFreq+0x50>
{ /* MSISRANGE from RCC_CSR applies */
msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
8002498: 4b31 ldr r3, [pc, #196] @ (8002560 <HAL_RCC_GetSysClockFreq+0x108>)
800249a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
800249e: 0a1b lsrs r3, r3, #8
80024a0: f003 030f and.w r3, r3, #15
80024a4: 61fb str r3, [r7, #28]
80024a6: e005 b.n 80024b4 <HAL_RCC_GetSysClockFreq+0x5c>
}
else
{ /* MSIRANGE from RCC_CR applies */
msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
80024a8: 4b2d ldr r3, [pc, #180] @ (8002560 <HAL_RCC_GetSysClockFreq+0x108>)
80024aa: 681b ldr r3, [r3, #0]
80024ac: 091b lsrs r3, r3, #4
80024ae: f003 030f and.w r3, r3, #15
80024b2: 61fb str r3, [r7, #28]
}
/*MSI frequency range in HZ*/
msirange = MSIRangeTable[msirange];
80024b4: 4a2b ldr r2, [pc, #172] @ (8002564 <HAL_RCC_GetSysClockFreq+0x10c>)
80024b6: 69fb ldr r3, [r7, #28]
80024b8: f852 3023 ldr.w r3, [r2, r3, lsl #2]
80024bc: 61fb str r3, [r7, #28]
if(sysclk_source == RCC_CFGR_SWS_MSI)
80024be: 693b ldr r3, [r7, #16]
80024c0: 2b00 cmp r3, #0
80024c2: d10d bne.n 80024e0 <HAL_RCC_GetSysClockFreq+0x88>
{
/* MSI used as system clock source */
sysclockfreq = msirange;
80024c4: 69fb ldr r3, [r7, #28]
80024c6: 61bb str r3, [r7, #24]
if(sysclk_source == RCC_CFGR_SWS_MSI)
80024c8: e00a b.n 80024e0 <HAL_RCC_GetSysClockFreq+0x88>
}
}
else if(sysclk_source == RCC_CFGR_SWS_HSI)
80024ca: 693b ldr r3, [r7, #16]
80024cc: 2b04 cmp r3, #4
80024ce: d102 bne.n 80024d6 <HAL_RCC_GetSysClockFreq+0x7e>
{
/* HSI used as system clock source */
sysclockfreq = HSI_VALUE;
80024d0: 4b25 ldr r3, [pc, #148] @ (8002568 <HAL_RCC_GetSysClockFreq+0x110>)
80024d2: 61bb str r3, [r7, #24]
80024d4: e004 b.n 80024e0 <HAL_RCC_GetSysClockFreq+0x88>
}
else if(sysclk_source == RCC_CFGR_SWS_HSE)
80024d6: 693b ldr r3, [r7, #16]
80024d8: 2b08 cmp r3, #8
80024da: d101 bne.n 80024e0 <HAL_RCC_GetSysClockFreq+0x88>
{
/* HSE used as system clock source */
sysclockfreq = HSE_VALUE;
80024dc: 4b23 ldr r3, [pc, #140] @ (800256c <HAL_RCC_GetSysClockFreq+0x114>)
80024de: 61bb str r3, [r7, #24]
else
{
/* unexpected case: sysclockfreq at 0 */
}
if(sysclk_source == RCC_CFGR_SWS_PLL)
80024e0: 693b ldr r3, [r7, #16]
80024e2: 2b0c cmp r3, #12
80024e4: d134 bne.n 8002550 <HAL_RCC_GetSysClockFreq+0xf8>
/* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
SYSCLK = PLL_VCO / PLLR
*/
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
80024e6: 4b1e ldr r3, [pc, #120] @ (8002560 <HAL_RCC_GetSysClockFreq+0x108>)
80024e8: 68db ldr r3, [r3, #12]
80024ea: f003 0303 and.w r3, r3, #3
80024ee: 60bb str r3, [r7, #8]
switch (pllsource)
80024f0: 68bb ldr r3, [r7, #8]
80024f2: 2b02 cmp r3, #2
80024f4: d003 beq.n 80024fe <HAL_RCC_GetSysClockFreq+0xa6>
80024f6: 68bb ldr r3, [r7, #8]
80024f8: 2b03 cmp r3, #3
80024fa: d003 beq.n 8002504 <HAL_RCC_GetSysClockFreq+0xac>
80024fc: e005 b.n 800250a <HAL_RCC_GetSysClockFreq+0xb2>
{
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
pllvco = HSI_VALUE;
80024fe: 4b1a ldr r3, [pc, #104] @ (8002568 <HAL_RCC_GetSysClockFreq+0x110>)
8002500: 617b str r3, [r7, #20]
break;
8002502: e005 b.n 8002510 <HAL_RCC_GetSysClockFreq+0xb8>
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = HSE_VALUE;
8002504: 4b19 ldr r3, [pc, #100] @ (800256c <HAL_RCC_GetSysClockFreq+0x114>)
8002506: 617b str r3, [r7, #20]
break;
8002508: e002 b.n 8002510 <HAL_RCC_GetSysClockFreq+0xb8>
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
default:
pllvco = msirange;
800250a: 69fb ldr r3, [r7, #28]
800250c: 617b str r3, [r7, #20]
break;
800250e: bf00 nop
}
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
8002510: 4b13 ldr r3, [pc, #76] @ (8002560 <HAL_RCC_GetSysClockFreq+0x108>)
8002512: 68db ldr r3, [r3, #12]
8002514: 091b lsrs r3, r3, #4
8002516: f003 0307 and.w r3, r3, #7
800251a: 3301 adds r3, #1
800251c: 607b str r3, [r7, #4]
pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;
800251e: 4b10 ldr r3, [pc, #64] @ (8002560 <HAL_RCC_GetSysClockFreq+0x108>)
8002520: 68db ldr r3, [r3, #12]
8002522: 0a1b lsrs r3, r3, #8
8002524: f003 037f and.w r3, r3, #127 @ 0x7f
8002528: 697a ldr r2, [r7, #20]
800252a: fb03 f202 mul.w r2, r3, r2
800252e: 687b ldr r3, [r7, #4]
8002530: fbb2 f3f3 udiv r3, r2, r3
8002534: 617b str r3, [r7, #20]
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
8002536: 4b0a ldr r3, [pc, #40] @ (8002560 <HAL_RCC_GetSysClockFreq+0x108>)
8002538: 68db ldr r3, [r3, #12]
800253a: 0e5b lsrs r3, r3, #25
800253c: f003 0303 and.w r3, r3, #3
8002540: 3301 adds r3, #1
8002542: 005b lsls r3, r3, #1
8002544: 603b str r3, [r7, #0]
sysclockfreq = pllvco / pllr;
8002546: 697a ldr r2, [r7, #20]
8002548: 683b ldr r3, [r7, #0]
800254a: fbb2 f3f3 udiv r3, r2, r3
800254e: 61bb str r3, [r7, #24]
}
return sysclockfreq;
8002550: 69bb ldr r3, [r7, #24]
}
8002552: 4618 mov r0, r3
8002554: 3724 adds r7, #36 @ 0x24
8002556: 46bd mov sp, r7
8002558: f85d 7b04 ldr.w r7, [sp], #4
800255c: 4770 bx lr
800255e: bf00 nop
8002560: 40021000 .word 0x40021000
8002564: 08005658 .word 0x08005658
8002568: 00f42400 .word 0x00f42400
800256c: 007a1200 .word 0x007a1200
08002570 <RCC_SetFlashLatencyFromMSIRange>:
voltage range.
* @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
* @retval HAL status
*/
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
{
8002570: b580 push {r7, lr}
8002572: b086 sub sp, #24
8002574: af00 add r7, sp, #0
8002576: 6078 str r0, [r7, #4]
uint32_t vos;
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
8002578: 2300 movs r3, #0
800257a: 613b str r3, [r7, #16]
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
800257c: 4b2a ldr r3, [pc, #168] @ (8002628 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
800257e: 6d9b ldr r3, [r3, #88] @ 0x58
8002580: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002584: 2b00 cmp r3, #0
8002586: d003 beq.n 8002590 <RCC_SetFlashLatencyFromMSIRange+0x20>
{
vos = HAL_PWREx_GetVoltageRange();
8002588: f7ff fa44 bl 8001a14 <HAL_PWREx_GetVoltageRange>
800258c: 6178 str r0, [r7, #20]
800258e: e014 b.n 80025ba <RCC_SetFlashLatencyFromMSIRange+0x4a>
}
else
{
__HAL_RCC_PWR_CLK_ENABLE();
8002590: 4b25 ldr r3, [pc, #148] @ (8002628 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8002592: 6d9b ldr r3, [r3, #88] @ 0x58
8002594: 4a24 ldr r2, [pc, #144] @ (8002628 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8002596: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800259a: 6593 str r3, [r2, #88] @ 0x58
800259c: 4b22 ldr r3, [pc, #136] @ (8002628 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
800259e: 6d9b ldr r3, [r3, #88] @ 0x58
80025a0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80025a4: 60fb str r3, [r7, #12]
80025a6: 68fb ldr r3, [r7, #12]
vos = HAL_PWREx_GetVoltageRange();
80025a8: f7ff fa34 bl 8001a14 <HAL_PWREx_GetVoltageRange>
80025ac: 6178 str r0, [r7, #20]
__HAL_RCC_PWR_CLK_DISABLE();
80025ae: 4b1e ldr r3, [pc, #120] @ (8002628 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
80025b0: 6d9b ldr r3, [r3, #88] @ 0x58
80025b2: 4a1d ldr r2, [pc, #116] @ (8002628 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
80025b4: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80025b8: 6593 str r3, [r2, #88] @ 0x58
}
if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
80025ba: 697b ldr r3, [r7, #20]
80025bc: f5b3 7f00 cmp.w r3, #512 @ 0x200
80025c0: d10b bne.n 80025da <RCC_SetFlashLatencyFromMSIRange+0x6a>
{
if(msirange > RCC_MSIRANGE_8)
80025c2: 687b ldr r3, [r7, #4]
80025c4: 2b80 cmp r3, #128 @ 0x80
80025c6: d919 bls.n 80025fc <RCC_SetFlashLatencyFromMSIRange+0x8c>
{
/* MSI > 16Mhz */
if(msirange > RCC_MSIRANGE_10)
80025c8: 687b ldr r3, [r7, #4]
80025ca: 2ba0 cmp r3, #160 @ 0xa0
80025cc: d902 bls.n 80025d4 <RCC_SetFlashLatencyFromMSIRange+0x64>
{
/* MSI 48Mhz */
latency = FLASH_LATENCY_2; /* 2WS */
80025ce: 2302 movs r3, #2
80025d0: 613b str r3, [r7, #16]
80025d2: e013 b.n 80025fc <RCC_SetFlashLatencyFromMSIRange+0x8c>
}
else
{
/* MSI 24Mhz or 32Mhz */
latency = FLASH_LATENCY_1; /* 1WS */
80025d4: 2301 movs r3, #1
80025d6: 613b str r3, [r7, #16]
80025d8: e010 b.n 80025fc <RCC_SetFlashLatencyFromMSIRange+0x8c>
latency = FLASH_LATENCY_1; /* 1WS */
}
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
}
#else
if(msirange > RCC_MSIRANGE_8)
80025da: 687b ldr r3, [r7, #4]
80025dc: 2b80 cmp r3, #128 @ 0x80
80025de: d902 bls.n 80025e6 <RCC_SetFlashLatencyFromMSIRange+0x76>
{
/* MSI > 16Mhz */
latency = FLASH_LATENCY_3; /* 3WS */
80025e0: 2303 movs r3, #3
80025e2: 613b str r3, [r7, #16]
80025e4: e00a b.n 80025fc <RCC_SetFlashLatencyFromMSIRange+0x8c>
}
else
{
if(msirange == RCC_MSIRANGE_8)
80025e6: 687b ldr r3, [r7, #4]
80025e8: 2b80 cmp r3, #128 @ 0x80
80025ea: d102 bne.n 80025f2 <RCC_SetFlashLatencyFromMSIRange+0x82>
{
/* MSI 16Mhz */
latency = FLASH_LATENCY_2; /* 2WS */
80025ec: 2302 movs r3, #2
80025ee: 613b str r3, [r7, #16]
80025f0: e004 b.n 80025fc <RCC_SetFlashLatencyFromMSIRange+0x8c>
}
else if(msirange == RCC_MSIRANGE_7)
80025f2: 687b ldr r3, [r7, #4]
80025f4: 2b70 cmp r3, #112 @ 0x70
80025f6: d101 bne.n 80025fc <RCC_SetFlashLatencyFromMSIRange+0x8c>
{
/* MSI 8Mhz */
latency = FLASH_LATENCY_1; /* 1WS */
80025f8: 2301 movs r3, #1
80025fa: 613b str r3, [r7, #16]
}
}
#endif
}
__HAL_FLASH_SET_LATENCY(latency);
80025fc: 4b0b ldr r3, [pc, #44] @ (800262c <RCC_SetFlashLatencyFromMSIRange+0xbc>)
80025fe: 681b ldr r3, [r3, #0]
8002600: f023 0207 bic.w r2, r3, #7
8002604: 4909 ldr r1, [pc, #36] @ (800262c <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8002606: 693b ldr r3, [r7, #16]
8002608: 4313 orrs r3, r2
800260a: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != latency)
800260c: 4b07 ldr r3, [pc, #28] @ (800262c <RCC_SetFlashLatencyFromMSIRange+0xbc>)
800260e: 681b ldr r3, [r3, #0]
8002610: f003 0307 and.w r3, r3, #7
8002614: 693a ldr r2, [r7, #16]
8002616: 429a cmp r2, r3
8002618: d001 beq.n 800261e <RCC_SetFlashLatencyFromMSIRange+0xae>
{
return HAL_ERROR;
800261a: 2301 movs r3, #1
800261c: e000 b.n 8002620 <RCC_SetFlashLatencyFromMSIRange+0xb0>
}
return HAL_OK;
800261e: 2300 movs r3, #0
}
8002620: 4618 mov r0, r3
8002622: 3718 adds r7, #24
8002624: 46bd mov sp, r7
8002626: bd80 pop {r7, pc}
8002628: 40021000 .word 0x40021000
800262c: 40022000 .word 0x40022000
08002630 <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
8002630: b580 push {r7, lr}
8002632: b084 sub sp, #16
8002634: af00 add r7, sp, #0
8002636: 6078 str r0, [r7, #4]
uint32_t frxth;
/* Check the SPI handle allocation */
if (hspi == NULL)
8002638: 687b ldr r3, [r7, #4]
800263a: 2b00 cmp r3, #0
800263c: d101 bne.n 8002642 <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
800263e: 2301 movs r3, #1
8002640: e095 b.n 800276e <HAL_SPI_Init+0x13e>
assert_param(IS_SPI_NSS(hspi->Init.NSS));
assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
8002642: 687b ldr r3, [r7, #4]
8002644: 6a5b ldr r3, [r3, #36] @ 0x24
8002646: 2b00 cmp r3, #0
8002648: d108 bne.n 800265c <HAL_SPI_Init+0x2c>
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
if (hspi->Init.Mode == SPI_MODE_MASTER)
800264a: 687b ldr r3, [r7, #4]
800264c: 685b ldr r3, [r3, #4]
800264e: f5b3 7f82 cmp.w r3, #260 @ 0x104
8002652: d009 beq.n 8002668 <HAL_SPI_Init+0x38>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
}
else
{
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
8002654: 687b ldr r3, [r7, #4]
8002656: 2200 movs r2, #0
8002658: 61da str r2, [r3, #28]
800265a: e005 b.n 8002668 <HAL_SPI_Init+0x38>
else
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
/* Force polarity and phase to TI protocaol requirements */
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
800265c: 687b ldr r3, [r7, #4]
800265e: 2200 movs r2, #0
8002660: 611a str r2, [r3, #16]
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
8002662: 687b ldr r3, [r7, #4]
8002664: 2200 movs r2, #0
8002666: 615a str r2, [r3, #20]
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8002668: 687b ldr r3, [r7, #4]
800266a: 2200 movs r2, #0
800266c: 629a str r2, [r3, #40] @ 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
800266e: 687b ldr r3, [r7, #4]
8002670: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
8002674: b2db uxtb r3, r3
8002676: 2b00 cmp r3, #0
8002678: d106 bne.n 8002688 <HAL_SPI_Init+0x58>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
800267a: 687b ldr r3, [r7, #4]
800267c: 2200 movs r2, #0
800267e: f883 205c strb.w r2, [r3, #92] @ 0x5c
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
8002682: 6878 ldr r0, [r7, #4]
8002684: f7fe fd38 bl 80010f8 <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
8002688: 687b ldr r3, [r7, #4]
800268a: 2202 movs r2, #2
800268c: f883 205d strb.w r2, [r3, #93] @ 0x5d
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8002690: 687b ldr r3, [r7, #4]
8002692: 681b ldr r3, [r3, #0]
8002694: 681a ldr r2, [r3, #0]
8002696: 687b ldr r3, [r7, #4]
8002698: 681b ldr r3, [r3, #0]
800269a: f022 0240 bic.w r2, r2, #64 @ 0x40
800269e: 601a str r2, [r3, #0]
/* Align by default the rs fifo threshold on the data size */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
80026a0: 687b ldr r3, [r7, #4]
80026a2: 68db ldr r3, [r3, #12]
80026a4: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
80026a8: d902 bls.n 80026b0 <HAL_SPI_Init+0x80>
{
frxth = SPI_RXFIFO_THRESHOLD_HF;
80026aa: 2300 movs r3, #0
80026ac: 60fb str r3, [r7, #12]
80026ae: e002 b.n 80026b6 <HAL_SPI_Init+0x86>
}
else
{
frxth = SPI_RXFIFO_THRESHOLD_QF;
80026b0: f44f 5380 mov.w r3, #4096 @ 0x1000
80026b4: 60fb str r3, [r7, #12]
}
/* CRC calculation is valid only for 16Bit and 8 Bit */
if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
80026b6: 687b ldr r3, [r7, #4]
80026b8: 68db ldr r3, [r3, #12]
80026ba: f5b3 6f70 cmp.w r3, #3840 @ 0xf00
80026be: d007 beq.n 80026d0 <HAL_SPI_Init+0xa0>
80026c0: 687b ldr r3, [r7, #4]
80026c2: 68db ldr r3, [r3, #12]
80026c4: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
80026c8: d002 beq.n 80026d0 <HAL_SPI_Init+0xa0>
{
/* CRC must be disabled */
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
80026ca: 687b ldr r3, [r7, #4]
80026cc: 2200 movs r2, #0
80026ce: 629a str r2, [r3, #40] @ 0x28
}
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
80026d0: 687b ldr r3, [r7, #4]
80026d2: 685b ldr r3, [r3, #4]
80026d4: f403 7282 and.w r2, r3, #260 @ 0x104
80026d8: 687b ldr r3, [r7, #4]
80026da: 689b ldr r3, [r3, #8]
80026dc: f403 4304 and.w r3, r3, #33792 @ 0x8400
80026e0: 431a orrs r2, r3
80026e2: 687b ldr r3, [r7, #4]
80026e4: 691b ldr r3, [r3, #16]
80026e6: f003 0302 and.w r3, r3, #2
80026ea: 431a orrs r2, r3
80026ec: 687b ldr r3, [r7, #4]
80026ee: 695b ldr r3, [r3, #20]
80026f0: f003 0301 and.w r3, r3, #1
80026f4: 431a orrs r2, r3
80026f6: 687b ldr r3, [r7, #4]
80026f8: 699b ldr r3, [r3, #24]
80026fa: f403 7300 and.w r3, r3, #512 @ 0x200
80026fe: 431a orrs r2, r3
8002700: 687b ldr r3, [r7, #4]
8002702: 69db ldr r3, [r3, #28]
8002704: f003 0338 and.w r3, r3, #56 @ 0x38
8002708: 431a orrs r2, r3
800270a: 687b ldr r3, [r7, #4]
800270c: 6a1b ldr r3, [r3, #32]
800270e: f003 0380 and.w r3, r3, #128 @ 0x80
8002712: ea42 0103 orr.w r1, r2, r3
8002716: 687b ldr r3, [r7, #4]
8002718: 6a9b ldr r3, [r3, #40] @ 0x28
800271a: f403 5200 and.w r2, r3, #8192 @ 0x2000
800271e: 687b ldr r3, [r7, #4]
8002720: 681b ldr r3, [r3, #0]
8002722: 430a orrs r2, r1
8002724: 601a str r2, [r3, #0]
}
}
#endif /* USE_SPI_CRC */
/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
8002726: 687b ldr r3, [r7, #4]
8002728: 699b ldr r3, [r3, #24]
800272a: 0c1b lsrs r3, r3, #16
800272c: f003 0204 and.w r2, r3, #4
8002730: 687b ldr r3, [r7, #4]
8002732: 6a5b ldr r3, [r3, #36] @ 0x24
8002734: f003 0310 and.w r3, r3, #16
8002738: 431a orrs r2, r3
800273a: 687b ldr r3, [r7, #4]
800273c: 6b5b ldr r3, [r3, #52] @ 0x34
800273e: f003 0308 and.w r3, r3, #8
8002742: 431a orrs r2, r3
8002744: 687b ldr r3, [r7, #4]
8002746: 68db ldr r3, [r3, #12]
8002748: f403 6370 and.w r3, r3, #3840 @ 0xf00
800274c: ea42 0103 orr.w r1, r2, r3
8002750: 68fb ldr r3, [r7, #12]
8002752: f403 5280 and.w r2, r3, #4096 @ 0x1000
8002756: 687b ldr r3, [r7, #4]
8002758: 681b ldr r3, [r3, #0]
800275a: 430a orrs r2, r1
800275c: 605a str r2, [r3, #4]
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
800275e: 687b ldr r3, [r7, #4]
8002760: 2200 movs r2, #0
8002762: 661a str r2, [r3, #96] @ 0x60
hspi->State = HAL_SPI_STATE_READY;
8002764: 687b ldr r3, [r7, #4]
8002766: 2201 movs r2, #1
8002768: f883 205d strb.w r2, [r3, #93] @ 0x5d
return HAL_OK;
800276c: 2300 movs r3, #0
}
800276e: 4618 mov r0, r3
8002770: 3710 adds r7, #16
8002772: 46bd mov sp, r7
8002774: bd80 pop {r7, pc}
08002776 <HAL_SPI_Transmit>:
* @param Size amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8002776: b580 push {r7, lr}
8002778: b088 sub sp, #32
800277a: af00 add r7, sp, #0
800277c: 60f8 str r0, [r7, #12]
800277e: 60b9 str r1, [r7, #8]
8002780: 603b str r3, [r7, #0]
8002782: 4613 mov r3, r2
8002784: 80fb strh r3, [r7, #6]
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
8002786: f7fe fe9d bl 80014c4 <HAL_GetTick>
800278a: 61f8 str r0, [r7, #28]
initial_TxXferCount = Size;
800278c: 88fb ldrh r3, [r7, #6]
800278e: 837b strh r3, [r7, #26]
if (hspi->State != HAL_SPI_STATE_READY)
8002790: 68fb ldr r3, [r7, #12]
8002792: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
8002796: b2db uxtb r3, r3
8002798: 2b01 cmp r3, #1
800279a: d001 beq.n 80027a0 <HAL_SPI_Transmit+0x2a>
{
return HAL_BUSY;
800279c: 2302 movs r3, #2
800279e: e15c b.n 8002a5a <HAL_SPI_Transmit+0x2e4>
}
if ((pData == NULL) || (Size == 0U))
80027a0: 68bb ldr r3, [r7, #8]
80027a2: 2b00 cmp r3, #0
80027a4: d002 beq.n 80027ac <HAL_SPI_Transmit+0x36>
80027a6: 88fb ldrh r3, [r7, #6]
80027a8: 2b00 cmp r3, #0
80027aa: d101 bne.n 80027b0 <HAL_SPI_Transmit+0x3a>
{
return HAL_ERROR;
80027ac: 2301 movs r3, #1
80027ae: e154 b.n 8002a5a <HAL_SPI_Transmit+0x2e4>
}
/* Process Locked */
__HAL_LOCK(hspi);
80027b0: 68fb ldr r3, [r7, #12]
80027b2: f893 305c ldrb.w r3, [r3, #92] @ 0x5c
80027b6: 2b01 cmp r3, #1
80027b8: d101 bne.n 80027be <HAL_SPI_Transmit+0x48>
80027ba: 2302 movs r3, #2
80027bc: e14d b.n 8002a5a <HAL_SPI_Transmit+0x2e4>
80027be: 68fb ldr r3, [r7, #12]
80027c0: 2201 movs r2, #1
80027c2: f883 205c strb.w r2, [r3, #92] @ 0x5c
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
80027c6: 68fb ldr r3, [r7, #12]
80027c8: 2203 movs r2, #3
80027ca: f883 205d strb.w r2, [r3, #93] @ 0x5d
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
80027ce: 68fb ldr r3, [r7, #12]
80027d0: 2200 movs r2, #0
80027d2: 661a str r2, [r3, #96] @ 0x60
hspi->pTxBuffPtr = (const uint8_t *)pData;
80027d4: 68fb ldr r3, [r7, #12]
80027d6: 68ba ldr r2, [r7, #8]
80027d8: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferSize = Size;
80027da: 68fb ldr r3, [r7, #12]
80027dc: 88fa ldrh r2, [r7, #6]
80027de: 879a strh r2, [r3, #60] @ 0x3c
hspi->TxXferCount = Size;
80027e0: 68fb ldr r3, [r7, #12]
80027e2: 88fa ldrh r2, [r7, #6]
80027e4: 87da strh r2, [r3, #62] @ 0x3e
/*Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
80027e6: 68fb ldr r3, [r7, #12]
80027e8: 2200 movs r2, #0
80027ea: 641a str r2, [r3, #64] @ 0x40
hspi->RxXferSize = 0U;
80027ec: 68fb ldr r3, [r7, #12]
80027ee: 2200 movs r2, #0
80027f0: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
hspi->RxXferCount = 0U;
80027f4: 68fb ldr r3, [r7, #12]
80027f6: 2200 movs r2, #0
80027f8: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
hspi->TxISR = NULL;
80027fc: 68fb ldr r3, [r7, #12]
80027fe: 2200 movs r2, #0
8002800: 651a str r2, [r3, #80] @ 0x50
hspi->RxISR = NULL;
8002802: 68fb ldr r3, [r7, #12]
8002804: 2200 movs r2, #0
8002806: 64da str r2, [r3, #76] @ 0x4c
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
8002808: 68fb ldr r3, [r7, #12]
800280a: 689b ldr r3, [r3, #8]
800280c: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8002810: d10f bne.n 8002832 <HAL_SPI_Transmit+0xbc>
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
8002812: 68fb ldr r3, [r7, #12]
8002814: 681b ldr r3, [r3, #0]
8002816: 681a ldr r2, [r3, #0]
8002818: 68fb ldr r3, [r7, #12]
800281a: 681b ldr r3, [r3, #0]
800281c: f022 0240 bic.w r2, r2, #64 @ 0x40
8002820: 601a str r2, [r3, #0]
SPI_1LINE_TX(hspi);
8002822: 68fb ldr r3, [r7, #12]
8002824: 681b ldr r3, [r3, #0]
8002826: 681a ldr r2, [r3, #0]
8002828: 68fb ldr r3, [r7, #12]
800282a: 681b ldr r3, [r3, #0]
800282c: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8002830: 601a str r2, [r3, #0]
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
8002832: 68fb ldr r3, [r7, #12]
8002834: 681b ldr r3, [r3, #0]
8002836: 681b ldr r3, [r3, #0]
8002838: f003 0340 and.w r3, r3, #64 @ 0x40
800283c: 2b40 cmp r3, #64 @ 0x40
800283e: d007 beq.n 8002850 <HAL_SPI_Transmit+0xda>
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
8002840: 68fb ldr r3, [r7, #12]
8002842: 681b ldr r3, [r3, #0]
8002844: 681a ldr r2, [r3, #0]
8002846: 68fb ldr r3, [r7, #12]
8002848: 681b ldr r3, [r3, #0]
800284a: f042 0240 orr.w r2, r2, #64 @ 0x40
800284e: 601a str r2, [r3, #0]
}
/* Transmit data in 16 Bit mode */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
8002850: 68fb ldr r3, [r7, #12]
8002852: 68db ldr r3, [r3, #12]
8002854: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
8002858: d952 bls.n 8002900 <HAL_SPI_Transmit+0x18a>
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
800285a: 68fb ldr r3, [r7, #12]
800285c: 685b ldr r3, [r3, #4]
800285e: 2b00 cmp r3, #0
8002860: d002 beq.n 8002868 <HAL_SPI_Transmit+0xf2>
8002862: 8b7b ldrh r3, [r7, #26]
8002864: 2b01 cmp r3, #1
8002866: d145 bne.n 80028f4 <HAL_SPI_Transmit+0x17e>
{
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
8002868: 68fb ldr r3, [r7, #12]
800286a: 6b9b ldr r3, [r3, #56] @ 0x38
800286c: 881a ldrh r2, [r3, #0]
800286e: 68fb ldr r3, [r7, #12]
8002870: 681b ldr r3, [r3, #0]
8002872: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
8002874: 68fb ldr r3, [r7, #12]
8002876: 6b9b ldr r3, [r3, #56] @ 0x38
8002878: 1c9a adds r2, r3, #2
800287a: 68fb ldr r3, [r7, #12]
800287c: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount--;
800287e: 68fb ldr r3, [r7, #12]
8002880: 8fdb ldrh r3, [r3, #62] @ 0x3e
8002882: b29b uxth r3, r3
8002884: 3b01 subs r3, #1
8002886: b29a uxth r2, r3
8002888: 68fb ldr r3, [r7, #12]
800288a: 87da strh r2, [r3, #62] @ 0x3e
}
/* Transmit data in 16 Bit mode */
while (hspi->TxXferCount > 0U)
800288c: e032 b.n 80028f4 <HAL_SPI_Transmit+0x17e>
{
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
800288e: 68fb ldr r3, [r7, #12]
8002890: 681b ldr r3, [r3, #0]
8002892: 689b ldr r3, [r3, #8]
8002894: f003 0302 and.w r3, r3, #2
8002898: 2b02 cmp r3, #2
800289a: d112 bne.n 80028c2 <HAL_SPI_Transmit+0x14c>
{
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
800289c: 68fb ldr r3, [r7, #12]
800289e: 6b9b ldr r3, [r3, #56] @ 0x38
80028a0: 881a ldrh r2, [r3, #0]
80028a2: 68fb ldr r3, [r7, #12]
80028a4: 681b ldr r3, [r3, #0]
80028a6: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
80028a8: 68fb ldr r3, [r7, #12]
80028aa: 6b9b ldr r3, [r3, #56] @ 0x38
80028ac: 1c9a adds r2, r3, #2
80028ae: 68fb ldr r3, [r7, #12]
80028b0: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount--;
80028b2: 68fb ldr r3, [r7, #12]
80028b4: 8fdb ldrh r3, [r3, #62] @ 0x3e
80028b6: b29b uxth r3, r3
80028b8: 3b01 subs r3, #1
80028ba: b29a uxth r2, r3
80028bc: 68fb ldr r3, [r7, #12]
80028be: 87da strh r2, [r3, #62] @ 0x3e
80028c0: e018 b.n 80028f4 <HAL_SPI_Transmit+0x17e>
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
80028c2: f7fe fdff bl 80014c4 <HAL_GetTick>
80028c6: 4602 mov r2, r0
80028c8: 69fb ldr r3, [r7, #28]
80028ca: 1ad3 subs r3, r2, r3
80028cc: 683a ldr r2, [r7, #0]
80028ce: 429a cmp r2, r3
80028d0: d803 bhi.n 80028da <HAL_SPI_Transmit+0x164>
80028d2: 683b ldr r3, [r7, #0]
80028d4: f1b3 3fff cmp.w r3, #4294967295
80028d8: d102 bne.n 80028e0 <HAL_SPI_Transmit+0x16a>
80028da: 683b ldr r3, [r7, #0]
80028dc: 2b00 cmp r3, #0
80028de: d109 bne.n 80028f4 <HAL_SPI_Transmit+0x17e>
{
hspi->State = HAL_SPI_STATE_READY;
80028e0: 68fb ldr r3, [r7, #12]
80028e2: 2201 movs r2, #1
80028e4: f883 205d strb.w r2, [r3, #93] @ 0x5d
__HAL_UNLOCK(hspi);
80028e8: 68fb ldr r3, [r7, #12]
80028ea: 2200 movs r2, #0
80028ec: f883 205c strb.w r2, [r3, #92] @ 0x5c
return HAL_TIMEOUT;
80028f0: 2303 movs r3, #3
80028f2: e0b2 b.n 8002a5a <HAL_SPI_Transmit+0x2e4>
while (hspi->TxXferCount > 0U)
80028f4: 68fb ldr r3, [r7, #12]
80028f6: 8fdb ldrh r3, [r3, #62] @ 0x3e
80028f8: b29b uxth r3, r3
80028fa: 2b00 cmp r3, #0
80028fc: d1c7 bne.n 800288e <HAL_SPI_Transmit+0x118>
80028fe: e083 b.n 8002a08 <HAL_SPI_Transmit+0x292>
}
}
/* Transmit data in 8 Bit mode */
else
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
8002900: 68fb ldr r3, [r7, #12]
8002902: 685b ldr r3, [r3, #4]
8002904: 2b00 cmp r3, #0
8002906: d002 beq.n 800290e <HAL_SPI_Transmit+0x198>
8002908: 8b7b ldrh r3, [r7, #26]
800290a: 2b01 cmp r3, #1
800290c: d177 bne.n 80029fe <HAL_SPI_Transmit+0x288>
{
if (hspi->TxXferCount > 1U)
800290e: 68fb ldr r3, [r7, #12]
8002910: 8fdb ldrh r3, [r3, #62] @ 0x3e
8002912: b29b uxth r3, r3
8002914: 2b01 cmp r3, #1
8002916: d912 bls.n 800293e <HAL_SPI_Transmit+0x1c8>
{
/* write on the data register in packing mode */
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
8002918: 68fb ldr r3, [r7, #12]
800291a: 6b9b ldr r3, [r3, #56] @ 0x38
800291c: 881a ldrh r2, [r3, #0]
800291e: 68fb ldr r3, [r7, #12]
8002920: 681b ldr r3, [r3, #0]
8002922: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
8002924: 68fb ldr r3, [r7, #12]
8002926: 6b9b ldr r3, [r3, #56] @ 0x38
8002928: 1c9a adds r2, r3, #2
800292a: 68fb ldr r3, [r7, #12]
800292c: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount -= 2U;
800292e: 68fb ldr r3, [r7, #12]
8002930: 8fdb ldrh r3, [r3, #62] @ 0x3e
8002932: b29b uxth r3, r3
8002934: 3b02 subs r3, #2
8002936: b29a uxth r2, r3
8002938: 68fb ldr r3, [r7, #12]
800293a: 87da strh r2, [r3, #62] @ 0x3e
800293c: e05f b.n 80029fe <HAL_SPI_Transmit+0x288>
}
else
{
*((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
800293e: 68fb ldr r3, [r7, #12]
8002940: 6b9a ldr r2, [r3, #56] @ 0x38
8002942: 68fb ldr r3, [r7, #12]
8002944: 681b ldr r3, [r3, #0]
8002946: 330c adds r3, #12
8002948: 7812 ldrb r2, [r2, #0]
800294a: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr ++;
800294c: 68fb ldr r3, [r7, #12]
800294e: 6b9b ldr r3, [r3, #56] @ 0x38
8002950: 1c5a adds r2, r3, #1
8002952: 68fb ldr r3, [r7, #12]
8002954: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount--;
8002956: 68fb ldr r3, [r7, #12]
8002958: 8fdb ldrh r3, [r3, #62] @ 0x3e
800295a: b29b uxth r3, r3
800295c: 3b01 subs r3, #1
800295e: b29a uxth r2, r3
8002960: 68fb ldr r3, [r7, #12]
8002962: 87da strh r2, [r3, #62] @ 0x3e
}
}
while (hspi->TxXferCount > 0U)
8002964: e04b b.n 80029fe <HAL_SPI_Transmit+0x288>
{
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
8002966: 68fb ldr r3, [r7, #12]
8002968: 681b ldr r3, [r3, #0]
800296a: 689b ldr r3, [r3, #8]
800296c: f003 0302 and.w r3, r3, #2
8002970: 2b02 cmp r3, #2
8002972: d12b bne.n 80029cc <HAL_SPI_Transmit+0x256>
{
if (hspi->TxXferCount > 1U)
8002974: 68fb ldr r3, [r7, #12]
8002976: 8fdb ldrh r3, [r3, #62] @ 0x3e
8002978: b29b uxth r3, r3
800297a: 2b01 cmp r3, #1
800297c: d912 bls.n 80029a4 <HAL_SPI_Transmit+0x22e>
{
/* write on the data register in packing mode */
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
800297e: 68fb ldr r3, [r7, #12]
8002980: 6b9b ldr r3, [r3, #56] @ 0x38
8002982: 881a ldrh r2, [r3, #0]
8002984: 68fb ldr r3, [r7, #12]
8002986: 681b ldr r3, [r3, #0]
8002988: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
800298a: 68fb ldr r3, [r7, #12]
800298c: 6b9b ldr r3, [r3, #56] @ 0x38
800298e: 1c9a adds r2, r3, #2
8002990: 68fb ldr r3, [r7, #12]
8002992: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount -= 2U;
8002994: 68fb ldr r3, [r7, #12]
8002996: 8fdb ldrh r3, [r3, #62] @ 0x3e
8002998: b29b uxth r3, r3
800299a: 3b02 subs r3, #2
800299c: b29a uxth r2, r3
800299e: 68fb ldr r3, [r7, #12]
80029a0: 87da strh r2, [r3, #62] @ 0x3e
80029a2: e02c b.n 80029fe <HAL_SPI_Transmit+0x288>
}
else
{
*((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
80029a4: 68fb ldr r3, [r7, #12]
80029a6: 6b9a ldr r2, [r3, #56] @ 0x38
80029a8: 68fb ldr r3, [r7, #12]
80029aa: 681b ldr r3, [r3, #0]
80029ac: 330c adds r3, #12
80029ae: 7812 ldrb r2, [r2, #0]
80029b0: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr++;
80029b2: 68fb ldr r3, [r7, #12]
80029b4: 6b9b ldr r3, [r3, #56] @ 0x38
80029b6: 1c5a adds r2, r3, #1
80029b8: 68fb ldr r3, [r7, #12]
80029ba: 639a str r2, [r3, #56] @ 0x38
hspi->TxXferCount--;
80029bc: 68fb ldr r3, [r7, #12]
80029be: 8fdb ldrh r3, [r3, #62] @ 0x3e
80029c0: b29b uxth r3, r3
80029c2: 3b01 subs r3, #1
80029c4: b29a uxth r2, r3
80029c6: 68fb ldr r3, [r7, #12]
80029c8: 87da strh r2, [r3, #62] @ 0x3e
80029ca: e018 b.n 80029fe <HAL_SPI_Transmit+0x288>
}
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
80029cc: f7fe fd7a bl 80014c4 <HAL_GetTick>
80029d0: 4602 mov r2, r0
80029d2: 69fb ldr r3, [r7, #28]
80029d4: 1ad3 subs r3, r2, r3
80029d6: 683a ldr r2, [r7, #0]
80029d8: 429a cmp r2, r3
80029da: d803 bhi.n 80029e4 <HAL_SPI_Transmit+0x26e>
80029dc: 683b ldr r3, [r7, #0]
80029de: f1b3 3fff cmp.w r3, #4294967295
80029e2: d102 bne.n 80029ea <HAL_SPI_Transmit+0x274>
80029e4: 683b ldr r3, [r7, #0]
80029e6: 2b00 cmp r3, #0
80029e8: d109 bne.n 80029fe <HAL_SPI_Transmit+0x288>
{
hspi->State = HAL_SPI_STATE_READY;
80029ea: 68fb ldr r3, [r7, #12]
80029ec: 2201 movs r2, #1
80029ee: f883 205d strb.w r2, [r3, #93] @ 0x5d
__HAL_UNLOCK(hspi);
80029f2: 68fb ldr r3, [r7, #12]
80029f4: 2200 movs r2, #0
80029f6: f883 205c strb.w r2, [r3, #92] @ 0x5c
return HAL_TIMEOUT;
80029fa: 2303 movs r3, #3
80029fc: e02d b.n 8002a5a <HAL_SPI_Transmit+0x2e4>
while (hspi->TxXferCount > 0U)
80029fe: 68fb ldr r3, [r7, #12]
8002a00: 8fdb ldrh r3, [r3, #62] @ 0x3e
8002a02: b29b uxth r3, r3
8002a04: 2b00 cmp r3, #0
8002a06: d1ae bne.n 8002966 <HAL_SPI_Transmit+0x1f0>
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
8002a08: 69fa ldr r2, [r7, #28]
8002a0a: 6839 ldr r1, [r7, #0]
8002a0c: 68f8 ldr r0, [r7, #12]
8002a0e: f000 f947 bl 8002ca0 <SPI_EndRxTxTransaction>
8002a12: 4603 mov r3, r0
8002a14: 2b00 cmp r3, #0
8002a16: d002 beq.n 8002a1e <HAL_SPI_Transmit+0x2a8>
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
8002a18: 68fb ldr r3, [r7, #12]
8002a1a: 2220 movs r2, #32
8002a1c: 661a str r2, [r3, #96] @ 0x60
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
8002a1e: 68fb ldr r3, [r7, #12]
8002a20: 689b ldr r3, [r3, #8]
8002a22: 2b00 cmp r3, #0
8002a24: d10a bne.n 8002a3c <HAL_SPI_Transmit+0x2c6>
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
8002a26: 2300 movs r3, #0
8002a28: 617b str r3, [r7, #20]
8002a2a: 68fb ldr r3, [r7, #12]
8002a2c: 681b ldr r3, [r3, #0]
8002a2e: 68db ldr r3, [r3, #12]
8002a30: 617b str r3, [r7, #20]
8002a32: 68fb ldr r3, [r7, #12]
8002a34: 681b ldr r3, [r3, #0]
8002a36: 689b ldr r3, [r3, #8]
8002a38: 617b str r3, [r7, #20]
8002a3a: 697b ldr r3, [r7, #20]
}
hspi->State = HAL_SPI_STATE_READY;
8002a3c: 68fb ldr r3, [r7, #12]
8002a3e: 2201 movs r2, #1
8002a40: f883 205d strb.w r2, [r3, #93] @ 0x5d
/* Process Unlocked */
__HAL_UNLOCK(hspi);
8002a44: 68fb ldr r3, [r7, #12]
8002a46: 2200 movs r2, #0
8002a48: f883 205c strb.w r2, [r3, #92] @ 0x5c
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
8002a4c: 68fb ldr r3, [r7, #12]
8002a4e: 6e1b ldr r3, [r3, #96] @ 0x60
8002a50: 2b00 cmp r3, #0
8002a52: d001 beq.n 8002a58 <HAL_SPI_Transmit+0x2e2>
{
return HAL_ERROR;
8002a54: 2301 movs r3, #1
8002a56: e000 b.n 8002a5a <HAL_SPI_Transmit+0x2e4>
}
else
{
return HAL_OK;
8002a58: 2300 movs r3, #0
}
}
8002a5a: 4618 mov r0, r3
8002a5c: 3720 adds r7, #32
8002a5e: 46bd mov sp, r7
8002a60: bd80 pop {r7, pc}
...
08002a64 <SPI_WaitFlagStateUntilTimeout>:
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart)
{
8002a64: b580 push {r7, lr}
8002a66: b088 sub sp, #32
8002a68: af00 add r7, sp, #0
8002a6a: 60f8 str r0, [r7, #12]
8002a6c: 60b9 str r1, [r7, #8]
8002a6e: 603b str r3, [r7, #0]
8002a70: 4613 mov r3, r2
8002a72: 71fb strb r3, [r7, #7]
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
/* Adjust Timeout value in case of end of transfer */
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
8002a74: f7fe fd26 bl 80014c4 <HAL_GetTick>
8002a78: 4602 mov r2, r0
8002a7a: 6abb ldr r3, [r7, #40] @ 0x28
8002a7c: 1a9b subs r3, r3, r2
8002a7e: 683a ldr r2, [r7, #0]
8002a80: 4413 add r3, r2
8002a82: 61fb str r3, [r7, #28]
tmp_tickstart = HAL_GetTick();
8002a84: f7fe fd1e bl 80014c4 <HAL_GetTick>
8002a88: 61b8 str r0, [r7, #24]
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
8002a8a: 4b39 ldr r3, [pc, #228] @ (8002b70 <SPI_WaitFlagStateUntilTimeout+0x10c>)
8002a8c: 681b ldr r3, [r3, #0]
8002a8e: 015b lsls r3, r3, #5
8002a90: 0d1b lsrs r3, r3, #20
8002a92: 69fa ldr r2, [r7, #28]
8002a94: fb02 f303 mul.w r3, r2, r3
8002a98: 617b str r3, [r7, #20]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
8002a9a: e054 b.n 8002b46 <SPI_WaitFlagStateUntilTimeout+0xe2>
{
if (Timeout != HAL_MAX_DELAY)
8002a9c: 683b ldr r3, [r7, #0]
8002a9e: f1b3 3fff cmp.w r3, #4294967295
8002aa2: d050 beq.n 8002b46 <SPI_WaitFlagStateUntilTimeout+0xe2>
{
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
8002aa4: f7fe fd0e bl 80014c4 <HAL_GetTick>
8002aa8: 4602 mov r2, r0
8002aaa: 69bb ldr r3, [r7, #24]
8002aac: 1ad3 subs r3, r2, r3
8002aae: 69fa ldr r2, [r7, #28]
8002ab0: 429a cmp r2, r3
8002ab2: d902 bls.n 8002aba <SPI_WaitFlagStateUntilTimeout+0x56>
8002ab4: 69fb ldr r3, [r7, #28]
8002ab6: 2b00 cmp r3, #0
8002ab8: d13d bne.n 8002b36 <SPI_WaitFlagStateUntilTimeout+0xd2>
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
8002aba: 68fb ldr r3, [r7, #12]
8002abc: 681b ldr r3, [r3, #0]
8002abe: 685a ldr r2, [r3, #4]
8002ac0: 68fb ldr r3, [r7, #12]
8002ac2: 681b ldr r3, [r3, #0]
8002ac4: f022 02e0 bic.w r2, r2, #224 @ 0xe0
8002ac8: 605a str r2, [r3, #4]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
8002aca: 68fb ldr r3, [r7, #12]
8002acc: 685b ldr r3, [r3, #4]
8002ace: f5b3 7f82 cmp.w r3, #260 @ 0x104
8002ad2: d111 bne.n 8002af8 <SPI_WaitFlagStateUntilTimeout+0x94>
8002ad4: 68fb ldr r3, [r7, #12]
8002ad6: 689b ldr r3, [r3, #8]
8002ad8: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8002adc: d004 beq.n 8002ae8 <SPI_WaitFlagStateUntilTimeout+0x84>
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
8002ade: 68fb ldr r3, [r7, #12]
8002ae0: 689b ldr r3, [r3, #8]
8002ae2: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8002ae6: d107 bne.n 8002af8 <SPI_WaitFlagStateUntilTimeout+0x94>
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8002ae8: 68fb ldr r3, [r7, #12]
8002aea: 681b ldr r3, [r3, #0]
8002aec: 681a ldr r2, [r3, #0]
8002aee: 68fb ldr r3, [r7, #12]
8002af0: 681b ldr r3, [r3, #0]
8002af2: f022 0240 bic.w r2, r2, #64 @ 0x40
8002af6: 601a str r2, [r3, #0]
}
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
8002af8: 68fb ldr r3, [r7, #12]
8002afa: 6a9b ldr r3, [r3, #40] @ 0x28
8002afc: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8002b00: d10f bne.n 8002b22 <SPI_WaitFlagStateUntilTimeout+0xbe>
{
SPI_RESET_CRC(hspi);
8002b02: 68fb ldr r3, [r7, #12]
8002b04: 681b ldr r3, [r3, #0]
8002b06: 681a ldr r2, [r3, #0]
8002b08: 68fb ldr r3, [r7, #12]
8002b0a: 681b ldr r3, [r3, #0]
8002b0c: f422 5200 bic.w r2, r2, #8192 @ 0x2000
8002b10: 601a str r2, [r3, #0]
8002b12: 68fb ldr r3, [r7, #12]
8002b14: 681b ldr r3, [r3, #0]
8002b16: 681a ldr r2, [r3, #0]
8002b18: 68fb ldr r3, [r7, #12]
8002b1a: 681b ldr r3, [r3, #0]
8002b1c: f442 5200 orr.w r2, r2, #8192 @ 0x2000
8002b20: 601a str r2, [r3, #0]
}
hspi->State = HAL_SPI_STATE_READY;
8002b22: 68fb ldr r3, [r7, #12]
8002b24: 2201 movs r2, #1
8002b26: f883 205d strb.w r2, [r3, #93] @ 0x5d
/* Process Unlocked */
__HAL_UNLOCK(hspi);
8002b2a: 68fb ldr r3, [r7, #12]
8002b2c: 2200 movs r2, #0
8002b2e: f883 205c strb.w r2, [r3, #92] @ 0x5c
return HAL_TIMEOUT;
8002b32: 2303 movs r3, #3
8002b34: e017 b.n 8002b66 <SPI_WaitFlagStateUntilTimeout+0x102>
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
if (count == 0U)
8002b36: 697b ldr r3, [r7, #20]
8002b38: 2b00 cmp r3, #0
8002b3a: d101 bne.n 8002b40 <SPI_WaitFlagStateUntilTimeout+0xdc>
{
tmp_timeout = 0U;
8002b3c: 2300 movs r3, #0
8002b3e: 61fb str r3, [r7, #28]
}
count--;
8002b40: 697b ldr r3, [r7, #20]
8002b42: 3b01 subs r3, #1
8002b44: 617b str r3, [r7, #20]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
8002b46: 68fb ldr r3, [r7, #12]
8002b48: 681b ldr r3, [r3, #0]
8002b4a: 689a ldr r2, [r3, #8]
8002b4c: 68bb ldr r3, [r7, #8]
8002b4e: 4013 ands r3, r2
8002b50: 68ba ldr r2, [r7, #8]
8002b52: 429a cmp r2, r3
8002b54: bf0c ite eq
8002b56: 2301 moveq r3, #1
8002b58: 2300 movne r3, #0
8002b5a: b2db uxtb r3, r3
8002b5c: 461a mov r2, r3
8002b5e: 79fb ldrb r3, [r7, #7]
8002b60: 429a cmp r2, r3
8002b62: d19b bne.n 8002a9c <SPI_WaitFlagStateUntilTimeout+0x38>
}
}
return HAL_OK;
8002b64: 2300 movs r3, #0
}
8002b66: 4618 mov r0, r3
8002b68: 3720 adds r7, #32
8002b6a: 46bd mov sp, r7
8002b6c: bd80 pop {r7, pc}
8002b6e: bf00 nop
8002b70: 20000000 .word 0x20000000
08002b74 <SPI_WaitFifoStateUntilTimeout>:
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
uint32_t Timeout, uint32_t Tickstart)
{
8002b74: b580 push {r7, lr}
8002b76: b08a sub sp, #40 @ 0x28
8002b78: af00 add r7, sp, #0
8002b7a: 60f8 str r0, [r7, #12]
8002b7c: 60b9 str r1, [r7, #8]
8002b7e: 607a str r2, [r7, #4]
8002b80: 603b str r3, [r7, #0]
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
__IO const uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
8002b82: 2300 movs r3, #0
8002b84: 75fb strb r3, [r7, #23]
/* Adjust Timeout value in case of end of transfer */
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
8002b86: f7fe fc9d bl 80014c4 <HAL_GetTick>
8002b8a: 4602 mov r2, r0
8002b8c: 6b3b ldr r3, [r7, #48] @ 0x30
8002b8e: 1a9b subs r3, r3, r2
8002b90: 683a ldr r2, [r7, #0]
8002b92: 4413 add r3, r2
8002b94: 627b str r3, [r7, #36] @ 0x24
tmp_tickstart = HAL_GetTick();
8002b96: f7fe fc95 bl 80014c4 <HAL_GetTick>
8002b9a: 6238 str r0, [r7, #32]
/* Initialize the 8bit temporary pointer */
ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
8002b9c: 68fb ldr r3, [r7, #12]
8002b9e: 681b ldr r3, [r3, #0]
8002ba0: 330c adds r3, #12
8002ba2: 61fb str r3, [r7, #28]
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
8002ba4: 4b3d ldr r3, [pc, #244] @ (8002c9c <SPI_WaitFifoStateUntilTimeout+0x128>)
8002ba6: 681a ldr r2, [r3, #0]
8002ba8: 4613 mov r3, r2
8002baa: 009b lsls r3, r3, #2
8002bac: 4413 add r3, r2
8002bae: 00da lsls r2, r3, #3
8002bb0: 1ad3 subs r3, r2, r3
8002bb2: 0d1b lsrs r3, r3, #20
8002bb4: 6a7a ldr r2, [r7, #36] @ 0x24
8002bb6: fb02 f303 mul.w r3, r2, r3
8002bba: 61bb str r3, [r7, #24]
while ((hspi->Instance->SR & Fifo) != State)
8002bbc: e060 b.n 8002c80 <SPI_WaitFifoStateUntilTimeout+0x10c>
{
if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
8002bbe: 68bb ldr r3, [r7, #8]
8002bc0: f5b3 6fc0 cmp.w r3, #1536 @ 0x600
8002bc4: d107 bne.n 8002bd6 <SPI_WaitFifoStateUntilTimeout+0x62>
8002bc6: 687b ldr r3, [r7, #4]
8002bc8: 2b00 cmp r3, #0
8002bca: d104 bne.n 8002bd6 <SPI_WaitFifoStateUntilTimeout+0x62>
{
/* Flush Data Register by a blank read */
tmpreg8 = *ptmpreg8;
8002bcc: 69fb ldr r3, [r7, #28]
8002bce: 781b ldrb r3, [r3, #0]
8002bd0: b2db uxtb r3, r3
8002bd2: 75fb strb r3, [r7, #23]
/* To avoid GCC warning */
UNUSED(tmpreg8);
8002bd4: 7dfb ldrb r3, [r7, #23]
}
if (Timeout != HAL_MAX_DELAY)
8002bd6: 683b ldr r3, [r7, #0]
8002bd8: f1b3 3fff cmp.w r3, #4294967295
8002bdc: d050 beq.n 8002c80 <SPI_WaitFifoStateUntilTimeout+0x10c>
{
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
8002bde: f7fe fc71 bl 80014c4 <HAL_GetTick>
8002be2: 4602 mov r2, r0
8002be4: 6a3b ldr r3, [r7, #32]
8002be6: 1ad3 subs r3, r2, r3
8002be8: 6a7a ldr r2, [r7, #36] @ 0x24
8002bea: 429a cmp r2, r3
8002bec: d902 bls.n 8002bf4 <SPI_WaitFifoStateUntilTimeout+0x80>
8002bee: 6a7b ldr r3, [r7, #36] @ 0x24
8002bf0: 2b00 cmp r3, #0
8002bf2: d13d bne.n 8002c70 <SPI_WaitFifoStateUntilTimeout+0xfc>
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
8002bf4: 68fb ldr r3, [r7, #12]
8002bf6: 681b ldr r3, [r3, #0]
8002bf8: 685a ldr r2, [r3, #4]
8002bfa: 68fb ldr r3, [r7, #12]
8002bfc: 681b ldr r3, [r3, #0]
8002bfe: f022 02e0 bic.w r2, r2, #224 @ 0xe0
8002c02: 605a str r2, [r3, #4]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
8002c04: 68fb ldr r3, [r7, #12]
8002c06: 685b ldr r3, [r3, #4]
8002c08: f5b3 7f82 cmp.w r3, #260 @ 0x104
8002c0c: d111 bne.n 8002c32 <SPI_WaitFifoStateUntilTimeout+0xbe>
8002c0e: 68fb ldr r3, [r7, #12]
8002c10: 689b ldr r3, [r3, #8]
8002c12: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8002c16: d004 beq.n 8002c22 <SPI_WaitFifoStateUntilTimeout+0xae>
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
8002c18: 68fb ldr r3, [r7, #12]
8002c1a: 689b ldr r3, [r3, #8]
8002c1c: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8002c20: d107 bne.n 8002c32 <SPI_WaitFifoStateUntilTimeout+0xbe>
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8002c22: 68fb ldr r3, [r7, #12]
8002c24: 681b ldr r3, [r3, #0]
8002c26: 681a ldr r2, [r3, #0]
8002c28: 68fb ldr r3, [r7, #12]
8002c2a: 681b ldr r3, [r3, #0]
8002c2c: f022 0240 bic.w r2, r2, #64 @ 0x40
8002c30: 601a str r2, [r3, #0]
}
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
8002c32: 68fb ldr r3, [r7, #12]
8002c34: 6a9b ldr r3, [r3, #40] @ 0x28
8002c36: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8002c3a: d10f bne.n 8002c5c <SPI_WaitFifoStateUntilTimeout+0xe8>
{
SPI_RESET_CRC(hspi);
8002c3c: 68fb ldr r3, [r7, #12]
8002c3e: 681b ldr r3, [r3, #0]
8002c40: 681a ldr r2, [r3, #0]
8002c42: 68fb ldr r3, [r7, #12]
8002c44: 681b ldr r3, [r3, #0]
8002c46: f422 5200 bic.w r2, r2, #8192 @ 0x2000
8002c4a: 601a str r2, [r3, #0]
8002c4c: 68fb ldr r3, [r7, #12]
8002c4e: 681b ldr r3, [r3, #0]
8002c50: 681a ldr r2, [r3, #0]
8002c52: 68fb ldr r3, [r7, #12]
8002c54: 681b ldr r3, [r3, #0]
8002c56: f442 5200 orr.w r2, r2, #8192 @ 0x2000
8002c5a: 601a str r2, [r3, #0]
}
hspi->State = HAL_SPI_STATE_READY;
8002c5c: 68fb ldr r3, [r7, #12]
8002c5e: 2201 movs r2, #1
8002c60: f883 205d strb.w r2, [r3, #93] @ 0x5d
/* Process Unlocked */
__HAL_UNLOCK(hspi);
8002c64: 68fb ldr r3, [r7, #12]
8002c66: 2200 movs r2, #0
8002c68: f883 205c strb.w r2, [r3, #92] @ 0x5c
return HAL_TIMEOUT;
8002c6c: 2303 movs r3, #3
8002c6e: e010 b.n 8002c92 <SPI_WaitFifoStateUntilTimeout+0x11e>
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
if (count == 0U)
8002c70: 69bb ldr r3, [r7, #24]
8002c72: 2b00 cmp r3, #0
8002c74: d101 bne.n 8002c7a <SPI_WaitFifoStateUntilTimeout+0x106>
{
tmp_timeout = 0U;
8002c76: 2300 movs r3, #0
8002c78: 627b str r3, [r7, #36] @ 0x24
}
count--;
8002c7a: 69bb ldr r3, [r7, #24]
8002c7c: 3b01 subs r3, #1
8002c7e: 61bb str r3, [r7, #24]
while ((hspi->Instance->SR & Fifo) != State)
8002c80: 68fb ldr r3, [r7, #12]
8002c82: 681b ldr r3, [r3, #0]
8002c84: 689a ldr r2, [r3, #8]
8002c86: 68bb ldr r3, [r7, #8]
8002c88: 4013 ands r3, r2
8002c8a: 687a ldr r2, [r7, #4]
8002c8c: 429a cmp r2, r3
8002c8e: d196 bne.n 8002bbe <SPI_WaitFifoStateUntilTimeout+0x4a>
}
}
return HAL_OK;
8002c90: 2300 movs r3, #0
}
8002c92: 4618 mov r0, r3
8002c94: 3728 adds r7, #40 @ 0x28
8002c96: 46bd mov sp, r7
8002c98: bd80 pop {r7, pc}
8002c9a: bf00 nop
8002c9c: 20000000 .word 0x20000000
08002ca0 <SPI_EndRxTxTransaction>:
* @param Timeout Timeout duration
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
8002ca0: b580 push {r7, lr}
8002ca2: b086 sub sp, #24
8002ca4: af02 add r7, sp, #8
8002ca6: 60f8 str r0, [r7, #12]
8002ca8: 60b9 str r1, [r7, #8]
8002caa: 607a str r2, [r7, #4]
/* Control if the TX fifo is empty */
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
8002cac: 687b ldr r3, [r7, #4]
8002cae: 9300 str r3, [sp, #0]
8002cb0: 68bb ldr r3, [r7, #8]
8002cb2: 2200 movs r2, #0
8002cb4: f44f 51c0 mov.w r1, #6144 @ 0x1800
8002cb8: 68f8 ldr r0, [r7, #12]
8002cba: f7ff ff5b bl 8002b74 <SPI_WaitFifoStateUntilTimeout>
8002cbe: 4603 mov r3, r0
8002cc0: 2b00 cmp r3, #0
8002cc2: d007 beq.n 8002cd4 <SPI_EndRxTxTransaction+0x34>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
8002cc4: 68fb ldr r3, [r7, #12]
8002cc6: 6e1b ldr r3, [r3, #96] @ 0x60
8002cc8: f043 0220 orr.w r2, r3, #32
8002ccc: 68fb ldr r3, [r7, #12]
8002cce: 661a str r2, [r3, #96] @ 0x60
return HAL_TIMEOUT;
8002cd0: 2303 movs r3, #3
8002cd2: e027 b.n 8002d24 <SPI_EndRxTxTransaction+0x84>
}
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
8002cd4: 687b ldr r3, [r7, #4]
8002cd6: 9300 str r3, [sp, #0]
8002cd8: 68bb ldr r3, [r7, #8]
8002cda: 2200 movs r2, #0
8002cdc: 2180 movs r1, #128 @ 0x80
8002cde: 68f8 ldr r0, [r7, #12]
8002ce0: f7ff fec0 bl 8002a64 <SPI_WaitFlagStateUntilTimeout>
8002ce4: 4603 mov r3, r0
8002ce6: 2b00 cmp r3, #0
8002ce8: d007 beq.n 8002cfa <SPI_EndRxTxTransaction+0x5a>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
8002cea: 68fb ldr r3, [r7, #12]
8002cec: 6e1b ldr r3, [r3, #96] @ 0x60
8002cee: f043 0220 orr.w r2, r3, #32
8002cf2: 68fb ldr r3, [r7, #12]
8002cf4: 661a str r2, [r3, #96] @ 0x60
return HAL_TIMEOUT;
8002cf6: 2303 movs r3, #3
8002cf8: e014 b.n 8002d24 <SPI_EndRxTxTransaction+0x84>
}
/* Control if the RX fifo is empty */
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
8002cfa: 687b ldr r3, [r7, #4]
8002cfc: 9300 str r3, [sp, #0]
8002cfe: 68bb ldr r3, [r7, #8]
8002d00: 2200 movs r2, #0
8002d02: f44f 61c0 mov.w r1, #1536 @ 0x600
8002d06: 68f8 ldr r0, [r7, #12]
8002d08: f7ff ff34 bl 8002b74 <SPI_WaitFifoStateUntilTimeout>
8002d0c: 4603 mov r3, r0
8002d0e: 2b00 cmp r3, #0
8002d10: d007 beq.n 8002d22 <SPI_EndRxTxTransaction+0x82>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
8002d12: 68fb ldr r3, [r7, #12]
8002d14: 6e1b ldr r3, [r3, #96] @ 0x60
8002d16: f043 0220 orr.w r2, r3, #32
8002d1a: 68fb ldr r3, [r7, #12]
8002d1c: 661a str r2, [r3, #96] @ 0x60
return HAL_TIMEOUT;
8002d1e: 2303 movs r3, #3
8002d20: e000 b.n 8002d24 <SPI_EndRxTxTransaction+0x84>
}
return HAL_OK;
8002d22: 2300 movs r3, #0
}
8002d24: 4618 mov r0, r3
8002d26: 3710 adds r7, #16
8002d28: 46bd mov sp, r7
8002d2a: bd80 pop {r7, pc}
08002d2c <__cvt>:
8002d2c: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
8002d30: ec57 6b10 vmov r6, r7, d0
8002d34: 2f00 cmp r7, #0
8002d36: 460c mov r4, r1
8002d38: 4619 mov r1, r3
8002d3a: 463b mov r3, r7
8002d3c: bfbb ittet lt
8002d3e: f107 4300 addlt.w r3, r7, #2147483648 @ 0x80000000
8002d42: 461f movlt r7, r3
8002d44: 2300 movge r3, #0
8002d46: 232d movlt r3, #45 @ 0x2d
8002d48: 700b strb r3, [r1, #0]
8002d4a: 9b0d ldr r3, [sp, #52] @ 0x34
8002d4c: f8dd a030 ldr.w sl, [sp, #48] @ 0x30
8002d50: 4691 mov r9, r2
8002d52: f023 0820 bic.w r8, r3, #32
8002d56: bfbc itt lt
8002d58: 4632 movlt r2, r6
8002d5a: 4616 movlt r6, r2
8002d5c: f1b8 0f46 cmp.w r8, #70 @ 0x46
8002d60: d005 beq.n 8002d6e <__cvt+0x42>
8002d62: f1b8 0f45 cmp.w r8, #69 @ 0x45
8002d66: d100 bne.n 8002d6a <__cvt+0x3e>
8002d68: 3401 adds r4, #1
8002d6a: 2102 movs r1, #2
8002d6c: e000 b.n 8002d70 <__cvt+0x44>
8002d6e: 2103 movs r1, #3
8002d70: ab03 add r3, sp, #12
8002d72: 9301 str r3, [sp, #4]
8002d74: ab02 add r3, sp, #8
8002d76: 9300 str r3, [sp, #0]
8002d78: ec47 6b10 vmov d0, r6, r7
8002d7c: 4653 mov r3, sl
8002d7e: 4622 mov r2, r4
8002d80: f000 fe3a bl 80039f8 <_dtoa_r>
8002d84: f1b8 0f47 cmp.w r8, #71 @ 0x47
8002d88: 4605 mov r5, r0
8002d8a: d119 bne.n 8002dc0 <__cvt+0x94>
8002d8c: f019 0f01 tst.w r9, #1
8002d90: d00e beq.n 8002db0 <__cvt+0x84>
8002d92: eb00 0904 add.w r9, r0, r4
8002d96: 2200 movs r2, #0
8002d98: 2300 movs r3, #0
8002d9a: 4630 mov r0, r6
8002d9c: 4639 mov r1, r7
8002d9e: f7fd fe9b bl 8000ad8 <__aeabi_dcmpeq>
8002da2: b108 cbz r0, 8002da8 <__cvt+0x7c>
8002da4: f8cd 900c str.w r9, [sp, #12]
8002da8: 2230 movs r2, #48 @ 0x30
8002daa: 9b03 ldr r3, [sp, #12]
8002dac: 454b cmp r3, r9
8002dae: d31e bcc.n 8002dee <__cvt+0xc2>
8002db0: 9b03 ldr r3, [sp, #12]
8002db2: 9a0e ldr r2, [sp, #56] @ 0x38
8002db4: 1b5b subs r3, r3, r5
8002db6: 4628 mov r0, r5
8002db8: 6013 str r3, [r2, #0]
8002dba: b004 add sp, #16
8002dbc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8002dc0: f1b8 0f46 cmp.w r8, #70 @ 0x46
8002dc4: eb00 0904 add.w r9, r0, r4
8002dc8: d1e5 bne.n 8002d96 <__cvt+0x6a>
8002dca: 7803 ldrb r3, [r0, #0]
8002dcc: 2b30 cmp r3, #48 @ 0x30
8002dce: d10a bne.n 8002de6 <__cvt+0xba>
8002dd0: 2200 movs r2, #0
8002dd2: 2300 movs r3, #0
8002dd4: 4630 mov r0, r6
8002dd6: 4639 mov r1, r7
8002dd8: f7fd fe7e bl 8000ad8 <__aeabi_dcmpeq>
8002ddc: b918 cbnz r0, 8002de6 <__cvt+0xba>
8002dde: f1c4 0401 rsb r4, r4, #1
8002de2: f8ca 4000 str.w r4, [sl]
8002de6: f8da 3000 ldr.w r3, [sl]
8002dea: 4499 add r9, r3
8002dec: e7d3 b.n 8002d96 <__cvt+0x6a>
8002dee: 1c59 adds r1, r3, #1
8002df0: 9103 str r1, [sp, #12]
8002df2: 701a strb r2, [r3, #0]
8002df4: e7d9 b.n 8002daa <__cvt+0x7e>
08002df6 <__exponent>:
8002df6: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
8002df8: 2900 cmp r1, #0
8002dfa: bfba itte lt
8002dfc: 4249 neglt r1, r1
8002dfe: 232d movlt r3, #45 @ 0x2d
8002e00: 232b movge r3, #43 @ 0x2b
8002e02: 2909 cmp r1, #9
8002e04: 7002 strb r2, [r0, #0]
8002e06: 7043 strb r3, [r0, #1]
8002e08: dd29 ble.n 8002e5e <__exponent+0x68>
8002e0a: f10d 0307 add.w r3, sp, #7
8002e0e: 461d mov r5, r3
8002e10: 270a movs r7, #10
8002e12: 461a mov r2, r3
8002e14: fbb1 f6f7 udiv r6, r1, r7
8002e18: fb07 1416 mls r4, r7, r6, r1
8002e1c: 3430 adds r4, #48 @ 0x30
8002e1e: f802 4c01 strb.w r4, [r2, #-1]
8002e22: 460c mov r4, r1
8002e24: 2c63 cmp r4, #99 @ 0x63
8002e26: f103 33ff add.w r3, r3, #4294967295
8002e2a: 4631 mov r1, r6
8002e2c: dcf1 bgt.n 8002e12 <__exponent+0x1c>
8002e2e: 3130 adds r1, #48 @ 0x30
8002e30: 1e94 subs r4, r2, #2
8002e32: f803 1c01 strb.w r1, [r3, #-1]
8002e36: 1c41 adds r1, r0, #1
8002e38: 4623 mov r3, r4
8002e3a: 42ab cmp r3, r5
8002e3c: d30a bcc.n 8002e54 <__exponent+0x5e>
8002e3e: f10d 0309 add.w r3, sp, #9
8002e42: 1a9b subs r3, r3, r2
8002e44: 42ac cmp r4, r5
8002e46: bf88 it hi
8002e48: 2300 movhi r3, #0
8002e4a: 3302 adds r3, #2
8002e4c: 4403 add r3, r0
8002e4e: 1a18 subs r0, r3, r0
8002e50: b003 add sp, #12
8002e52: bdf0 pop {r4, r5, r6, r7, pc}
8002e54: f813 6b01 ldrb.w r6, [r3], #1
8002e58: f801 6f01 strb.w r6, [r1, #1]!
8002e5c: e7ed b.n 8002e3a <__exponent+0x44>
8002e5e: 2330 movs r3, #48 @ 0x30
8002e60: 3130 adds r1, #48 @ 0x30
8002e62: 7083 strb r3, [r0, #2]
8002e64: 70c1 strb r1, [r0, #3]
8002e66: 1d03 adds r3, r0, #4
8002e68: e7f1 b.n 8002e4e <__exponent+0x58>
...
08002e6c <_printf_float>:
8002e6c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8002e70: b08d sub sp, #52 @ 0x34
8002e72: 460c mov r4, r1
8002e74: f8dd 8058 ldr.w r8, [sp, #88] @ 0x58
8002e78: 4616 mov r6, r2
8002e7a: 461f mov r7, r3
8002e7c: 4605 mov r5, r0
8002e7e: f000 fcb9 bl 80037f4 <_localeconv_r>
8002e82: 6803 ldr r3, [r0, #0]
8002e84: 9304 str r3, [sp, #16]
8002e86: 4618 mov r0, r3
8002e88: f7fd f9fa bl 8000280 <strlen>
8002e8c: 2300 movs r3, #0
8002e8e: 930a str r3, [sp, #40] @ 0x28
8002e90: f8d8 3000 ldr.w r3, [r8]
8002e94: 9005 str r0, [sp, #20]
8002e96: 3307 adds r3, #7
8002e98: f023 0307 bic.w r3, r3, #7
8002e9c: f103 0208 add.w r2, r3, #8
8002ea0: f894 a018 ldrb.w sl, [r4, #24]
8002ea4: f8d4 b000 ldr.w fp, [r4]
8002ea8: f8c8 2000 str.w r2, [r8]
8002eac: e9d3 8900 ldrd r8, r9, [r3]
8002eb0: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000
8002eb4: 9307 str r3, [sp, #28]
8002eb6: f8cd 8018 str.w r8, [sp, #24]
8002eba: e9c4 8912 strd r8, r9, [r4, #72] @ 0x48
8002ebe: e9dd 0106 ldrd r0, r1, [sp, #24]
8002ec2: 4b9c ldr r3, [pc, #624] @ (8003134 <_printf_float+0x2c8>)
8002ec4: f04f 32ff mov.w r2, #4294967295
8002ec8: f7fd fe38 bl 8000b3c <__aeabi_dcmpun>
8002ecc: bb70 cbnz r0, 8002f2c <_printf_float+0xc0>
8002ece: e9dd 0106 ldrd r0, r1, [sp, #24]
8002ed2: 4b98 ldr r3, [pc, #608] @ (8003134 <_printf_float+0x2c8>)
8002ed4: f04f 32ff mov.w r2, #4294967295
8002ed8: f7fd fe12 bl 8000b00 <__aeabi_dcmple>
8002edc: bb30 cbnz r0, 8002f2c <_printf_float+0xc0>
8002ede: 2200 movs r2, #0
8002ee0: 2300 movs r3, #0
8002ee2: 4640 mov r0, r8
8002ee4: 4649 mov r1, r9
8002ee6: f7fd fe01 bl 8000aec <__aeabi_dcmplt>
8002eea: b110 cbz r0, 8002ef2 <_printf_float+0x86>
8002eec: 232d movs r3, #45 @ 0x2d
8002eee: f884 3043 strb.w r3, [r4, #67] @ 0x43
8002ef2: 4a91 ldr r2, [pc, #580] @ (8003138 <_printf_float+0x2cc>)
8002ef4: 4b91 ldr r3, [pc, #580] @ (800313c <_printf_float+0x2d0>)
8002ef6: f1ba 0f47 cmp.w sl, #71 @ 0x47
8002efa: bf8c ite hi
8002efc: 4690 movhi r8, r2
8002efe: 4698 movls r8, r3
8002f00: 2303 movs r3, #3
8002f02: 6123 str r3, [r4, #16]
8002f04: f02b 0304 bic.w r3, fp, #4
8002f08: 6023 str r3, [r4, #0]
8002f0a: f04f 0900 mov.w r9, #0
8002f0e: 9700 str r7, [sp, #0]
8002f10: 4633 mov r3, r6
8002f12: aa0b add r2, sp, #44 @ 0x2c
8002f14: 4621 mov r1, r4
8002f16: 4628 mov r0, r5
8002f18: f000 f9d2 bl 80032c0 <_printf_common>
8002f1c: 3001 adds r0, #1
8002f1e: f040 808d bne.w 800303c <_printf_float+0x1d0>
8002f22: f04f 30ff mov.w r0, #4294967295
8002f26: b00d add sp, #52 @ 0x34
8002f28: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
8002f2c: 4642 mov r2, r8
8002f2e: 464b mov r3, r9
8002f30: 4640 mov r0, r8
8002f32: 4649 mov r1, r9
8002f34: f7fd fe02 bl 8000b3c <__aeabi_dcmpun>
8002f38: b140 cbz r0, 8002f4c <_printf_float+0xe0>
8002f3a: 464b mov r3, r9
8002f3c: 2b00 cmp r3, #0
8002f3e: bfbc itt lt
8002f40: 232d movlt r3, #45 @ 0x2d
8002f42: f884 3043 strblt.w r3, [r4, #67] @ 0x43
8002f46: 4a7e ldr r2, [pc, #504] @ (8003140 <_printf_float+0x2d4>)
8002f48: 4b7e ldr r3, [pc, #504] @ (8003144 <_printf_float+0x2d8>)
8002f4a: e7d4 b.n 8002ef6 <_printf_float+0x8a>
8002f4c: 6863 ldr r3, [r4, #4]
8002f4e: f00a 02df and.w r2, sl, #223 @ 0xdf
8002f52: 9206 str r2, [sp, #24]
8002f54: 1c5a adds r2, r3, #1
8002f56: d13b bne.n 8002fd0 <_printf_float+0x164>
8002f58: 2306 movs r3, #6
8002f5a: 6063 str r3, [r4, #4]
8002f5c: f44b 6280 orr.w r2, fp, #1024 @ 0x400
8002f60: 2300 movs r3, #0
8002f62: 6022 str r2, [r4, #0]
8002f64: 9303 str r3, [sp, #12]
8002f66: ab0a add r3, sp, #40 @ 0x28
8002f68: e9cd a301 strd sl, r3, [sp, #4]
8002f6c: ab09 add r3, sp, #36 @ 0x24
8002f6e: 9300 str r3, [sp, #0]
8002f70: 6861 ldr r1, [r4, #4]
8002f72: ec49 8b10 vmov d0, r8, r9
8002f76: f10d 0323 add.w r3, sp, #35 @ 0x23
8002f7a: 4628 mov r0, r5
8002f7c: f7ff fed6 bl 8002d2c <__cvt>
8002f80: 9b06 ldr r3, [sp, #24]
8002f82: 9909 ldr r1, [sp, #36] @ 0x24
8002f84: 2b47 cmp r3, #71 @ 0x47
8002f86: 4680 mov r8, r0
8002f88: d129 bne.n 8002fde <_printf_float+0x172>
8002f8a: 1cc8 adds r0, r1, #3
8002f8c: db02 blt.n 8002f94 <_printf_float+0x128>
8002f8e: 6863 ldr r3, [r4, #4]
8002f90: 4299 cmp r1, r3
8002f92: dd41 ble.n 8003018 <_printf_float+0x1ac>
8002f94: f1aa 0a02 sub.w sl, sl, #2
8002f98: fa5f fa8a uxtb.w sl, sl
8002f9c: 3901 subs r1, #1
8002f9e: 4652 mov r2, sl
8002fa0: f104 0050 add.w r0, r4, #80 @ 0x50
8002fa4: 9109 str r1, [sp, #36] @ 0x24
8002fa6: f7ff ff26 bl 8002df6 <__exponent>
8002faa: 9a0a ldr r2, [sp, #40] @ 0x28
8002fac: 1813 adds r3, r2, r0
8002fae: 2a01 cmp r2, #1
8002fb0: 4681 mov r9, r0
8002fb2: 6123 str r3, [r4, #16]
8002fb4: dc02 bgt.n 8002fbc <_printf_float+0x150>
8002fb6: 6822 ldr r2, [r4, #0]
8002fb8: 07d2 lsls r2, r2, #31
8002fba: d501 bpl.n 8002fc0 <_printf_float+0x154>
8002fbc: 3301 adds r3, #1
8002fbe: 6123 str r3, [r4, #16]
8002fc0: f89d 3023 ldrb.w r3, [sp, #35] @ 0x23
8002fc4: 2b00 cmp r3, #0
8002fc6: d0a2 beq.n 8002f0e <_printf_float+0xa2>
8002fc8: 232d movs r3, #45 @ 0x2d
8002fca: f884 3043 strb.w r3, [r4, #67] @ 0x43
8002fce: e79e b.n 8002f0e <_printf_float+0xa2>
8002fd0: 9a06 ldr r2, [sp, #24]
8002fd2: 2a47 cmp r2, #71 @ 0x47
8002fd4: d1c2 bne.n 8002f5c <_printf_float+0xf0>
8002fd6: 2b00 cmp r3, #0
8002fd8: d1c0 bne.n 8002f5c <_printf_float+0xf0>
8002fda: 2301 movs r3, #1
8002fdc: e7bd b.n 8002f5a <_printf_float+0xee>
8002fde: f1ba 0f65 cmp.w sl, #101 @ 0x65
8002fe2: d9db bls.n 8002f9c <_printf_float+0x130>
8002fe4: f1ba 0f66 cmp.w sl, #102 @ 0x66
8002fe8: d118 bne.n 800301c <_printf_float+0x1b0>
8002fea: 2900 cmp r1, #0
8002fec: 6863 ldr r3, [r4, #4]
8002fee: dd0b ble.n 8003008 <_printf_float+0x19c>
8002ff0: 6121 str r1, [r4, #16]
8002ff2: b913 cbnz r3, 8002ffa <_printf_float+0x18e>
8002ff4: 6822 ldr r2, [r4, #0]
8002ff6: 07d0 lsls r0, r2, #31
8002ff8: d502 bpl.n 8003000 <_printf_float+0x194>
8002ffa: 3301 adds r3, #1
8002ffc: 440b add r3, r1
8002ffe: 6123 str r3, [r4, #16]
8003000: 65a1 str r1, [r4, #88] @ 0x58
8003002: f04f 0900 mov.w r9, #0
8003006: e7db b.n 8002fc0 <_printf_float+0x154>
8003008: b913 cbnz r3, 8003010 <_printf_float+0x1a4>
800300a: 6822 ldr r2, [r4, #0]
800300c: 07d2 lsls r2, r2, #31
800300e: d501 bpl.n 8003014 <_printf_float+0x1a8>
8003010: 3302 adds r3, #2
8003012: e7f4 b.n 8002ffe <_printf_float+0x192>
8003014: 2301 movs r3, #1
8003016: e7f2 b.n 8002ffe <_printf_float+0x192>
8003018: f04f 0a67 mov.w sl, #103 @ 0x67
800301c: 9b0a ldr r3, [sp, #40] @ 0x28
800301e: 4299 cmp r1, r3
8003020: db05 blt.n 800302e <_printf_float+0x1c2>
8003022: 6823 ldr r3, [r4, #0]
8003024: 6121 str r1, [r4, #16]
8003026: 07d8 lsls r0, r3, #31
8003028: d5ea bpl.n 8003000 <_printf_float+0x194>
800302a: 1c4b adds r3, r1, #1
800302c: e7e7 b.n 8002ffe <_printf_float+0x192>
800302e: 2900 cmp r1, #0
8003030: bfd4 ite le
8003032: f1c1 0202 rsble r2, r1, #2
8003036: 2201 movgt r2, #1
8003038: 4413 add r3, r2
800303a: e7e0 b.n 8002ffe <_printf_float+0x192>
800303c: 6823 ldr r3, [r4, #0]
800303e: 055a lsls r2, r3, #21
8003040: d407 bmi.n 8003052 <_printf_float+0x1e6>
8003042: 6923 ldr r3, [r4, #16]
8003044: 4642 mov r2, r8
8003046: 4631 mov r1, r6
8003048: 4628 mov r0, r5
800304a: 47b8 blx r7
800304c: 3001 adds r0, #1
800304e: d12b bne.n 80030a8 <_printf_float+0x23c>
8003050: e767 b.n 8002f22 <_printf_float+0xb6>
8003052: f1ba 0f65 cmp.w sl, #101 @ 0x65
8003056: f240 80dd bls.w 8003214 <_printf_float+0x3a8>
800305a: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48
800305e: 2200 movs r2, #0
8003060: 2300 movs r3, #0
8003062: f7fd fd39 bl 8000ad8 <__aeabi_dcmpeq>
8003066: 2800 cmp r0, #0
8003068: d033 beq.n 80030d2 <_printf_float+0x266>
800306a: 4a37 ldr r2, [pc, #220] @ (8003148 <_printf_float+0x2dc>)
800306c: 2301 movs r3, #1
800306e: 4631 mov r1, r6
8003070: 4628 mov r0, r5
8003072: 47b8 blx r7
8003074: 3001 adds r0, #1
8003076: f43f af54 beq.w 8002f22 <_printf_float+0xb6>
800307a: e9dd 3809 ldrd r3, r8, [sp, #36] @ 0x24
800307e: 4543 cmp r3, r8
8003080: db02 blt.n 8003088 <_printf_float+0x21c>
8003082: 6823 ldr r3, [r4, #0]
8003084: 07d8 lsls r0, r3, #31
8003086: d50f bpl.n 80030a8 <_printf_float+0x23c>
8003088: e9dd 2304 ldrd r2, r3, [sp, #16]
800308c: 4631 mov r1, r6
800308e: 4628 mov r0, r5
8003090: 47b8 blx r7
8003092: 3001 adds r0, #1
8003094: f43f af45 beq.w 8002f22 <_printf_float+0xb6>
8003098: f04f 0900 mov.w r9, #0
800309c: f108 38ff add.w r8, r8, #4294967295
80030a0: f104 0a1a add.w sl, r4, #26
80030a4: 45c8 cmp r8, r9
80030a6: dc09 bgt.n 80030bc <_printf_float+0x250>
80030a8: 6823 ldr r3, [r4, #0]
80030aa: 079b lsls r3, r3, #30
80030ac: f100 8103 bmi.w 80032b6 <_printf_float+0x44a>
80030b0: 68e0 ldr r0, [r4, #12]
80030b2: 9b0b ldr r3, [sp, #44] @ 0x2c
80030b4: 4298 cmp r0, r3
80030b6: bfb8 it lt
80030b8: 4618 movlt r0, r3
80030ba: e734 b.n 8002f26 <_printf_float+0xba>
80030bc: 2301 movs r3, #1
80030be: 4652 mov r2, sl
80030c0: 4631 mov r1, r6
80030c2: 4628 mov r0, r5
80030c4: 47b8 blx r7
80030c6: 3001 adds r0, #1
80030c8: f43f af2b beq.w 8002f22 <_printf_float+0xb6>
80030cc: f109 0901 add.w r9, r9, #1
80030d0: e7e8 b.n 80030a4 <_printf_float+0x238>
80030d2: 9b09 ldr r3, [sp, #36] @ 0x24
80030d4: 2b00 cmp r3, #0
80030d6: dc39 bgt.n 800314c <_printf_float+0x2e0>
80030d8: 4a1b ldr r2, [pc, #108] @ (8003148 <_printf_float+0x2dc>)
80030da: 2301 movs r3, #1
80030dc: 4631 mov r1, r6
80030de: 4628 mov r0, r5
80030e0: 47b8 blx r7
80030e2: 3001 adds r0, #1
80030e4: f43f af1d beq.w 8002f22 <_printf_float+0xb6>
80030e8: e9dd 3909 ldrd r3, r9, [sp, #36] @ 0x24
80030ec: ea59 0303 orrs.w r3, r9, r3
80030f0: d102 bne.n 80030f8 <_printf_float+0x28c>
80030f2: 6823 ldr r3, [r4, #0]
80030f4: 07d9 lsls r1, r3, #31
80030f6: d5d7 bpl.n 80030a8 <_printf_float+0x23c>
80030f8: e9dd 2304 ldrd r2, r3, [sp, #16]
80030fc: 4631 mov r1, r6
80030fe: 4628 mov r0, r5
8003100: 47b8 blx r7
8003102: 3001 adds r0, #1
8003104: f43f af0d beq.w 8002f22 <_printf_float+0xb6>
8003108: f04f 0a00 mov.w sl, #0
800310c: f104 0b1a add.w fp, r4, #26
8003110: 9b09 ldr r3, [sp, #36] @ 0x24
8003112: 425b negs r3, r3
8003114: 4553 cmp r3, sl
8003116: dc01 bgt.n 800311c <_printf_float+0x2b0>
8003118: 464b mov r3, r9
800311a: e793 b.n 8003044 <_printf_float+0x1d8>
800311c: 2301 movs r3, #1
800311e: 465a mov r2, fp
8003120: 4631 mov r1, r6
8003122: 4628 mov r0, r5
8003124: 47b8 blx r7
8003126: 3001 adds r0, #1
8003128: f43f aefb beq.w 8002f22 <_printf_float+0xb6>
800312c: f10a 0a01 add.w sl, sl, #1
8003130: e7ee b.n 8003110 <_printf_float+0x2a4>
8003132: bf00 nop
8003134: 7fefffff .word 0x7fefffff
8003138: 0800568c .word 0x0800568c
800313c: 08005688 .word 0x08005688
8003140: 08005694 .word 0x08005694
8003144: 08005690 .word 0x08005690
8003148: 08005698 .word 0x08005698
800314c: 6da3 ldr r3, [r4, #88] @ 0x58
800314e: f8dd a028 ldr.w sl, [sp, #40] @ 0x28
8003152: 4553 cmp r3, sl
8003154: bfa8 it ge
8003156: 4653 movge r3, sl
8003158: 2b00 cmp r3, #0
800315a: 4699 mov r9, r3
800315c: dc36 bgt.n 80031cc <_printf_float+0x360>
800315e: f04f 0b00 mov.w fp, #0
8003162: ea29 79e9 bic.w r9, r9, r9, asr #31
8003166: f104 021a add.w r2, r4, #26
800316a: 6da3 ldr r3, [r4, #88] @ 0x58
800316c: 9306 str r3, [sp, #24]
800316e: eba3 0309 sub.w r3, r3, r9
8003172: 455b cmp r3, fp
8003174: dc31 bgt.n 80031da <_printf_float+0x36e>
8003176: 9b09 ldr r3, [sp, #36] @ 0x24
8003178: 459a cmp sl, r3
800317a: dc3a bgt.n 80031f2 <_printf_float+0x386>
800317c: 6823 ldr r3, [r4, #0]
800317e: 07da lsls r2, r3, #31
8003180: d437 bmi.n 80031f2 <_printf_float+0x386>
8003182: 9b09 ldr r3, [sp, #36] @ 0x24
8003184: ebaa 0903 sub.w r9, sl, r3
8003188: 9b06 ldr r3, [sp, #24]
800318a: ebaa 0303 sub.w r3, sl, r3
800318e: 4599 cmp r9, r3
8003190: bfa8 it ge
8003192: 4699 movge r9, r3
8003194: f1b9 0f00 cmp.w r9, #0
8003198: dc33 bgt.n 8003202 <_printf_float+0x396>
800319a: f04f 0800 mov.w r8, #0
800319e: ea29 79e9 bic.w r9, r9, r9, asr #31
80031a2: f104 0b1a add.w fp, r4, #26
80031a6: 9b09 ldr r3, [sp, #36] @ 0x24
80031a8: ebaa 0303 sub.w r3, sl, r3
80031ac: eba3 0309 sub.w r3, r3, r9
80031b0: 4543 cmp r3, r8
80031b2: f77f af79 ble.w 80030a8 <_printf_float+0x23c>
80031b6: 2301 movs r3, #1
80031b8: 465a mov r2, fp
80031ba: 4631 mov r1, r6
80031bc: 4628 mov r0, r5
80031be: 47b8 blx r7
80031c0: 3001 adds r0, #1
80031c2: f43f aeae beq.w 8002f22 <_printf_float+0xb6>
80031c6: f108 0801 add.w r8, r8, #1
80031ca: e7ec b.n 80031a6 <_printf_float+0x33a>
80031cc: 4642 mov r2, r8
80031ce: 4631 mov r1, r6
80031d0: 4628 mov r0, r5
80031d2: 47b8 blx r7
80031d4: 3001 adds r0, #1
80031d6: d1c2 bne.n 800315e <_printf_float+0x2f2>
80031d8: e6a3 b.n 8002f22 <_printf_float+0xb6>
80031da: 2301 movs r3, #1
80031dc: 4631 mov r1, r6
80031de: 4628 mov r0, r5
80031e0: 9206 str r2, [sp, #24]
80031e2: 47b8 blx r7
80031e4: 3001 adds r0, #1
80031e6: f43f ae9c beq.w 8002f22 <_printf_float+0xb6>
80031ea: 9a06 ldr r2, [sp, #24]
80031ec: f10b 0b01 add.w fp, fp, #1
80031f0: e7bb b.n 800316a <_printf_float+0x2fe>
80031f2: e9dd 2304 ldrd r2, r3, [sp, #16]
80031f6: 4631 mov r1, r6
80031f8: 4628 mov r0, r5
80031fa: 47b8 blx r7
80031fc: 3001 adds r0, #1
80031fe: d1c0 bne.n 8003182 <_printf_float+0x316>
8003200: e68f b.n 8002f22 <_printf_float+0xb6>
8003202: 9a06 ldr r2, [sp, #24]
8003204: 464b mov r3, r9
8003206: 4442 add r2, r8
8003208: 4631 mov r1, r6
800320a: 4628 mov r0, r5
800320c: 47b8 blx r7
800320e: 3001 adds r0, #1
8003210: d1c3 bne.n 800319a <_printf_float+0x32e>
8003212: e686 b.n 8002f22 <_printf_float+0xb6>
8003214: f8dd a028 ldr.w sl, [sp, #40] @ 0x28
8003218: f1ba 0f01 cmp.w sl, #1
800321c: dc01 bgt.n 8003222 <_printf_float+0x3b6>
800321e: 07db lsls r3, r3, #31
8003220: d536 bpl.n 8003290 <_printf_float+0x424>
8003222: 2301 movs r3, #1
8003224: 4642 mov r2, r8
8003226: 4631 mov r1, r6
8003228: 4628 mov r0, r5
800322a: 47b8 blx r7
800322c: 3001 adds r0, #1
800322e: f43f ae78 beq.w 8002f22 <_printf_float+0xb6>
8003232: e9dd 2304 ldrd r2, r3, [sp, #16]
8003236: 4631 mov r1, r6
8003238: 4628 mov r0, r5
800323a: 47b8 blx r7
800323c: 3001 adds r0, #1
800323e: f43f ae70 beq.w 8002f22 <_printf_float+0xb6>
8003242: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48
8003246: 2200 movs r2, #0
8003248: 2300 movs r3, #0
800324a: f10a 3aff add.w sl, sl, #4294967295
800324e: f7fd fc43 bl 8000ad8 <__aeabi_dcmpeq>
8003252: b9c0 cbnz r0, 8003286 <_printf_float+0x41a>
8003254: 4653 mov r3, sl
8003256: f108 0201 add.w r2, r8, #1
800325a: 4631 mov r1, r6
800325c: 4628 mov r0, r5
800325e: 47b8 blx r7
8003260: 3001 adds r0, #1
8003262: d10c bne.n 800327e <_printf_float+0x412>
8003264: e65d b.n 8002f22 <_printf_float+0xb6>
8003266: 2301 movs r3, #1
8003268: 465a mov r2, fp
800326a: 4631 mov r1, r6
800326c: 4628 mov r0, r5
800326e: 47b8 blx r7
8003270: 3001 adds r0, #1
8003272: f43f ae56 beq.w 8002f22 <_printf_float+0xb6>
8003276: f108 0801 add.w r8, r8, #1
800327a: 45d0 cmp r8, sl
800327c: dbf3 blt.n 8003266 <_printf_float+0x3fa>
800327e: 464b mov r3, r9
8003280: f104 0250 add.w r2, r4, #80 @ 0x50
8003284: e6df b.n 8003046 <_printf_float+0x1da>
8003286: f04f 0800 mov.w r8, #0
800328a: f104 0b1a add.w fp, r4, #26
800328e: e7f4 b.n 800327a <_printf_float+0x40e>
8003290: 2301 movs r3, #1
8003292: 4642 mov r2, r8
8003294: e7e1 b.n 800325a <_printf_float+0x3ee>
8003296: 2301 movs r3, #1
8003298: 464a mov r2, r9
800329a: 4631 mov r1, r6
800329c: 4628 mov r0, r5
800329e: 47b8 blx r7
80032a0: 3001 adds r0, #1
80032a2: f43f ae3e beq.w 8002f22 <_printf_float+0xb6>
80032a6: f108 0801 add.w r8, r8, #1
80032aa: 68e3 ldr r3, [r4, #12]
80032ac: 990b ldr r1, [sp, #44] @ 0x2c
80032ae: 1a5b subs r3, r3, r1
80032b0: 4543 cmp r3, r8
80032b2: dcf0 bgt.n 8003296 <_printf_float+0x42a>
80032b4: e6fc b.n 80030b0 <_printf_float+0x244>
80032b6: f04f 0800 mov.w r8, #0
80032ba: f104 0919 add.w r9, r4, #25
80032be: e7f4 b.n 80032aa <_printf_float+0x43e>
080032c0 <_printf_common>:
80032c0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80032c4: 4616 mov r6, r2
80032c6: 4698 mov r8, r3
80032c8: 688a ldr r2, [r1, #8]
80032ca: 690b ldr r3, [r1, #16]
80032cc: f8dd 9020 ldr.w r9, [sp, #32]
80032d0: 4293 cmp r3, r2
80032d2: bfb8 it lt
80032d4: 4613 movlt r3, r2
80032d6: 6033 str r3, [r6, #0]
80032d8: f891 2043 ldrb.w r2, [r1, #67] @ 0x43
80032dc: 4607 mov r7, r0
80032de: 460c mov r4, r1
80032e0: b10a cbz r2, 80032e6 <_printf_common+0x26>
80032e2: 3301 adds r3, #1
80032e4: 6033 str r3, [r6, #0]
80032e6: 6823 ldr r3, [r4, #0]
80032e8: 0699 lsls r1, r3, #26
80032ea: bf42 ittt mi
80032ec: 6833 ldrmi r3, [r6, #0]
80032ee: 3302 addmi r3, #2
80032f0: 6033 strmi r3, [r6, #0]
80032f2: 6825 ldr r5, [r4, #0]
80032f4: f015 0506 ands.w r5, r5, #6
80032f8: d106 bne.n 8003308 <_printf_common+0x48>
80032fa: f104 0a19 add.w sl, r4, #25
80032fe: 68e3 ldr r3, [r4, #12]
8003300: 6832 ldr r2, [r6, #0]
8003302: 1a9b subs r3, r3, r2
8003304: 42ab cmp r3, r5
8003306: dc26 bgt.n 8003356 <_printf_common+0x96>
8003308: f894 3043 ldrb.w r3, [r4, #67] @ 0x43
800330c: 6822 ldr r2, [r4, #0]
800330e: 3b00 subs r3, #0
8003310: bf18 it ne
8003312: 2301 movne r3, #1
8003314: 0692 lsls r2, r2, #26
8003316: d42b bmi.n 8003370 <_printf_common+0xb0>
8003318: f104 0243 add.w r2, r4, #67 @ 0x43
800331c: 4641 mov r1, r8
800331e: 4638 mov r0, r7
8003320: 47c8 blx r9
8003322: 3001 adds r0, #1
8003324: d01e beq.n 8003364 <_printf_common+0xa4>
8003326: 6823 ldr r3, [r4, #0]
8003328: 6922 ldr r2, [r4, #16]
800332a: f003 0306 and.w r3, r3, #6
800332e: 2b04 cmp r3, #4
8003330: bf02 ittt eq
8003332: 68e5 ldreq r5, [r4, #12]
8003334: 6833 ldreq r3, [r6, #0]
8003336: 1aed subeq r5, r5, r3
8003338: 68a3 ldr r3, [r4, #8]
800333a: bf0c ite eq
800333c: ea25 75e5 biceq.w r5, r5, r5, asr #31
8003340: 2500 movne r5, #0
8003342: 4293 cmp r3, r2
8003344: bfc4 itt gt
8003346: 1a9b subgt r3, r3, r2
8003348: 18ed addgt r5, r5, r3
800334a: 2600 movs r6, #0
800334c: 341a adds r4, #26
800334e: 42b5 cmp r5, r6
8003350: d11a bne.n 8003388 <_printf_common+0xc8>
8003352: 2000 movs r0, #0
8003354: e008 b.n 8003368 <_printf_common+0xa8>
8003356: 2301 movs r3, #1
8003358: 4652 mov r2, sl
800335a: 4641 mov r1, r8
800335c: 4638 mov r0, r7
800335e: 47c8 blx r9
8003360: 3001 adds r0, #1
8003362: d103 bne.n 800336c <_printf_common+0xac>
8003364: f04f 30ff mov.w r0, #4294967295
8003368: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800336c: 3501 adds r5, #1
800336e: e7c6 b.n 80032fe <_printf_common+0x3e>
8003370: 18e1 adds r1, r4, r3
8003372: 1c5a adds r2, r3, #1
8003374: 2030 movs r0, #48 @ 0x30
8003376: f881 0043 strb.w r0, [r1, #67] @ 0x43
800337a: 4422 add r2, r4
800337c: f894 1045 ldrb.w r1, [r4, #69] @ 0x45
8003380: f882 1043 strb.w r1, [r2, #67] @ 0x43
8003384: 3302 adds r3, #2
8003386: e7c7 b.n 8003318 <_printf_common+0x58>
8003388: 2301 movs r3, #1
800338a: 4622 mov r2, r4
800338c: 4641 mov r1, r8
800338e: 4638 mov r0, r7
8003390: 47c8 blx r9
8003392: 3001 adds r0, #1
8003394: d0e6 beq.n 8003364 <_printf_common+0xa4>
8003396: 3601 adds r6, #1
8003398: e7d9 b.n 800334e <_printf_common+0x8e>
...
0800339c <_printf_i>:
800339c: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
80033a0: 7e0f ldrb r7, [r1, #24]
80033a2: 9e0c ldr r6, [sp, #48] @ 0x30
80033a4: 2f78 cmp r7, #120 @ 0x78
80033a6: 4691 mov r9, r2
80033a8: 4680 mov r8, r0
80033aa: 460c mov r4, r1
80033ac: 469a mov sl, r3
80033ae: f101 0243 add.w r2, r1, #67 @ 0x43
80033b2: d807 bhi.n 80033c4 <_printf_i+0x28>
80033b4: 2f62 cmp r7, #98 @ 0x62
80033b6: d80a bhi.n 80033ce <_printf_i+0x32>
80033b8: 2f00 cmp r7, #0
80033ba: f000 80d1 beq.w 8003560 <_printf_i+0x1c4>
80033be: 2f58 cmp r7, #88 @ 0x58
80033c0: f000 80b8 beq.w 8003534 <_printf_i+0x198>
80033c4: f104 0642 add.w r6, r4, #66 @ 0x42
80033c8: f884 7042 strb.w r7, [r4, #66] @ 0x42
80033cc: e03a b.n 8003444 <_printf_i+0xa8>
80033ce: f1a7 0363 sub.w r3, r7, #99 @ 0x63
80033d2: 2b15 cmp r3, #21
80033d4: d8f6 bhi.n 80033c4 <_printf_i+0x28>
80033d6: a101 add r1, pc, #4 @ (adr r1, 80033dc <_printf_i+0x40>)
80033d8: f851 f023 ldr.w pc, [r1, r3, lsl #2]
80033dc: 08003435 .word 0x08003435
80033e0: 08003449 .word 0x08003449
80033e4: 080033c5 .word 0x080033c5
80033e8: 080033c5 .word 0x080033c5
80033ec: 080033c5 .word 0x080033c5
80033f0: 080033c5 .word 0x080033c5
80033f4: 08003449 .word 0x08003449
80033f8: 080033c5 .word 0x080033c5
80033fc: 080033c5 .word 0x080033c5
8003400: 080033c5 .word 0x080033c5
8003404: 080033c5 .word 0x080033c5
8003408: 08003547 .word 0x08003547
800340c: 08003473 .word 0x08003473
8003410: 08003501 .word 0x08003501
8003414: 080033c5 .word 0x080033c5
8003418: 080033c5 .word 0x080033c5
800341c: 08003569 .word 0x08003569
8003420: 080033c5 .word 0x080033c5
8003424: 08003473 .word 0x08003473
8003428: 080033c5 .word 0x080033c5
800342c: 080033c5 .word 0x080033c5
8003430: 08003509 .word 0x08003509
8003434: 6833 ldr r3, [r6, #0]
8003436: 1d1a adds r2, r3, #4
8003438: 681b ldr r3, [r3, #0]
800343a: 6032 str r2, [r6, #0]
800343c: f104 0642 add.w r6, r4, #66 @ 0x42
8003440: f884 3042 strb.w r3, [r4, #66] @ 0x42
8003444: 2301 movs r3, #1
8003446: e09c b.n 8003582 <_printf_i+0x1e6>
8003448: 6833 ldr r3, [r6, #0]
800344a: 6820 ldr r0, [r4, #0]
800344c: 1d19 adds r1, r3, #4
800344e: 6031 str r1, [r6, #0]
8003450: 0606 lsls r6, r0, #24
8003452: d501 bpl.n 8003458 <_printf_i+0xbc>
8003454: 681d ldr r5, [r3, #0]
8003456: e003 b.n 8003460 <_printf_i+0xc4>
8003458: 0645 lsls r5, r0, #25
800345a: d5fb bpl.n 8003454 <_printf_i+0xb8>
800345c: f9b3 5000 ldrsh.w r5, [r3]
8003460: 2d00 cmp r5, #0
8003462: da03 bge.n 800346c <_printf_i+0xd0>
8003464: 232d movs r3, #45 @ 0x2d
8003466: 426d negs r5, r5
8003468: f884 3043 strb.w r3, [r4, #67] @ 0x43
800346c: 4858 ldr r0, [pc, #352] @ (80035d0 <_printf_i+0x234>)
800346e: 230a movs r3, #10
8003470: e011 b.n 8003496 <_printf_i+0xfa>
8003472: 6821 ldr r1, [r4, #0]
8003474: 6833 ldr r3, [r6, #0]
8003476: 0608 lsls r0, r1, #24
8003478: f853 5b04 ldr.w r5, [r3], #4
800347c: d402 bmi.n 8003484 <_printf_i+0xe8>
800347e: 0649 lsls r1, r1, #25
8003480: bf48 it mi
8003482: b2ad uxthmi r5, r5
8003484: 2f6f cmp r7, #111 @ 0x6f
8003486: 4852 ldr r0, [pc, #328] @ (80035d0 <_printf_i+0x234>)
8003488: 6033 str r3, [r6, #0]
800348a: bf14 ite ne
800348c: 230a movne r3, #10
800348e: 2308 moveq r3, #8
8003490: 2100 movs r1, #0
8003492: f884 1043 strb.w r1, [r4, #67] @ 0x43
8003496: 6866 ldr r6, [r4, #4]
8003498: 60a6 str r6, [r4, #8]
800349a: 2e00 cmp r6, #0
800349c: db05 blt.n 80034aa <_printf_i+0x10e>
800349e: 6821 ldr r1, [r4, #0]
80034a0: 432e orrs r6, r5
80034a2: f021 0104 bic.w r1, r1, #4
80034a6: 6021 str r1, [r4, #0]
80034a8: d04b beq.n 8003542 <_printf_i+0x1a6>
80034aa: 4616 mov r6, r2
80034ac: fbb5 f1f3 udiv r1, r5, r3
80034b0: fb03 5711 mls r7, r3, r1, r5
80034b4: 5dc7 ldrb r7, [r0, r7]
80034b6: f806 7d01 strb.w r7, [r6, #-1]!
80034ba: 462f mov r7, r5
80034bc: 42bb cmp r3, r7
80034be: 460d mov r5, r1
80034c0: d9f4 bls.n 80034ac <_printf_i+0x110>
80034c2: 2b08 cmp r3, #8
80034c4: d10b bne.n 80034de <_printf_i+0x142>
80034c6: 6823 ldr r3, [r4, #0]
80034c8: 07df lsls r7, r3, #31
80034ca: d508 bpl.n 80034de <_printf_i+0x142>
80034cc: 6923 ldr r3, [r4, #16]
80034ce: 6861 ldr r1, [r4, #4]
80034d0: 4299 cmp r1, r3
80034d2: bfde ittt le
80034d4: 2330 movle r3, #48 @ 0x30
80034d6: f806 3c01 strble.w r3, [r6, #-1]
80034da: f106 36ff addle.w r6, r6, #4294967295
80034de: 1b92 subs r2, r2, r6
80034e0: 6122 str r2, [r4, #16]
80034e2: f8cd a000 str.w sl, [sp]
80034e6: 464b mov r3, r9
80034e8: aa03 add r2, sp, #12
80034ea: 4621 mov r1, r4
80034ec: 4640 mov r0, r8
80034ee: f7ff fee7 bl 80032c0 <_printf_common>
80034f2: 3001 adds r0, #1
80034f4: d14a bne.n 800358c <_printf_i+0x1f0>
80034f6: f04f 30ff mov.w r0, #4294967295
80034fa: b004 add sp, #16
80034fc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8003500: 6823 ldr r3, [r4, #0]
8003502: f043 0320 orr.w r3, r3, #32
8003506: 6023 str r3, [r4, #0]
8003508: 4832 ldr r0, [pc, #200] @ (80035d4 <_printf_i+0x238>)
800350a: 2778 movs r7, #120 @ 0x78
800350c: f884 7045 strb.w r7, [r4, #69] @ 0x45
8003510: 6823 ldr r3, [r4, #0]
8003512: 6831 ldr r1, [r6, #0]
8003514: 061f lsls r7, r3, #24
8003516: f851 5b04 ldr.w r5, [r1], #4
800351a: d402 bmi.n 8003522 <_printf_i+0x186>
800351c: 065f lsls r7, r3, #25
800351e: bf48 it mi
8003520: b2ad uxthmi r5, r5
8003522: 6031 str r1, [r6, #0]
8003524: 07d9 lsls r1, r3, #31
8003526: bf44 itt mi
8003528: f043 0320 orrmi.w r3, r3, #32
800352c: 6023 strmi r3, [r4, #0]
800352e: b11d cbz r5, 8003538 <_printf_i+0x19c>
8003530: 2310 movs r3, #16
8003532: e7ad b.n 8003490 <_printf_i+0xf4>
8003534: 4826 ldr r0, [pc, #152] @ (80035d0 <_printf_i+0x234>)
8003536: e7e9 b.n 800350c <_printf_i+0x170>
8003538: 6823 ldr r3, [r4, #0]
800353a: f023 0320 bic.w r3, r3, #32
800353e: 6023 str r3, [r4, #0]
8003540: e7f6 b.n 8003530 <_printf_i+0x194>
8003542: 4616 mov r6, r2
8003544: e7bd b.n 80034c2 <_printf_i+0x126>
8003546: 6833 ldr r3, [r6, #0]
8003548: 6825 ldr r5, [r4, #0]
800354a: 6961 ldr r1, [r4, #20]
800354c: 1d18 adds r0, r3, #4
800354e: 6030 str r0, [r6, #0]
8003550: 062e lsls r6, r5, #24
8003552: 681b ldr r3, [r3, #0]
8003554: d501 bpl.n 800355a <_printf_i+0x1be>
8003556: 6019 str r1, [r3, #0]
8003558: e002 b.n 8003560 <_printf_i+0x1c4>
800355a: 0668 lsls r0, r5, #25
800355c: d5fb bpl.n 8003556 <_printf_i+0x1ba>
800355e: 8019 strh r1, [r3, #0]
8003560: 2300 movs r3, #0
8003562: 6123 str r3, [r4, #16]
8003564: 4616 mov r6, r2
8003566: e7bc b.n 80034e2 <_printf_i+0x146>
8003568: 6833 ldr r3, [r6, #0]
800356a: 1d1a adds r2, r3, #4
800356c: 6032 str r2, [r6, #0]
800356e: 681e ldr r6, [r3, #0]
8003570: 6862 ldr r2, [r4, #4]
8003572: 2100 movs r1, #0
8003574: 4630 mov r0, r6
8003576: f7fc fe33 bl 80001e0 <memchr>
800357a: b108 cbz r0, 8003580 <_printf_i+0x1e4>
800357c: 1b80 subs r0, r0, r6
800357e: 6060 str r0, [r4, #4]
8003580: 6863 ldr r3, [r4, #4]
8003582: 6123 str r3, [r4, #16]
8003584: 2300 movs r3, #0
8003586: f884 3043 strb.w r3, [r4, #67] @ 0x43
800358a: e7aa b.n 80034e2 <_printf_i+0x146>
800358c: 6923 ldr r3, [r4, #16]
800358e: 4632 mov r2, r6
8003590: 4649 mov r1, r9
8003592: 4640 mov r0, r8
8003594: 47d0 blx sl
8003596: 3001 adds r0, #1
8003598: d0ad beq.n 80034f6 <_printf_i+0x15a>
800359a: 6823 ldr r3, [r4, #0]
800359c: 079b lsls r3, r3, #30
800359e: d413 bmi.n 80035c8 <_printf_i+0x22c>
80035a0: 68e0 ldr r0, [r4, #12]
80035a2: 9b03 ldr r3, [sp, #12]
80035a4: 4298 cmp r0, r3
80035a6: bfb8 it lt
80035a8: 4618 movlt r0, r3
80035aa: e7a6 b.n 80034fa <_printf_i+0x15e>
80035ac: 2301 movs r3, #1
80035ae: 4632 mov r2, r6
80035b0: 4649 mov r1, r9
80035b2: 4640 mov r0, r8
80035b4: 47d0 blx sl
80035b6: 3001 adds r0, #1
80035b8: d09d beq.n 80034f6 <_printf_i+0x15a>
80035ba: 3501 adds r5, #1
80035bc: 68e3 ldr r3, [r4, #12]
80035be: 9903 ldr r1, [sp, #12]
80035c0: 1a5b subs r3, r3, r1
80035c2: 42ab cmp r3, r5
80035c4: dcf2 bgt.n 80035ac <_printf_i+0x210>
80035c6: e7eb b.n 80035a0 <_printf_i+0x204>
80035c8: 2500 movs r5, #0
80035ca: f104 0619 add.w r6, r4, #25
80035ce: e7f5 b.n 80035bc <_printf_i+0x220>
80035d0: 0800569a .word 0x0800569a
80035d4: 080056ab .word 0x080056ab
080035d8 <std>:
80035d8: 2300 movs r3, #0
80035da: b510 push {r4, lr}
80035dc: 4604 mov r4, r0
80035de: e9c0 3300 strd r3, r3, [r0]
80035e2: e9c0 3304 strd r3, r3, [r0, #16]
80035e6: 6083 str r3, [r0, #8]
80035e8: 8181 strh r1, [r0, #12]
80035ea: 6643 str r3, [r0, #100] @ 0x64
80035ec: 81c2 strh r2, [r0, #14]
80035ee: 6183 str r3, [r0, #24]
80035f0: 4619 mov r1, r3
80035f2: 2208 movs r2, #8
80035f4: 305c adds r0, #92 @ 0x5c
80035f6: f000 f8f4 bl 80037e2 <memset>
80035fa: 4b0d ldr r3, [pc, #52] @ (8003630 <std+0x58>)
80035fc: 6263 str r3, [r4, #36] @ 0x24
80035fe: 4b0d ldr r3, [pc, #52] @ (8003634 <std+0x5c>)
8003600: 62a3 str r3, [r4, #40] @ 0x28
8003602: 4b0d ldr r3, [pc, #52] @ (8003638 <std+0x60>)
8003604: 62e3 str r3, [r4, #44] @ 0x2c
8003606: 4b0d ldr r3, [pc, #52] @ (800363c <std+0x64>)
8003608: 6323 str r3, [r4, #48] @ 0x30
800360a: 4b0d ldr r3, [pc, #52] @ (8003640 <std+0x68>)
800360c: 6224 str r4, [r4, #32]
800360e: 429c cmp r4, r3
8003610: d006 beq.n 8003620 <std+0x48>
8003612: f103 0268 add.w r2, r3, #104 @ 0x68
8003616: 4294 cmp r4, r2
8003618: d002 beq.n 8003620 <std+0x48>
800361a: 33d0 adds r3, #208 @ 0xd0
800361c: 429c cmp r4, r3
800361e: d105 bne.n 800362c <std+0x54>
8003620: f104 0058 add.w r0, r4, #88 @ 0x58
8003624: e8bd 4010 ldmia.w sp!, {r4, lr}
8003628: f000 b958 b.w 80038dc <__retarget_lock_init_recursive>
800362c: bd10 pop {r4, pc}
800362e: bf00 nop
8003630: 0800375d .word 0x0800375d
8003634: 0800377f .word 0x0800377f
8003638: 080037b7 .word 0x080037b7
800363c: 080037db .word 0x080037db
8003640: 20000660 .word 0x20000660
08003644 <stdio_exit_handler>:
8003644: 4a02 ldr r2, [pc, #8] @ (8003650 <stdio_exit_handler+0xc>)
8003646: 4903 ldr r1, [pc, #12] @ (8003654 <stdio_exit_handler+0x10>)
8003648: 4803 ldr r0, [pc, #12] @ (8003658 <stdio_exit_handler+0x14>)
800364a: f000 b869 b.w 8003720 <_fwalk_sglue>
800364e: bf00 nop
8003650: 2000000c .word 0x2000000c
8003654: 08004f95 .word 0x08004f95
8003658: 2000001c .word 0x2000001c
0800365c <cleanup_stdio>:
800365c: 6841 ldr r1, [r0, #4]
800365e: 4b0c ldr r3, [pc, #48] @ (8003690 <cleanup_stdio+0x34>)
8003660: 4299 cmp r1, r3
8003662: b510 push {r4, lr}
8003664: 4604 mov r4, r0
8003666: d001 beq.n 800366c <cleanup_stdio+0x10>
8003668: f001 fc94 bl 8004f94 <_fflush_r>
800366c: 68a1 ldr r1, [r4, #8]
800366e: 4b09 ldr r3, [pc, #36] @ (8003694 <cleanup_stdio+0x38>)
8003670: 4299 cmp r1, r3
8003672: d002 beq.n 800367a <cleanup_stdio+0x1e>
8003674: 4620 mov r0, r4
8003676: f001 fc8d bl 8004f94 <_fflush_r>
800367a: 68e1 ldr r1, [r4, #12]
800367c: 4b06 ldr r3, [pc, #24] @ (8003698 <cleanup_stdio+0x3c>)
800367e: 4299 cmp r1, r3
8003680: d004 beq.n 800368c <cleanup_stdio+0x30>
8003682: 4620 mov r0, r4
8003684: e8bd 4010 ldmia.w sp!, {r4, lr}
8003688: f001 bc84 b.w 8004f94 <_fflush_r>
800368c: bd10 pop {r4, pc}
800368e: bf00 nop
8003690: 20000660 .word 0x20000660
8003694: 200006c8 .word 0x200006c8
8003698: 20000730 .word 0x20000730
0800369c <global_stdio_init.part.0>:
800369c: b510 push {r4, lr}
800369e: 4b0b ldr r3, [pc, #44] @ (80036cc <global_stdio_init.part.0+0x30>)
80036a0: 4c0b ldr r4, [pc, #44] @ (80036d0 <global_stdio_init.part.0+0x34>)
80036a2: 4a0c ldr r2, [pc, #48] @ (80036d4 <global_stdio_init.part.0+0x38>)
80036a4: 601a str r2, [r3, #0]
80036a6: 4620 mov r0, r4
80036a8: 2200 movs r2, #0
80036aa: 2104 movs r1, #4
80036ac: f7ff ff94 bl 80035d8 <std>
80036b0: f104 0068 add.w r0, r4, #104 @ 0x68
80036b4: 2201 movs r2, #1
80036b6: 2109 movs r1, #9
80036b8: f7ff ff8e bl 80035d8 <std>
80036bc: f104 00d0 add.w r0, r4, #208 @ 0xd0
80036c0: 2202 movs r2, #2
80036c2: e8bd 4010 ldmia.w sp!, {r4, lr}
80036c6: 2112 movs r1, #18
80036c8: f7ff bf86 b.w 80035d8 <std>
80036cc: 20000798 .word 0x20000798
80036d0: 20000660 .word 0x20000660
80036d4: 08003645 .word 0x08003645
080036d8 <__sfp_lock_acquire>:
80036d8: 4801 ldr r0, [pc, #4] @ (80036e0 <__sfp_lock_acquire+0x8>)
80036da: f000 b900 b.w 80038de <__retarget_lock_acquire_recursive>
80036de: bf00 nop
80036e0: 200007a1 .word 0x200007a1
080036e4 <__sfp_lock_release>:
80036e4: 4801 ldr r0, [pc, #4] @ (80036ec <__sfp_lock_release+0x8>)
80036e6: f000 b8fb b.w 80038e0 <__retarget_lock_release_recursive>
80036ea: bf00 nop
80036ec: 200007a1 .word 0x200007a1
080036f0 <__sinit>:
80036f0: b510 push {r4, lr}
80036f2: 4604 mov r4, r0
80036f4: f7ff fff0 bl 80036d8 <__sfp_lock_acquire>
80036f8: 6a23 ldr r3, [r4, #32]
80036fa: b11b cbz r3, 8003704 <__sinit+0x14>
80036fc: e8bd 4010 ldmia.w sp!, {r4, lr}
8003700: f7ff bff0 b.w 80036e4 <__sfp_lock_release>
8003704: 4b04 ldr r3, [pc, #16] @ (8003718 <__sinit+0x28>)
8003706: 6223 str r3, [r4, #32]
8003708: 4b04 ldr r3, [pc, #16] @ (800371c <__sinit+0x2c>)
800370a: 681b ldr r3, [r3, #0]
800370c: 2b00 cmp r3, #0
800370e: d1f5 bne.n 80036fc <__sinit+0xc>
8003710: f7ff ffc4 bl 800369c <global_stdio_init.part.0>
8003714: e7f2 b.n 80036fc <__sinit+0xc>
8003716: bf00 nop
8003718: 0800365d .word 0x0800365d
800371c: 20000798 .word 0x20000798
08003720 <_fwalk_sglue>:
8003720: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
8003724: 4607 mov r7, r0
8003726: 4688 mov r8, r1
8003728: 4614 mov r4, r2
800372a: 2600 movs r6, #0
800372c: e9d4 9501 ldrd r9, r5, [r4, #4]
8003730: f1b9 0901 subs.w r9, r9, #1
8003734: d505 bpl.n 8003742 <_fwalk_sglue+0x22>
8003736: 6824 ldr r4, [r4, #0]
8003738: 2c00 cmp r4, #0
800373a: d1f7 bne.n 800372c <_fwalk_sglue+0xc>
800373c: 4630 mov r0, r6
800373e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
8003742: 89ab ldrh r3, [r5, #12]
8003744: 2b01 cmp r3, #1
8003746: d907 bls.n 8003758 <_fwalk_sglue+0x38>
8003748: f9b5 300e ldrsh.w r3, [r5, #14]
800374c: 3301 adds r3, #1
800374e: d003 beq.n 8003758 <_fwalk_sglue+0x38>
8003750: 4629 mov r1, r5
8003752: 4638 mov r0, r7
8003754: 47c0 blx r8
8003756: 4306 orrs r6, r0
8003758: 3568 adds r5, #104 @ 0x68
800375a: e7e9 b.n 8003730 <_fwalk_sglue+0x10>
0800375c <__sread>:
800375c: b510 push {r4, lr}
800375e: 460c mov r4, r1
8003760: f9b1 100e ldrsh.w r1, [r1, #14]
8003764: f000 f86c bl 8003840 <_read_r>
8003768: 2800 cmp r0, #0
800376a: bfab itete ge
800376c: 6d63 ldrge r3, [r4, #84] @ 0x54
800376e: 89a3 ldrhlt r3, [r4, #12]
8003770: 181b addge r3, r3, r0
8003772: f423 5380 biclt.w r3, r3, #4096 @ 0x1000
8003776: bfac ite ge
8003778: 6563 strge r3, [r4, #84] @ 0x54
800377a: 81a3 strhlt r3, [r4, #12]
800377c: bd10 pop {r4, pc}
0800377e <__swrite>:
800377e: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
8003782: 461f mov r7, r3
8003784: 898b ldrh r3, [r1, #12]
8003786: 05db lsls r3, r3, #23
8003788: 4605 mov r5, r0
800378a: 460c mov r4, r1
800378c: 4616 mov r6, r2
800378e: d505 bpl.n 800379c <__swrite+0x1e>
8003790: f9b1 100e ldrsh.w r1, [r1, #14]
8003794: 2302 movs r3, #2
8003796: 2200 movs r2, #0
8003798: f000 f840 bl 800381c <_lseek_r>
800379c: 89a3 ldrh r3, [r4, #12]
800379e: f9b4 100e ldrsh.w r1, [r4, #14]
80037a2: f423 5380 bic.w r3, r3, #4096 @ 0x1000
80037a6: 81a3 strh r3, [r4, #12]
80037a8: 4632 mov r2, r6
80037aa: 463b mov r3, r7
80037ac: 4628 mov r0, r5
80037ae: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
80037b2: f000 b857 b.w 8003864 <_write_r>
080037b6 <__sseek>:
80037b6: b510 push {r4, lr}
80037b8: 460c mov r4, r1
80037ba: f9b1 100e ldrsh.w r1, [r1, #14]
80037be: f000 f82d bl 800381c <_lseek_r>
80037c2: 1c43 adds r3, r0, #1
80037c4: 89a3 ldrh r3, [r4, #12]
80037c6: bf15 itete ne
80037c8: 6560 strne r0, [r4, #84] @ 0x54
80037ca: f423 5380 biceq.w r3, r3, #4096 @ 0x1000
80037ce: f443 5380 orrne.w r3, r3, #4096 @ 0x1000
80037d2: 81a3 strheq r3, [r4, #12]
80037d4: bf18 it ne
80037d6: 81a3 strhne r3, [r4, #12]
80037d8: bd10 pop {r4, pc}
080037da <__sclose>:
80037da: f9b1 100e ldrsh.w r1, [r1, #14]
80037de: f000 b80d b.w 80037fc <_close_r>
080037e2 <memset>:
80037e2: 4402 add r2, r0
80037e4: 4603 mov r3, r0
80037e6: 4293 cmp r3, r2
80037e8: d100 bne.n 80037ec <memset+0xa>
80037ea: 4770 bx lr
80037ec: f803 1b01 strb.w r1, [r3], #1
80037f0: e7f9 b.n 80037e6 <memset+0x4>
...
080037f4 <_localeconv_r>:
80037f4: 4800 ldr r0, [pc, #0] @ (80037f8 <_localeconv_r+0x4>)
80037f6: 4770 bx lr
80037f8: 20000158 .word 0x20000158
080037fc <_close_r>:
80037fc: b538 push {r3, r4, r5, lr}
80037fe: 4d06 ldr r5, [pc, #24] @ (8003818 <_close_r+0x1c>)
8003800: 2300 movs r3, #0
8003802: 4604 mov r4, r0
8003804: 4608 mov r0, r1
8003806: 602b str r3, [r5, #0]
8003808: f7fd fd45 bl 8001296 <_close>
800380c: 1c43 adds r3, r0, #1
800380e: d102 bne.n 8003816 <_close_r+0x1a>
8003810: 682b ldr r3, [r5, #0]
8003812: b103 cbz r3, 8003816 <_close_r+0x1a>
8003814: 6023 str r3, [r4, #0]
8003816: bd38 pop {r3, r4, r5, pc}
8003818: 2000079c .word 0x2000079c
0800381c <_lseek_r>:
800381c: b538 push {r3, r4, r5, lr}
800381e: 4d07 ldr r5, [pc, #28] @ (800383c <_lseek_r+0x20>)
8003820: 4604 mov r4, r0
8003822: 4608 mov r0, r1
8003824: 4611 mov r1, r2
8003826: 2200 movs r2, #0
8003828: 602a str r2, [r5, #0]
800382a: 461a mov r2, r3
800382c: f7fd fd5a bl 80012e4 <_lseek>
8003830: 1c43 adds r3, r0, #1
8003832: d102 bne.n 800383a <_lseek_r+0x1e>
8003834: 682b ldr r3, [r5, #0]
8003836: b103 cbz r3, 800383a <_lseek_r+0x1e>
8003838: 6023 str r3, [r4, #0]
800383a: bd38 pop {r3, r4, r5, pc}
800383c: 2000079c .word 0x2000079c
08003840 <_read_r>:
8003840: b538 push {r3, r4, r5, lr}
8003842: 4d07 ldr r5, [pc, #28] @ (8003860 <_read_r+0x20>)
8003844: 4604 mov r4, r0
8003846: 4608 mov r0, r1
8003848: 4611 mov r1, r2
800384a: 2200 movs r2, #0
800384c: 602a str r2, [r5, #0]
800384e: 461a mov r2, r3
8003850: f7fd fce8 bl 8001224 <_read>
8003854: 1c43 adds r3, r0, #1
8003856: d102 bne.n 800385e <_read_r+0x1e>
8003858: 682b ldr r3, [r5, #0]
800385a: b103 cbz r3, 800385e <_read_r+0x1e>
800385c: 6023 str r3, [r4, #0]
800385e: bd38 pop {r3, r4, r5, pc}
8003860: 2000079c .word 0x2000079c
08003864 <_write_r>:
8003864: b538 push {r3, r4, r5, lr}
8003866: 4d07 ldr r5, [pc, #28] @ (8003884 <_write_r+0x20>)
8003868: 4604 mov r4, r0
800386a: 4608 mov r0, r1
800386c: 4611 mov r1, r2
800386e: 2200 movs r2, #0
8003870: 602a str r2, [r5, #0]
8003872: 461a mov r2, r3
8003874: f7fd fcf3 bl 800125e <_write>
8003878: 1c43 adds r3, r0, #1
800387a: d102 bne.n 8003882 <_write_r+0x1e>
800387c: 682b ldr r3, [r5, #0]
800387e: b103 cbz r3, 8003882 <_write_r+0x1e>
8003880: 6023 str r3, [r4, #0]
8003882: bd38 pop {r3, r4, r5, pc}
8003884: 2000079c .word 0x2000079c
08003888 <__errno>:
8003888: 4b01 ldr r3, [pc, #4] @ (8003890 <__errno+0x8>)
800388a: 6818 ldr r0, [r3, #0]
800388c: 4770 bx lr
800388e: bf00 nop
8003890: 20000018 .word 0x20000018
08003894 <__libc_init_array>:
8003894: b570 push {r4, r5, r6, lr}
8003896: 4d0d ldr r5, [pc, #52] @ (80038cc <__libc_init_array+0x38>)
8003898: 4c0d ldr r4, [pc, #52] @ (80038d0 <__libc_init_array+0x3c>)
800389a: 1b64 subs r4, r4, r5
800389c: 10a4 asrs r4, r4, #2
800389e: 2600 movs r6, #0
80038a0: 42a6 cmp r6, r4
80038a2: d109 bne.n 80038b8 <__libc_init_array+0x24>
80038a4: 4d0b ldr r5, [pc, #44] @ (80038d4 <__libc_init_array+0x40>)
80038a6: 4c0c ldr r4, [pc, #48] @ (80038d8 <__libc_init_array+0x44>)
80038a8: f001 fec2 bl 8005630 <_init>
80038ac: 1b64 subs r4, r4, r5
80038ae: 10a4 asrs r4, r4, #2
80038b0: 2600 movs r6, #0
80038b2: 42a6 cmp r6, r4
80038b4: d105 bne.n 80038c2 <__libc_init_array+0x2e>
80038b6: bd70 pop {r4, r5, r6, pc}
80038b8: f855 3b04 ldr.w r3, [r5], #4
80038bc: 4798 blx r3
80038be: 3601 adds r6, #1
80038c0: e7ee b.n 80038a0 <__libc_init_array+0xc>
80038c2: f855 3b04 ldr.w r3, [r5], #4
80038c6: 4798 blx r3
80038c8: 3601 adds r6, #1
80038ca: e7f2 b.n 80038b2 <__libc_init_array+0x1e>
80038cc: 08005a04 .word 0x08005a04
80038d0: 08005a04 .word 0x08005a04
80038d4: 08005a04 .word 0x08005a04
80038d8: 08005a08 .word 0x08005a08
080038dc <__retarget_lock_init_recursive>:
80038dc: 4770 bx lr
080038de <__retarget_lock_acquire_recursive>:
80038de: 4770 bx lr
080038e0 <__retarget_lock_release_recursive>:
80038e0: 4770 bx lr
080038e2 <quorem>:
80038e2: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
80038e6: 6903 ldr r3, [r0, #16]
80038e8: 690c ldr r4, [r1, #16]
80038ea: 42a3 cmp r3, r4
80038ec: 4607 mov r7, r0
80038ee: db7e blt.n 80039ee <quorem+0x10c>
80038f0: 3c01 subs r4, #1
80038f2: f101 0814 add.w r8, r1, #20
80038f6: 00a3 lsls r3, r4, #2
80038f8: f100 0514 add.w r5, r0, #20
80038fc: 9300 str r3, [sp, #0]
80038fe: eb05 0384 add.w r3, r5, r4, lsl #2
8003902: 9301 str r3, [sp, #4]
8003904: f858 3024 ldr.w r3, [r8, r4, lsl #2]
8003908: f855 2024 ldr.w r2, [r5, r4, lsl #2]
800390c: 3301 adds r3, #1
800390e: 429a cmp r2, r3
8003910: eb08 0984 add.w r9, r8, r4, lsl #2
8003914: fbb2 f6f3 udiv r6, r2, r3
8003918: d32e bcc.n 8003978 <quorem+0x96>
800391a: f04f 0a00 mov.w sl, #0
800391e: 46c4 mov ip, r8
8003920: 46ae mov lr, r5
8003922: 46d3 mov fp, sl
8003924: f85c 3b04 ldr.w r3, [ip], #4
8003928: b298 uxth r0, r3
800392a: fb06 a000 mla r0, r6, r0, sl
800392e: 0c02 lsrs r2, r0, #16
8003930: 0c1b lsrs r3, r3, #16
8003932: fb06 2303 mla r3, r6, r3, r2
8003936: f8de 2000 ldr.w r2, [lr]
800393a: b280 uxth r0, r0
800393c: b292 uxth r2, r2
800393e: 1a12 subs r2, r2, r0
8003940: 445a add r2, fp
8003942: f8de 0000 ldr.w r0, [lr]
8003946: ea4f 4a13 mov.w sl, r3, lsr #16
800394a: b29b uxth r3, r3
800394c: ebc3 4322 rsb r3, r3, r2, asr #16
8003950: eb03 4310 add.w r3, r3, r0, lsr #16
8003954: b292 uxth r2, r2
8003956: ea42 4203 orr.w r2, r2, r3, lsl #16
800395a: 45e1 cmp r9, ip
800395c: f84e 2b04 str.w r2, [lr], #4
8003960: ea4f 4b23 mov.w fp, r3, asr #16
8003964: d2de bcs.n 8003924 <quorem+0x42>
8003966: 9b00 ldr r3, [sp, #0]
8003968: 58eb ldr r3, [r5, r3]
800396a: b92b cbnz r3, 8003978 <quorem+0x96>
800396c: 9b01 ldr r3, [sp, #4]
800396e: 3b04 subs r3, #4
8003970: 429d cmp r5, r3
8003972: 461a mov r2, r3
8003974: d32f bcc.n 80039d6 <quorem+0xf4>
8003976: 613c str r4, [r7, #16]
8003978: 4638 mov r0, r7
800397a: f001 f97f bl 8004c7c <__mcmp>
800397e: 2800 cmp r0, #0
8003980: db25 blt.n 80039ce <quorem+0xec>
8003982: 4629 mov r1, r5
8003984: 2000 movs r0, #0
8003986: f858 2b04 ldr.w r2, [r8], #4
800398a: f8d1 c000 ldr.w ip, [r1]
800398e: fa1f fe82 uxth.w lr, r2
8003992: fa1f f38c uxth.w r3, ip
8003996: eba3 030e sub.w r3, r3, lr
800399a: 4403 add r3, r0
800399c: 0c12 lsrs r2, r2, #16
800399e: ebc2 4223 rsb r2, r2, r3, asr #16
80039a2: eb02 421c add.w r2, r2, ip, lsr #16
80039a6: b29b uxth r3, r3
80039a8: ea43 4302 orr.w r3, r3, r2, lsl #16
80039ac: 45c1 cmp r9, r8
80039ae: f841 3b04 str.w r3, [r1], #4
80039b2: ea4f 4022 mov.w r0, r2, asr #16
80039b6: d2e6 bcs.n 8003986 <quorem+0xa4>
80039b8: f855 2024 ldr.w r2, [r5, r4, lsl #2]
80039bc: eb05 0384 add.w r3, r5, r4, lsl #2
80039c0: b922 cbnz r2, 80039cc <quorem+0xea>
80039c2: 3b04 subs r3, #4
80039c4: 429d cmp r5, r3
80039c6: 461a mov r2, r3
80039c8: d30b bcc.n 80039e2 <quorem+0x100>
80039ca: 613c str r4, [r7, #16]
80039cc: 3601 adds r6, #1
80039ce: 4630 mov r0, r6
80039d0: b003 add sp, #12
80039d2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
80039d6: 6812 ldr r2, [r2, #0]
80039d8: 3b04 subs r3, #4
80039da: 2a00 cmp r2, #0
80039dc: d1cb bne.n 8003976 <quorem+0x94>
80039de: 3c01 subs r4, #1
80039e0: e7c6 b.n 8003970 <quorem+0x8e>
80039e2: 6812 ldr r2, [r2, #0]
80039e4: 3b04 subs r3, #4
80039e6: 2a00 cmp r2, #0
80039e8: d1ef bne.n 80039ca <quorem+0xe8>
80039ea: 3c01 subs r4, #1
80039ec: e7ea b.n 80039c4 <quorem+0xe2>
80039ee: 2000 movs r0, #0
80039f0: e7ee b.n 80039d0 <quorem+0xee>
80039f2: 0000 movs r0, r0
80039f4: 0000 movs r0, r0
...
080039f8 <_dtoa_r>:
80039f8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
80039fc: 69c7 ldr r7, [r0, #28]
80039fe: b097 sub sp, #92 @ 0x5c
8003a00: ed8d 0b04 vstr d0, [sp, #16]
8003a04: ec55 4b10 vmov r4, r5, d0
8003a08: 9e20 ldr r6, [sp, #128] @ 0x80
8003a0a: 9107 str r1, [sp, #28]
8003a0c: 4681 mov r9, r0
8003a0e: 920c str r2, [sp, #48] @ 0x30
8003a10: 9311 str r3, [sp, #68] @ 0x44
8003a12: b97f cbnz r7, 8003a34 <_dtoa_r+0x3c>
8003a14: 2010 movs r0, #16
8003a16: f000 fe09 bl 800462c <malloc>
8003a1a: 4602 mov r2, r0
8003a1c: f8c9 001c str.w r0, [r9, #28]
8003a20: b920 cbnz r0, 8003a2c <_dtoa_r+0x34>
8003a22: 4ba9 ldr r3, [pc, #676] @ (8003cc8 <_dtoa_r+0x2d0>)
8003a24: 21ef movs r1, #239 @ 0xef
8003a26: 48a9 ldr r0, [pc, #676] @ (8003ccc <_dtoa_r+0x2d4>)
8003a28: f001 fafa bl 8005020 <__assert_func>
8003a2c: e9c0 7701 strd r7, r7, [r0, #4]
8003a30: 6007 str r7, [r0, #0]
8003a32: 60c7 str r7, [r0, #12]
8003a34: f8d9 301c ldr.w r3, [r9, #28]
8003a38: 6819 ldr r1, [r3, #0]
8003a3a: b159 cbz r1, 8003a54 <_dtoa_r+0x5c>
8003a3c: 685a ldr r2, [r3, #4]
8003a3e: 604a str r2, [r1, #4]
8003a40: 2301 movs r3, #1
8003a42: 4093 lsls r3, r2
8003a44: 608b str r3, [r1, #8]
8003a46: 4648 mov r0, r9
8003a48: f000 fee6 bl 8004818 <_Bfree>
8003a4c: f8d9 301c ldr.w r3, [r9, #28]
8003a50: 2200 movs r2, #0
8003a52: 601a str r2, [r3, #0]
8003a54: 1e2b subs r3, r5, #0
8003a56: bfb9 ittee lt
8003a58: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000
8003a5c: 9305 strlt r3, [sp, #20]
8003a5e: 2300 movge r3, #0
8003a60: 6033 strge r3, [r6, #0]
8003a62: 9f05 ldr r7, [sp, #20]
8003a64: 4b9a ldr r3, [pc, #616] @ (8003cd0 <_dtoa_r+0x2d8>)
8003a66: bfbc itt lt
8003a68: 2201 movlt r2, #1
8003a6a: 6032 strlt r2, [r6, #0]
8003a6c: 43bb bics r3, r7
8003a6e: d112 bne.n 8003a96 <_dtoa_r+0x9e>
8003a70: 9a11 ldr r2, [sp, #68] @ 0x44
8003a72: f242 730f movw r3, #9999 @ 0x270f
8003a76: 6013 str r3, [r2, #0]
8003a78: f3c7 0313 ubfx r3, r7, #0, #20
8003a7c: 4323 orrs r3, r4
8003a7e: f000 855a beq.w 8004536 <_dtoa_r+0xb3e>
8003a82: 9b21 ldr r3, [sp, #132] @ 0x84
8003a84: f8df a25c ldr.w sl, [pc, #604] @ 8003ce4 <_dtoa_r+0x2ec>
8003a88: 2b00 cmp r3, #0
8003a8a: f000 855c beq.w 8004546 <_dtoa_r+0xb4e>
8003a8e: f10a 0303 add.w r3, sl, #3
8003a92: f000 bd56 b.w 8004542 <_dtoa_r+0xb4a>
8003a96: ed9d 7b04 vldr d7, [sp, #16]
8003a9a: 2200 movs r2, #0
8003a9c: ec51 0b17 vmov r0, r1, d7
8003aa0: 2300 movs r3, #0
8003aa2: ed8d 7b0a vstr d7, [sp, #40] @ 0x28
8003aa6: f7fd f817 bl 8000ad8 <__aeabi_dcmpeq>
8003aaa: 4680 mov r8, r0
8003aac: b158 cbz r0, 8003ac6 <_dtoa_r+0xce>
8003aae: 9a11 ldr r2, [sp, #68] @ 0x44
8003ab0: 2301 movs r3, #1
8003ab2: 6013 str r3, [r2, #0]
8003ab4: 9b21 ldr r3, [sp, #132] @ 0x84
8003ab6: b113 cbz r3, 8003abe <_dtoa_r+0xc6>
8003ab8: 9a21 ldr r2, [sp, #132] @ 0x84
8003aba: 4b86 ldr r3, [pc, #536] @ (8003cd4 <_dtoa_r+0x2dc>)
8003abc: 6013 str r3, [r2, #0]
8003abe: f8df a228 ldr.w sl, [pc, #552] @ 8003ce8 <_dtoa_r+0x2f0>
8003ac2: f000 bd40 b.w 8004546 <_dtoa_r+0xb4e>
8003ac6: ed9d 0b0a vldr d0, [sp, #40] @ 0x28
8003aca: aa14 add r2, sp, #80 @ 0x50
8003acc: a915 add r1, sp, #84 @ 0x54
8003ace: 4648 mov r0, r9
8003ad0: f001 f984 bl 8004ddc <__d2b>
8003ad4: f3c7 560a ubfx r6, r7, #20, #11
8003ad8: 9002 str r0, [sp, #8]
8003ada: 2e00 cmp r6, #0
8003adc: d078 beq.n 8003bd0 <_dtoa_r+0x1d8>
8003ade: 9b0b ldr r3, [sp, #44] @ 0x2c
8003ae0: f8cd 8048 str.w r8, [sp, #72] @ 0x48
8003ae4: f3c3 0313 ubfx r3, r3, #0, #20
8003ae8: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
8003aec: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000
8003af0: f443 1340 orr.w r3, r3, #3145728 @ 0x300000
8003af4: f2a6 36ff subw r6, r6, #1023 @ 0x3ff
8003af8: 4619 mov r1, r3
8003afa: 2200 movs r2, #0
8003afc: 4b76 ldr r3, [pc, #472] @ (8003cd8 <_dtoa_r+0x2e0>)
8003afe: f7fc fbcb bl 8000298 <__aeabi_dsub>
8003b02: a36b add r3, pc, #428 @ (adr r3, 8003cb0 <_dtoa_r+0x2b8>)
8003b04: e9d3 2300 ldrd r2, r3, [r3]
8003b08: f7fc fd7e bl 8000608 <__aeabi_dmul>
8003b0c: a36a add r3, pc, #424 @ (adr r3, 8003cb8 <_dtoa_r+0x2c0>)
8003b0e: e9d3 2300 ldrd r2, r3, [r3]
8003b12: f7fc fbc3 bl 800029c <__adddf3>
8003b16: 4604 mov r4, r0
8003b18: 4630 mov r0, r6
8003b1a: 460d mov r5, r1
8003b1c: f7fc fd0a bl 8000534 <__aeabi_i2d>
8003b20: a367 add r3, pc, #412 @ (adr r3, 8003cc0 <_dtoa_r+0x2c8>)
8003b22: e9d3 2300 ldrd r2, r3, [r3]
8003b26: f7fc fd6f bl 8000608 <__aeabi_dmul>
8003b2a: 4602 mov r2, r0
8003b2c: 460b mov r3, r1
8003b2e: 4620 mov r0, r4
8003b30: 4629 mov r1, r5
8003b32: f7fc fbb3 bl 800029c <__adddf3>
8003b36: 4604 mov r4, r0
8003b38: 460d mov r5, r1
8003b3a: f7fd f815 bl 8000b68 <__aeabi_d2iz>
8003b3e: 2200 movs r2, #0
8003b40: 4607 mov r7, r0
8003b42: 2300 movs r3, #0
8003b44: 4620 mov r0, r4
8003b46: 4629 mov r1, r5
8003b48: f7fc ffd0 bl 8000aec <__aeabi_dcmplt>
8003b4c: b140 cbz r0, 8003b60 <_dtoa_r+0x168>
8003b4e: 4638 mov r0, r7
8003b50: f7fc fcf0 bl 8000534 <__aeabi_i2d>
8003b54: 4622 mov r2, r4
8003b56: 462b mov r3, r5
8003b58: f7fc ffbe bl 8000ad8 <__aeabi_dcmpeq>
8003b5c: b900 cbnz r0, 8003b60 <_dtoa_r+0x168>
8003b5e: 3f01 subs r7, #1
8003b60: 2f16 cmp r7, #22
8003b62: d852 bhi.n 8003c0a <_dtoa_r+0x212>
8003b64: 4b5d ldr r3, [pc, #372] @ (8003cdc <_dtoa_r+0x2e4>)
8003b66: eb03 03c7 add.w r3, r3, r7, lsl #3
8003b6a: e9d3 2300 ldrd r2, r3, [r3]
8003b6e: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
8003b72: f7fc ffbb bl 8000aec <__aeabi_dcmplt>
8003b76: 2800 cmp r0, #0
8003b78: d049 beq.n 8003c0e <_dtoa_r+0x216>
8003b7a: 3f01 subs r7, #1
8003b7c: 2300 movs r3, #0
8003b7e: 9310 str r3, [sp, #64] @ 0x40
8003b80: 9b14 ldr r3, [sp, #80] @ 0x50
8003b82: 1b9b subs r3, r3, r6
8003b84: 1e5a subs r2, r3, #1
8003b86: bf45 ittet mi
8003b88: f1c3 0301 rsbmi r3, r3, #1
8003b8c: 9300 strmi r3, [sp, #0]
8003b8e: 2300 movpl r3, #0
8003b90: 2300 movmi r3, #0
8003b92: 9206 str r2, [sp, #24]
8003b94: bf54 ite pl
8003b96: 9300 strpl r3, [sp, #0]
8003b98: 9306 strmi r3, [sp, #24]
8003b9a: 2f00 cmp r7, #0
8003b9c: db39 blt.n 8003c12 <_dtoa_r+0x21a>
8003b9e: 9b06 ldr r3, [sp, #24]
8003ba0: 970d str r7, [sp, #52] @ 0x34
8003ba2: 443b add r3, r7
8003ba4: 9306 str r3, [sp, #24]
8003ba6: 2300 movs r3, #0
8003ba8: 9308 str r3, [sp, #32]
8003baa: 9b07 ldr r3, [sp, #28]
8003bac: 2b09 cmp r3, #9
8003bae: d863 bhi.n 8003c78 <_dtoa_r+0x280>
8003bb0: 2b05 cmp r3, #5
8003bb2: bfc4 itt gt
8003bb4: 3b04 subgt r3, #4
8003bb6: 9307 strgt r3, [sp, #28]
8003bb8: 9b07 ldr r3, [sp, #28]
8003bba: f1a3 0302 sub.w r3, r3, #2
8003bbe: bfcc ite gt
8003bc0: 2400 movgt r4, #0
8003bc2: 2401 movle r4, #1
8003bc4: 2b03 cmp r3, #3
8003bc6: d863 bhi.n 8003c90 <_dtoa_r+0x298>
8003bc8: e8df f003 tbb [pc, r3]
8003bcc: 2b375452 .word 0x2b375452
8003bd0: e9dd 6314 ldrd r6, r3, [sp, #80] @ 0x50
8003bd4: 441e add r6, r3
8003bd6: f206 4332 addw r3, r6, #1074 @ 0x432
8003bda: 2b20 cmp r3, #32
8003bdc: bfc1 itttt gt
8003bde: f1c3 0340 rsbgt r3, r3, #64 @ 0x40
8003be2: 409f lslgt r7, r3
8003be4: f206 4312 addwgt r3, r6, #1042 @ 0x412
8003be8: fa24 f303 lsrgt.w r3, r4, r3
8003bec: bfd6 itet le
8003bee: f1c3 0320 rsble r3, r3, #32
8003bf2: ea47 0003 orrgt.w r0, r7, r3
8003bf6: fa04 f003 lslle.w r0, r4, r3
8003bfa: f7fc fc8b bl 8000514 <__aeabi_ui2d>
8003bfe: 2201 movs r2, #1
8003c00: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000
8003c04: 3e01 subs r6, #1
8003c06: 9212 str r2, [sp, #72] @ 0x48
8003c08: e776 b.n 8003af8 <_dtoa_r+0x100>
8003c0a: 2301 movs r3, #1
8003c0c: e7b7 b.n 8003b7e <_dtoa_r+0x186>
8003c0e: 9010 str r0, [sp, #64] @ 0x40
8003c10: e7b6 b.n 8003b80 <_dtoa_r+0x188>
8003c12: 9b00 ldr r3, [sp, #0]
8003c14: 1bdb subs r3, r3, r7
8003c16: 9300 str r3, [sp, #0]
8003c18: 427b negs r3, r7
8003c1a: 9308 str r3, [sp, #32]
8003c1c: 2300 movs r3, #0
8003c1e: 930d str r3, [sp, #52] @ 0x34
8003c20: e7c3 b.n 8003baa <_dtoa_r+0x1b2>
8003c22: 2301 movs r3, #1
8003c24: 9309 str r3, [sp, #36] @ 0x24
8003c26: 9b0c ldr r3, [sp, #48] @ 0x30
8003c28: eb07 0b03 add.w fp, r7, r3
8003c2c: f10b 0301 add.w r3, fp, #1
8003c30: 2b01 cmp r3, #1
8003c32: 9303 str r3, [sp, #12]
8003c34: bfb8 it lt
8003c36: 2301 movlt r3, #1
8003c38: e006 b.n 8003c48 <_dtoa_r+0x250>
8003c3a: 2301 movs r3, #1
8003c3c: 9309 str r3, [sp, #36] @ 0x24
8003c3e: 9b0c ldr r3, [sp, #48] @ 0x30
8003c40: 2b00 cmp r3, #0
8003c42: dd28 ble.n 8003c96 <_dtoa_r+0x29e>
8003c44: 469b mov fp, r3
8003c46: 9303 str r3, [sp, #12]
8003c48: f8d9 001c ldr.w r0, [r9, #28]
8003c4c: 2100 movs r1, #0
8003c4e: 2204 movs r2, #4
8003c50: f102 0514 add.w r5, r2, #20
8003c54: 429d cmp r5, r3
8003c56: d926 bls.n 8003ca6 <_dtoa_r+0x2ae>
8003c58: 6041 str r1, [r0, #4]
8003c5a: 4648 mov r0, r9
8003c5c: f000 fd9c bl 8004798 <_Balloc>
8003c60: 4682 mov sl, r0
8003c62: 2800 cmp r0, #0
8003c64: d142 bne.n 8003cec <_dtoa_r+0x2f4>
8003c66: 4b1e ldr r3, [pc, #120] @ (8003ce0 <_dtoa_r+0x2e8>)
8003c68: 4602 mov r2, r0
8003c6a: f240 11af movw r1, #431 @ 0x1af
8003c6e: e6da b.n 8003a26 <_dtoa_r+0x2e>
8003c70: 2300 movs r3, #0
8003c72: e7e3 b.n 8003c3c <_dtoa_r+0x244>
8003c74: 2300 movs r3, #0
8003c76: e7d5 b.n 8003c24 <_dtoa_r+0x22c>
8003c78: 2401 movs r4, #1
8003c7a: 2300 movs r3, #0
8003c7c: 9307 str r3, [sp, #28]
8003c7e: 9409 str r4, [sp, #36] @ 0x24
8003c80: f04f 3bff mov.w fp, #4294967295
8003c84: 2200 movs r2, #0
8003c86: f8cd b00c str.w fp, [sp, #12]
8003c8a: 2312 movs r3, #18
8003c8c: 920c str r2, [sp, #48] @ 0x30
8003c8e: e7db b.n 8003c48 <_dtoa_r+0x250>
8003c90: 2301 movs r3, #1
8003c92: 9309 str r3, [sp, #36] @ 0x24
8003c94: e7f4 b.n 8003c80 <_dtoa_r+0x288>
8003c96: f04f 0b01 mov.w fp, #1
8003c9a: f8cd b00c str.w fp, [sp, #12]
8003c9e: 465b mov r3, fp
8003ca0: f8cd b030 str.w fp, [sp, #48] @ 0x30
8003ca4: e7d0 b.n 8003c48 <_dtoa_r+0x250>
8003ca6: 3101 adds r1, #1
8003ca8: 0052 lsls r2, r2, #1
8003caa: e7d1 b.n 8003c50 <_dtoa_r+0x258>
8003cac: f3af 8000 nop.w
8003cb0: 636f4361 .word 0x636f4361
8003cb4: 3fd287a7 .word 0x3fd287a7
8003cb8: 8b60c8b3 .word 0x8b60c8b3
8003cbc: 3fc68a28 .word 0x3fc68a28
8003cc0: 509f79fb .word 0x509f79fb
8003cc4: 3fd34413 .word 0x3fd34413
8003cc8: 080056c9 .word 0x080056c9
8003ccc: 080056e0 .word 0x080056e0
8003cd0: 7ff00000 .word 0x7ff00000
8003cd4: 08005699 .word 0x08005699
8003cd8: 3ff80000 .word 0x3ff80000
8003cdc: 08005830 .word 0x08005830
8003ce0: 08005738 .word 0x08005738
8003ce4: 080056c5 .word 0x080056c5
8003ce8: 08005698 .word 0x08005698
8003cec: f8d9 301c ldr.w r3, [r9, #28]
8003cf0: 6018 str r0, [r3, #0]
8003cf2: 9b03 ldr r3, [sp, #12]
8003cf4: 2b0e cmp r3, #14
8003cf6: f200 80a1 bhi.w 8003e3c <_dtoa_r+0x444>
8003cfa: 2c00 cmp r4, #0
8003cfc: f000 809e beq.w 8003e3c <_dtoa_r+0x444>
8003d00: 2f00 cmp r7, #0
8003d02: dd33 ble.n 8003d6c <_dtoa_r+0x374>
8003d04: 4b9c ldr r3, [pc, #624] @ (8003f78 <_dtoa_r+0x580>)
8003d06: f007 020f and.w r2, r7, #15
8003d0a: eb03 03c2 add.w r3, r3, r2, lsl #3
8003d0e: ed93 7b00 vldr d7, [r3]
8003d12: 05f8 lsls r0, r7, #23
8003d14: ed8d 7b0e vstr d7, [sp, #56] @ 0x38
8003d18: ea4f 1427 mov.w r4, r7, asr #4
8003d1c: d516 bpl.n 8003d4c <_dtoa_r+0x354>
8003d1e: 4b97 ldr r3, [pc, #604] @ (8003f7c <_dtoa_r+0x584>)
8003d20: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
8003d24: e9d3 2308 ldrd r2, r3, [r3, #32]
8003d28: f7fc fd98 bl 800085c <__aeabi_ddiv>
8003d2c: e9cd 0104 strd r0, r1, [sp, #16]
8003d30: f004 040f and.w r4, r4, #15
8003d34: 2603 movs r6, #3
8003d36: 4d91 ldr r5, [pc, #580] @ (8003f7c <_dtoa_r+0x584>)
8003d38: b954 cbnz r4, 8003d50 <_dtoa_r+0x358>
8003d3a: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
8003d3e: e9dd 0104 ldrd r0, r1, [sp, #16]
8003d42: f7fc fd8b bl 800085c <__aeabi_ddiv>
8003d46: e9cd 0104 strd r0, r1, [sp, #16]
8003d4a: e028 b.n 8003d9e <_dtoa_r+0x3a6>
8003d4c: 2602 movs r6, #2
8003d4e: e7f2 b.n 8003d36 <_dtoa_r+0x33e>
8003d50: 07e1 lsls r1, r4, #31
8003d52: d508 bpl.n 8003d66 <_dtoa_r+0x36e>
8003d54: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38
8003d58: e9d5 2300 ldrd r2, r3, [r5]
8003d5c: f7fc fc54 bl 8000608 <__aeabi_dmul>
8003d60: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
8003d64: 3601 adds r6, #1
8003d66: 1064 asrs r4, r4, #1
8003d68: 3508 adds r5, #8
8003d6a: e7e5 b.n 8003d38 <_dtoa_r+0x340>
8003d6c: f000 80af beq.w 8003ece <_dtoa_r+0x4d6>
8003d70: 427c negs r4, r7
8003d72: 4b81 ldr r3, [pc, #516] @ (8003f78 <_dtoa_r+0x580>)
8003d74: 4d81 ldr r5, [pc, #516] @ (8003f7c <_dtoa_r+0x584>)
8003d76: f004 020f and.w r2, r4, #15
8003d7a: eb03 03c2 add.w r3, r3, r2, lsl #3
8003d7e: e9d3 2300 ldrd r2, r3, [r3]
8003d82: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
8003d86: f7fc fc3f bl 8000608 <__aeabi_dmul>
8003d8a: e9cd 0104 strd r0, r1, [sp, #16]
8003d8e: 1124 asrs r4, r4, #4
8003d90: 2300 movs r3, #0
8003d92: 2602 movs r6, #2
8003d94: 2c00 cmp r4, #0
8003d96: f040 808f bne.w 8003eb8 <_dtoa_r+0x4c0>
8003d9a: 2b00 cmp r3, #0
8003d9c: d1d3 bne.n 8003d46 <_dtoa_r+0x34e>
8003d9e: 9b10 ldr r3, [sp, #64] @ 0x40
8003da0: e9dd 4504 ldrd r4, r5, [sp, #16]
8003da4: 2b00 cmp r3, #0
8003da6: f000 8094 beq.w 8003ed2 <_dtoa_r+0x4da>
8003daa: 4b75 ldr r3, [pc, #468] @ (8003f80 <_dtoa_r+0x588>)
8003dac: 2200 movs r2, #0
8003dae: 4620 mov r0, r4
8003db0: 4629 mov r1, r5
8003db2: f7fc fe9b bl 8000aec <__aeabi_dcmplt>
8003db6: 2800 cmp r0, #0
8003db8: f000 808b beq.w 8003ed2 <_dtoa_r+0x4da>
8003dbc: 9b03 ldr r3, [sp, #12]
8003dbe: 2b00 cmp r3, #0
8003dc0: f000 8087 beq.w 8003ed2 <_dtoa_r+0x4da>
8003dc4: f1bb 0f00 cmp.w fp, #0
8003dc8: dd34 ble.n 8003e34 <_dtoa_r+0x43c>
8003dca: 4620 mov r0, r4
8003dcc: 4b6d ldr r3, [pc, #436] @ (8003f84 <_dtoa_r+0x58c>)
8003dce: 2200 movs r2, #0
8003dd0: 4629 mov r1, r5
8003dd2: f7fc fc19 bl 8000608 <__aeabi_dmul>
8003dd6: e9cd 0104 strd r0, r1, [sp, #16]
8003dda: f107 38ff add.w r8, r7, #4294967295
8003dde: 3601 adds r6, #1
8003de0: 465c mov r4, fp
8003de2: 4630 mov r0, r6
8003de4: f7fc fba6 bl 8000534 <__aeabi_i2d>
8003de8: e9dd 2304 ldrd r2, r3, [sp, #16]
8003dec: f7fc fc0c bl 8000608 <__aeabi_dmul>
8003df0: 4b65 ldr r3, [pc, #404] @ (8003f88 <_dtoa_r+0x590>)
8003df2: 2200 movs r2, #0
8003df4: f7fc fa52 bl 800029c <__adddf3>
8003df8: 4605 mov r5, r0
8003dfa: f1a1 7650 sub.w r6, r1, #54525952 @ 0x3400000
8003dfe: 2c00 cmp r4, #0
8003e00: d16a bne.n 8003ed8 <_dtoa_r+0x4e0>
8003e02: e9dd 0104 ldrd r0, r1, [sp, #16]
8003e06: 4b61 ldr r3, [pc, #388] @ (8003f8c <_dtoa_r+0x594>)
8003e08: 2200 movs r2, #0
8003e0a: f7fc fa45 bl 8000298 <__aeabi_dsub>
8003e0e: 4602 mov r2, r0
8003e10: 460b mov r3, r1
8003e12: e9cd 2304 strd r2, r3, [sp, #16]
8003e16: 462a mov r2, r5
8003e18: 4633 mov r3, r6
8003e1a: f7fc fe85 bl 8000b28 <__aeabi_dcmpgt>
8003e1e: 2800 cmp r0, #0
8003e20: f040 8298 bne.w 8004354 <_dtoa_r+0x95c>
8003e24: e9dd 0104 ldrd r0, r1, [sp, #16]
8003e28: 462a mov r2, r5
8003e2a: f106 4300 add.w r3, r6, #2147483648 @ 0x80000000
8003e2e: f7fc fe5d bl 8000aec <__aeabi_dcmplt>
8003e32: bb38 cbnz r0, 8003e84 <_dtoa_r+0x48c>
8003e34: e9dd 340a ldrd r3, r4, [sp, #40] @ 0x28
8003e38: e9cd 3404 strd r3, r4, [sp, #16]
8003e3c: 9b15 ldr r3, [sp, #84] @ 0x54
8003e3e: 2b00 cmp r3, #0
8003e40: f2c0 8157 blt.w 80040f2 <_dtoa_r+0x6fa>
8003e44: 2f0e cmp r7, #14
8003e46: f300 8154 bgt.w 80040f2 <_dtoa_r+0x6fa>
8003e4a: 4b4b ldr r3, [pc, #300] @ (8003f78 <_dtoa_r+0x580>)
8003e4c: eb03 03c7 add.w r3, r3, r7, lsl #3
8003e50: ed93 7b00 vldr d7, [r3]
8003e54: 9b0c ldr r3, [sp, #48] @ 0x30
8003e56: 2b00 cmp r3, #0
8003e58: ed8d 7b00 vstr d7, [sp]
8003e5c: f280 80e5 bge.w 800402a <_dtoa_r+0x632>
8003e60: 9b03 ldr r3, [sp, #12]
8003e62: 2b00 cmp r3, #0
8003e64: f300 80e1 bgt.w 800402a <_dtoa_r+0x632>
8003e68: d10c bne.n 8003e84 <_dtoa_r+0x48c>
8003e6a: 4b48 ldr r3, [pc, #288] @ (8003f8c <_dtoa_r+0x594>)
8003e6c: 2200 movs r2, #0
8003e6e: ec51 0b17 vmov r0, r1, d7
8003e72: f7fc fbc9 bl 8000608 <__aeabi_dmul>
8003e76: e9dd 2304 ldrd r2, r3, [sp, #16]
8003e7a: f7fc fe4b bl 8000b14 <__aeabi_dcmpge>
8003e7e: 2800 cmp r0, #0
8003e80: f000 8266 beq.w 8004350 <_dtoa_r+0x958>
8003e84: 2400 movs r4, #0
8003e86: 4625 mov r5, r4
8003e88: 9b0c ldr r3, [sp, #48] @ 0x30
8003e8a: 4656 mov r6, sl
8003e8c: ea6f 0803 mvn.w r8, r3
8003e90: 2700 movs r7, #0
8003e92: 4621 mov r1, r4
8003e94: 4648 mov r0, r9
8003e96: f000 fcbf bl 8004818 <_Bfree>
8003e9a: 2d00 cmp r5, #0
8003e9c: f000 80bd beq.w 800401a <_dtoa_r+0x622>
8003ea0: b12f cbz r7, 8003eae <_dtoa_r+0x4b6>
8003ea2: 42af cmp r7, r5
8003ea4: d003 beq.n 8003eae <_dtoa_r+0x4b6>
8003ea6: 4639 mov r1, r7
8003ea8: 4648 mov r0, r9
8003eaa: f000 fcb5 bl 8004818 <_Bfree>
8003eae: 4629 mov r1, r5
8003eb0: 4648 mov r0, r9
8003eb2: f000 fcb1 bl 8004818 <_Bfree>
8003eb6: e0b0 b.n 800401a <_dtoa_r+0x622>
8003eb8: 07e2 lsls r2, r4, #31
8003eba: d505 bpl.n 8003ec8 <_dtoa_r+0x4d0>
8003ebc: e9d5 2300 ldrd r2, r3, [r5]
8003ec0: f7fc fba2 bl 8000608 <__aeabi_dmul>
8003ec4: 3601 adds r6, #1
8003ec6: 2301 movs r3, #1
8003ec8: 1064 asrs r4, r4, #1
8003eca: 3508 adds r5, #8
8003ecc: e762 b.n 8003d94 <_dtoa_r+0x39c>
8003ece: 2602 movs r6, #2
8003ed0: e765 b.n 8003d9e <_dtoa_r+0x3a6>
8003ed2: 9c03 ldr r4, [sp, #12]
8003ed4: 46b8 mov r8, r7
8003ed6: e784 b.n 8003de2 <_dtoa_r+0x3ea>
8003ed8: 4b27 ldr r3, [pc, #156] @ (8003f78 <_dtoa_r+0x580>)
8003eda: 9909 ldr r1, [sp, #36] @ 0x24
8003edc: eb03 03c4 add.w r3, r3, r4, lsl #3
8003ee0: e953 2302 ldrd r2, r3, [r3, #-8]
8003ee4: 4454 add r4, sl
8003ee6: 2900 cmp r1, #0
8003ee8: d054 beq.n 8003f94 <_dtoa_r+0x59c>
8003eea: 4929 ldr r1, [pc, #164] @ (8003f90 <_dtoa_r+0x598>)
8003eec: 2000 movs r0, #0
8003eee: f7fc fcb5 bl 800085c <__aeabi_ddiv>
8003ef2: 4633 mov r3, r6
8003ef4: 462a mov r2, r5
8003ef6: f7fc f9cf bl 8000298 <__aeabi_dsub>
8003efa: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
8003efe: 4656 mov r6, sl
8003f00: e9dd 0104 ldrd r0, r1, [sp, #16]
8003f04: f7fc fe30 bl 8000b68 <__aeabi_d2iz>
8003f08: 4605 mov r5, r0
8003f0a: f7fc fb13 bl 8000534 <__aeabi_i2d>
8003f0e: 4602 mov r2, r0
8003f10: 460b mov r3, r1
8003f12: e9dd 0104 ldrd r0, r1, [sp, #16]
8003f16: f7fc f9bf bl 8000298 <__aeabi_dsub>
8003f1a: 3530 adds r5, #48 @ 0x30
8003f1c: 4602 mov r2, r0
8003f1e: 460b mov r3, r1
8003f20: e9cd 2304 strd r2, r3, [sp, #16]
8003f24: f806 5b01 strb.w r5, [r6], #1
8003f28: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
8003f2c: f7fc fdde bl 8000aec <__aeabi_dcmplt>
8003f30: 2800 cmp r0, #0
8003f32: d172 bne.n 800401a <_dtoa_r+0x622>
8003f34: e9dd 2304 ldrd r2, r3, [sp, #16]
8003f38: 4911 ldr r1, [pc, #68] @ (8003f80 <_dtoa_r+0x588>)
8003f3a: 2000 movs r0, #0
8003f3c: f7fc f9ac bl 8000298 <__aeabi_dsub>
8003f40: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
8003f44: f7fc fdd2 bl 8000aec <__aeabi_dcmplt>
8003f48: 2800 cmp r0, #0
8003f4a: f040 80b4 bne.w 80040b6 <_dtoa_r+0x6be>
8003f4e: 42a6 cmp r6, r4
8003f50: f43f af70 beq.w 8003e34 <_dtoa_r+0x43c>
8003f54: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38
8003f58: 4b0a ldr r3, [pc, #40] @ (8003f84 <_dtoa_r+0x58c>)
8003f5a: 2200 movs r2, #0
8003f5c: f7fc fb54 bl 8000608 <__aeabi_dmul>
8003f60: 4b08 ldr r3, [pc, #32] @ (8003f84 <_dtoa_r+0x58c>)
8003f62: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
8003f66: 2200 movs r2, #0
8003f68: e9dd 0104 ldrd r0, r1, [sp, #16]
8003f6c: f7fc fb4c bl 8000608 <__aeabi_dmul>
8003f70: e9cd 0104 strd r0, r1, [sp, #16]
8003f74: e7c4 b.n 8003f00 <_dtoa_r+0x508>
8003f76: bf00 nop
8003f78: 08005830 .word 0x08005830
8003f7c: 08005808 .word 0x08005808
8003f80: 3ff00000 .word 0x3ff00000
8003f84: 40240000 .word 0x40240000
8003f88: 401c0000 .word 0x401c0000
8003f8c: 40140000 .word 0x40140000
8003f90: 3fe00000 .word 0x3fe00000
8003f94: 4631 mov r1, r6
8003f96: 4628 mov r0, r5
8003f98: f7fc fb36 bl 8000608 <__aeabi_dmul>
8003f9c: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
8003fa0: 9413 str r4, [sp, #76] @ 0x4c
8003fa2: 4656 mov r6, sl
8003fa4: e9dd 0104 ldrd r0, r1, [sp, #16]
8003fa8: f7fc fdde bl 8000b68 <__aeabi_d2iz>
8003fac: 4605 mov r5, r0
8003fae: f7fc fac1 bl 8000534 <__aeabi_i2d>
8003fb2: 4602 mov r2, r0
8003fb4: 460b mov r3, r1
8003fb6: e9dd 0104 ldrd r0, r1, [sp, #16]
8003fba: f7fc f96d bl 8000298 <__aeabi_dsub>
8003fbe: 3530 adds r5, #48 @ 0x30
8003fc0: f806 5b01 strb.w r5, [r6], #1
8003fc4: 4602 mov r2, r0
8003fc6: 460b mov r3, r1
8003fc8: 42a6 cmp r6, r4
8003fca: e9cd 2304 strd r2, r3, [sp, #16]
8003fce: f04f 0200 mov.w r2, #0
8003fd2: d124 bne.n 800401e <_dtoa_r+0x626>
8003fd4: 4baf ldr r3, [pc, #700] @ (8004294 <_dtoa_r+0x89c>)
8003fd6: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38
8003fda: f7fc f95f bl 800029c <__adddf3>
8003fde: 4602 mov r2, r0
8003fe0: 460b mov r3, r1
8003fe2: e9dd 0104 ldrd r0, r1, [sp, #16]
8003fe6: f7fc fd9f bl 8000b28 <__aeabi_dcmpgt>
8003fea: 2800 cmp r0, #0
8003fec: d163 bne.n 80040b6 <_dtoa_r+0x6be>
8003fee: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
8003ff2: 49a8 ldr r1, [pc, #672] @ (8004294 <_dtoa_r+0x89c>)
8003ff4: 2000 movs r0, #0
8003ff6: f7fc f94f bl 8000298 <__aeabi_dsub>
8003ffa: 4602 mov r2, r0
8003ffc: 460b mov r3, r1
8003ffe: e9dd 0104 ldrd r0, r1, [sp, #16]
8004002: f7fc fd73 bl 8000aec <__aeabi_dcmplt>
8004006: 2800 cmp r0, #0
8004008: f43f af14 beq.w 8003e34 <_dtoa_r+0x43c>
800400c: 9e13 ldr r6, [sp, #76] @ 0x4c
800400e: 1e73 subs r3, r6, #1
8004010: 9313 str r3, [sp, #76] @ 0x4c
8004012: f816 3c01 ldrb.w r3, [r6, #-1]
8004016: 2b30 cmp r3, #48 @ 0x30
8004018: d0f8 beq.n 800400c <_dtoa_r+0x614>
800401a: 4647 mov r7, r8
800401c: e03b b.n 8004096 <_dtoa_r+0x69e>
800401e: 4b9e ldr r3, [pc, #632] @ (8004298 <_dtoa_r+0x8a0>)
8004020: f7fc faf2 bl 8000608 <__aeabi_dmul>
8004024: e9cd 0104 strd r0, r1, [sp, #16]
8004028: e7bc b.n 8003fa4 <_dtoa_r+0x5ac>
800402a: e9dd 4504 ldrd r4, r5, [sp, #16]
800402e: 4656 mov r6, sl
8004030: e9dd 2300 ldrd r2, r3, [sp]
8004034: 4620 mov r0, r4
8004036: 4629 mov r1, r5
8004038: f7fc fc10 bl 800085c <__aeabi_ddiv>
800403c: f7fc fd94 bl 8000b68 <__aeabi_d2iz>
8004040: 4680 mov r8, r0
8004042: f7fc fa77 bl 8000534 <__aeabi_i2d>
8004046: e9dd 2300 ldrd r2, r3, [sp]
800404a: f7fc fadd bl 8000608 <__aeabi_dmul>
800404e: 4602 mov r2, r0
8004050: 460b mov r3, r1
8004052: 4620 mov r0, r4
8004054: 4629 mov r1, r5
8004056: f108 0430 add.w r4, r8, #48 @ 0x30
800405a: f7fc f91d bl 8000298 <__aeabi_dsub>
800405e: f806 4b01 strb.w r4, [r6], #1
8004062: 9d03 ldr r5, [sp, #12]
8004064: eba6 040a sub.w r4, r6, sl
8004068: 42a5 cmp r5, r4
800406a: 4602 mov r2, r0
800406c: 460b mov r3, r1
800406e: d133 bne.n 80040d8 <_dtoa_r+0x6e0>
8004070: f7fc f914 bl 800029c <__adddf3>
8004074: e9dd 2300 ldrd r2, r3, [sp]
8004078: 4604 mov r4, r0
800407a: 460d mov r5, r1
800407c: f7fc fd54 bl 8000b28 <__aeabi_dcmpgt>
8004080: b9c0 cbnz r0, 80040b4 <_dtoa_r+0x6bc>
8004082: e9dd 2300 ldrd r2, r3, [sp]
8004086: 4620 mov r0, r4
8004088: 4629 mov r1, r5
800408a: f7fc fd25 bl 8000ad8 <__aeabi_dcmpeq>
800408e: b110 cbz r0, 8004096 <_dtoa_r+0x69e>
8004090: f018 0f01 tst.w r8, #1
8004094: d10e bne.n 80040b4 <_dtoa_r+0x6bc>
8004096: 9902 ldr r1, [sp, #8]
8004098: 4648 mov r0, r9
800409a: f000 fbbd bl 8004818 <_Bfree>
800409e: 2300 movs r3, #0
80040a0: 7033 strb r3, [r6, #0]
80040a2: 9b11 ldr r3, [sp, #68] @ 0x44
80040a4: 3701 adds r7, #1
80040a6: 601f str r7, [r3, #0]
80040a8: 9b21 ldr r3, [sp, #132] @ 0x84
80040aa: 2b00 cmp r3, #0
80040ac: f000 824b beq.w 8004546 <_dtoa_r+0xb4e>
80040b0: 601e str r6, [r3, #0]
80040b2: e248 b.n 8004546 <_dtoa_r+0xb4e>
80040b4: 46b8 mov r8, r7
80040b6: 4633 mov r3, r6
80040b8: 461e mov r6, r3
80040ba: f813 2d01 ldrb.w r2, [r3, #-1]!
80040be: 2a39 cmp r2, #57 @ 0x39
80040c0: d106 bne.n 80040d0 <_dtoa_r+0x6d8>
80040c2: 459a cmp sl, r3
80040c4: d1f8 bne.n 80040b8 <_dtoa_r+0x6c0>
80040c6: 2230 movs r2, #48 @ 0x30
80040c8: f108 0801 add.w r8, r8, #1
80040cc: f88a 2000 strb.w r2, [sl]
80040d0: 781a ldrb r2, [r3, #0]
80040d2: 3201 adds r2, #1
80040d4: 701a strb r2, [r3, #0]
80040d6: e7a0 b.n 800401a <_dtoa_r+0x622>
80040d8: 4b6f ldr r3, [pc, #444] @ (8004298 <_dtoa_r+0x8a0>)
80040da: 2200 movs r2, #0
80040dc: f7fc fa94 bl 8000608 <__aeabi_dmul>
80040e0: 2200 movs r2, #0
80040e2: 2300 movs r3, #0
80040e4: 4604 mov r4, r0
80040e6: 460d mov r5, r1
80040e8: f7fc fcf6 bl 8000ad8 <__aeabi_dcmpeq>
80040ec: 2800 cmp r0, #0
80040ee: d09f beq.n 8004030 <_dtoa_r+0x638>
80040f0: e7d1 b.n 8004096 <_dtoa_r+0x69e>
80040f2: 9a09 ldr r2, [sp, #36] @ 0x24
80040f4: 2a00 cmp r2, #0
80040f6: f000 80ea beq.w 80042ce <_dtoa_r+0x8d6>
80040fa: 9a07 ldr r2, [sp, #28]
80040fc: 2a01 cmp r2, #1
80040fe: f300 80cd bgt.w 800429c <_dtoa_r+0x8a4>
8004102: 9a12 ldr r2, [sp, #72] @ 0x48
8004104: 2a00 cmp r2, #0
8004106: f000 80c1 beq.w 800428c <_dtoa_r+0x894>
800410a: f203 4333 addw r3, r3, #1075 @ 0x433
800410e: 9c08 ldr r4, [sp, #32]
8004110: 9e00 ldr r6, [sp, #0]
8004112: 9a00 ldr r2, [sp, #0]
8004114: 441a add r2, r3
8004116: 9200 str r2, [sp, #0]
8004118: 9a06 ldr r2, [sp, #24]
800411a: 2101 movs r1, #1
800411c: 441a add r2, r3
800411e: 4648 mov r0, r9
8004120: 9206 str r2, [sp, #24]
8004122: f000 fc2d bl 8004980 <__i2b>
8004126: 4605 mov r5, r0
8004128: b166 cbz r6, 8004144 <_dtoa_r+0x74c>
800412a: 9b06 ldr r3, [sp, #24]
800412c: 2b00 cmp r3, #0
800412e: dd09 ble.n 8004144 <_dtoa_r+0x74c>
8004130: 42b3 cmp r3, r6
8004132: 9a00 ldr r2, [sp, #0]
8004134: bfa8 it ge
8004136: 4633 movge r3, r6
8004138: 1ad2 subs r2, r2, r3
800413a: 9200 str r2, [sp, #0]
800413c: 9a06 ldr r2, [sp, #24]
800413e: 1af6 subs r6, r6, r3
8004140: 1ad3 subs r3, r2, r3
8004142: 9306 str r3, [sp, #24]
8004144: 9b08 ldr r3, [sp, #32]
8004146: b30b cbz r3, 800418c <_dtoa_r+0x794>
8004148: 9b09 ldr r3, [sp, #36] @ 0x24
800414a: 2b00 cmp r3, #0
800414c: f000 80c6 beq.w 80042dc <_dtoa_r+0x8e4>
8004150: 2c00 cmp r4, #0
8004152: f000 80c0 beq.w 80042d6 <_dtoa_r+0x8de>
8004156: 4629 mov r1, r5
8004158: 4622 mov r2, r4
800415a: 4648 mov r0, r9
800415c: f000 fcc8 bl 8004af0 <__pow5mult>
8004160: 9a02 ldr r2, [sp, #8]
8004162: 4601 mov r1, r0
8004164: 4605 mov r5, r0
8004166: 4648 mov r0, r9
8004168: f000 fc20 bl 80049ac <__multiply>
800416c: 9902 ldr r1, [sp, #8]
800416e: 4680 mov r8, r0
8004170: 4648 mov r0, r9
8004172: f000 fb51 bl 8004818 <_Bfree>
8004176: 9b08 ldr r3, [sp, #32]
8004178: 1b1b subs r3, r3, r4
800417a: 9308 str r3, [sp, #32]
800417c: f000 80b1 beq.w 80042e2 <_dtoa_r+0x8ea>
8004180: 9a08 ldr r2, [sp, #32]
8004182: 4641 mov r1, r8
8004184: 4648 mov r0, r9
8004186: f000 fcb3 bl 8004af0 <__pow5mult>
800418a: 9002 str r0, [sp, #8]
800418c: 2101 movs r1, #1
800418e: 4648 mov r0, r9
8004190: f000 fbf6 bl 8004980 <__i2b>
8004194: 9b0d ldr r3, [sp, #52] @ 0x34
8004196: 4604 mov r4, r0
8004198: 2b00 cmp r3, #0
800419a: f000 81d8 beq.w 800454e <_dtoa_r+0xb56>
800419e: 461a mov r2, r3
80041a0: 4601 mov r1, r0
80041a2: 4648 mov r0, r9
80041a4: f000 fca4 bl 8004af0 <__pow5mult>
80041a8: 9b07 ldr r3, [sp, #28]
80041aa: 2b01 cmp r3, #1
80041ac: 4604 mov r4, r0
80041ae: f300 809f bgt.w 80042f0 <_dtoa_r+0x8f8>
80041b2: 9b04 ldr r3, [sp, #16]
80041b4: 2b00 cmp r3, #0
80041b6: f040 8097 bne.w 80042e8 <_dtoa_r+0x8f0>
80041ba: 9b05 ldr r3, [sp, #20]
80041bc: f3c3 0313 ubfx r3, r3, #0, #20
80041c0: 2b00 cmp r3, #0
80041c2: f040 8093 bne.w 80042ec <_dtoa_r+0x8f4>
80041c6: 9b05 ldr r3, [sp, #20]
80041c8: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
80041cc: 0d1b lsrs r3, r3, #20
80041ce: 051b lsls r3, r3, #20
80041d0: b133 cbz r3, 80041e0 <_dtoa_r+0x7e8>
80041d2: 9b00 ldr r3, [sp, #0]
80041d4: 3301 adds r3, #1
80041d6: 9300 str r3, [sp, #0]
80041d8: 9b06 ldr r3, [sp, #24]
80041da: 3301 adds r3, #1
80041dc: 9306 str r3, [sp, #24]
80041de: 2301 movs r3, #1
80041e0: 9308 str r3, [sp, #32]
80041e2: 9b0d ldr r3, [sp, #52] @ 0x34
80041e4: 2b00 cmp r3, #0
80041e6: f000 81b8 beq.w 800455a <_dtoa_r+0xb62>
80041ea: 6923 ldr r3, [r4, #16]
80041ec: eb04 0383 add.w r3, r4, r3, lsl #2
80041f0: 6918 ldr r0, [r3, #16]
80041f2: f000 fb79 bl 80048e8 <__hi0bits>
80041f6: f1c0 0020 rsb r0, r0, #32
80041fa: 9b06 ldr r3, [sp, #24]
80041fc: 4418 add r0, r3
80041fe: f010 001f ands.w r0, r0, #31
8004202: f000 8082 beq.w 800430a <_dtoa_r+0x912>
8004206: f1c0 0320 rsb r3, r0, #32
800420a: 2b04 cmp r3, #4
800420c: dd73 ble.n 80042f6 <_dtoa_r+0x8fe>
800420e: 9b00 ldr r3, [sp, #0]
8004210: f1c0 001c rsb r0, r0, #28
8004214: 4403 add r3, r0
8004216: 9300 str r3, [sp, #0]
8004218: 9b06 ldr r3, [sp, #24]
800421a: 4403 add r3, r0
800421c: 4406 add r6, r0
800421e: 9306 str r3, [sp, #24]
8004220: 9b00 ldr r3, [sp, #0]
8004222: 2b00 cmp r3, #0
8004224: dd05 ble.n 8004232 <_dtoa_r+0x83a>
8004226: 9902 ldr r1, [sp, #8]
8004228: 461a mov r2, r3
800422a: 4648 mov r0, r9
800422c: f000 fcba bl 8004ba4 <__lshift>
8004230: 9002 str r0, [sp, #8]
8004232: 9b06 ldr r3, [sp, #24]
8004234: 2b00 cmp r3, #0
8004236: dd05 ble.n 8004244 <_dtoa_r+0x84c>
8004238: 4621 mov r1, r4
800423a: 461a mov r2, r3
800423c: 4648 mov r0, r9
800423e: f000 fcb1 bl 8004ba4 <__lshift>
8004242: 4604 mov r4, r0
8004244: 9b10 ldr r3, [sp, #64] @ 0x40
8004246: 2b00 cmp r3, #0
8004248: d061 beq.n 800430e <_dtoa_r+0x916>
800424a: 9802 ldr r0, [sp, #8]
800424c: 4621 mov r1, r4
800424e: f000 fd15 bl 8004c7c <__mcmp>
8004252: 2800 cmp r0, #0
8004254: da5b bge.n 800430e <_dtoa_r+0x916>
8004256: 2300 movs r3, #0
8004258: 9902 ldr r1, [sp, #8]
800425a: 220a movs r2, #10
800425c: 4648 mov r0, r9
800425e: f000 fafd bl 800485c <__multadd>
8004262: 9b09 ldr r3, [sp, #36] @ 0x24
8004264: 9002 str r0, [sp, #8]
8004266: f107 38ff add.w r8, r7, #4294967295
800426a: 2b00 cmp r3, #0
800426c: f000 8177 beq.w 800455e <_dtoa_r+0xb66>
8004270: 4629 mov r1, r5
8004272: 2300 movs r3, #0
8004274: 220a movs r2, #10
8004276: 4648 mov r0, r9
8004278: f000 faf0 bl 800485c <__multadd>
800427c: f1bb 0f00 cmp.w fp, #0
8004280: 4605 mov r5, r0
8004282: dc6f bgt.n 8004364 <_dtoa_r+0x96c>
8004284: 9b07 ldr r3, [sp, #28]
8004286: 2b02 cmp r3, #2
8004288: dc49 bgt.n 800431e <_dtoa_r+0x926>
800428a: e06b b.n 8004364 <_dtoa_r+0x96c>
800428c: 9b14 ldr r3, [sp, #80] @ 0x50
800428e: f1c3 0336 rsb r3, r3, #54 @ 0x36
8004292: e73c b.n 800410e <_dtoa_r+0x716>
8004294: 3fe00000 .word 0x3fe00000
8004298: 40240000 .word 0x40240000
800429c: 9b03 ldr r3, [sp, #12]
800429e: 1e5c subs r4, r3, #1
80042a0: 9b08 ldr r3, [sp, #32]
80042a2: 42a3 cmp r3, r4
80042a4: db09 blt.n 80042ba <_dtoa_r+0x8c2>
80042a6: 1b1c subs r4, r3, r4
80042a8: 9b03 ldr r3, [sp, #12]
80042aa: 2b00 cmp r3, #0
80042ac: f6bf af30 bge.w 8004110 <_dtoa_r+0x718>
80042b0: 9b00 ldr r3, [sp, #0]
80042b2: 9a03 ldr r2, [sp, #12]
80042b4: 1a9e subs r6, r3, r2
80042b6: 2300 movs r3, #0
80042b8: e72b b.n 8004112 <_dtoa_r+0x71a>
80042ba: 9b08 ldr r3, [sp, #32]
80042bc: 9a0d ldr r2, [sp, #52] @ 0x34
80042be: 9408 str r4, [sp, #32]
80042c0: 1ae3 subs r3, r4, r3
80042c2: 441a add r2, r3
80042c4: 9e00 ldr r6, [sp, #0]
80042c6: 9b03 ldr r3, [sp, #12]
80042c8: 920d str r2, [sp, #52] @ 0x34
80042ca: 2400 movs r4, #0
80042cc: e721 b.n 8004112 <_dtoa_r+0x71a>
80042ce: 9c08 ldr r4, [sp, #32]
80042d0: 9e00 ldr r6, [sp, #0]
80042d2: 9d09 ldr r5, [sp, #36] @ 0x24
80042d4: e728 b.n 8004128 <_dtoa_r+0x730>
80042d6: f8dd 8008 ldr.w r8, [sp, #8]
80042da: e751 b.n 8004180 <_dtoa_r+0x788>
80042dc: 9a08 ldr r2, [sp, #32]
80042de: 9902 ldr r1, [sp, #8]
80042e0: e750 b.n 8004184 <_dtoa_r+0x78c>
80042e2: f8cd 8008 str.w r8, [sp, #8]
80042e6: e751 b.n 800418c <_dtoa_r+0x794>
80042e8: 2300 movs r3, #0
80042ea: e779 b.n 80041e0 <_dtoa_r+0x7e8>
80042ec: 9b04 ldr r3, [sp, #16]
80042ee: e777 b.n 80041e0 <_dtoa_r+0x7e8>
80042f0: 2300 movs r3, #0
80042f2: 9308 str r3, [sp, #32]
80042f4: e779 b.n 80041ea <_dtoa_r+0x7f2>
80042f6: d093 beq.n 8004220 <_dtoa_r+0x828>
80042f8: 9a00 ldr r2, [sp, #0]
80042fa: 331c adds r3, #28
80042fc: 441a add r2, r3
80042fe: 9200 str r2, [sp, #0]
8004300: 9a06 ldr r2, [sp, #24]
8004302: 441a add r2, r3
8004304: 441e add r6, r3
8004306: 9206 str r2, [sp, #24]
8004308: e78a b.n 8004220 <_dtoa_r+0x828>
800430a: 4603 mov r3, r0
800430c: e7f4 b.n 80042f8 <_dtoa_r+0x900>
800430e: 9b03 ldr r3, [sp, #12]
8004310: 2b00 cmp r3, #0
8004312: 46b8 mov r8, r7
8004314: dc20 bgt.n 8004358 <_dtoa_r+0x960>
8004316: 469b mov fp, r3
8004318: 9b07 ldr r3, [sp, #28]
800431a: 2b02 cmp r3, #2
800431c: dd1e ble.n 800435c <_dtoa_r+0x964>
800431e: f1bb 0f00 cmp.w fp, #0
8004322: f47f adb1 bne.w 8003e88 <_dtoa_r+0x490>
8004326: 4621 mov r1, r4
8004328: 465b mov r3, fp
800432a: 2205 movs r2, #5
800432c: 4648 mov r0, r9
800432e: f000 fa95 bl 800485c <__multadd>
8004332: 4601 mov r1, r0
8004334: 4604 mov r4, r0
8004336: 9802 ldr r0, [sp, #8]
8004338: f000 fca0 bl 8004c7c <__mcmp>
800433c: 2800 cmp r0, #0
800433e: f77f ada3 ble.w 8003e88 <_dtoa_r+0x490>
8004342: 4656 mov r6, sl
8004344: 2331 movs r3, #49 @ 0x31
8004346: f806 3b01 strb.w r3, [r6], #1
800434a: f108 0801 add.w r8, r8, #1
800434e: e59f b.n 8003e90 <_dtoa_r+0x498>
8004350: 9c03 ldr r4, [sp, #12]
8004352: 46b8 mov r8, r7
8004354: 4625 mov r5, r4
8004356: e7f4 b.n 8004342 <_dtoa_r+0x94a>
8004358: f8dd b00c ldr.w fp, [sp, #12]
800435c: 9b09 ldr r3, [sp, #36] @ 0x24
800435e: 2b00 cmp r3, #0
8004360: f000 8101 beq.w 8004566 <_dtoa_r+0xb6e>
8004364: 2e00 cmp r6, #0
8004366: dd05 ble.n 8004374 <_dtoa_r+0x97c>
8004368: 4629 mov r1, r5
800436a: 4632 mov r2, r6
800436c: 4648 mov r0, r9
800436e: f000 fc19 bl 8004ba4 <__lshift>
8004372: 4605 mov r5, r0
8004374: 9b08 ldr r3, [sp, #32]
8004376: 2b00 cmp r3, #0
8004378: d05c beq.n 8004434 <_dtoa_r+0xa3c>
800437a: 6869 ldr r1, [r5, #4]
800437c: 4648 mov r0, r9
800437e: f000 fa0b bl 8004798 <_Balloc>
8004382: 4606 mov r6, r0
8004384: b928 cbnz r0, 8004392 <_dtoa_r+0x99a>
8004386: 4b82 ldr r3, [pc, #520] @ (8004590 <_dtoa_r+0xb98>)
8004388: 4602 mov r2, r0
800438a: f240 21ef movw r1, #751 @ 0x2ef
800438e: f7ff bb4a b.w 8003a26 <_dtoa_r+0x2e>
8004392: 692a ldr r2, [r5, #16]
8004394: 3202 adds r2, #2
8004396: 0092 lsls r2, r2, #2
8004398: f105 010c add.w r1, r5, #12
800439c: 300c adds r0, #12
800439e: f000 fe31 bl 8005004 <memcpy>
80043a2: 2201 movs r2, #1
80043a4: 4631 mov r1, r6
80043a6: 4648 mov r0, r9
80043a8: f000 fbfc bl 8004ba4 <__lshift>
80043ac: f10a 0301 add.w r3, sl, #1
80043b0: 9300 str r3, [sp, #0]
80043b2: eb0a 030b add.w r3, sl, fp
80043b6: 9308 str r3, [sp, #32]
80043b8: 9b04 ldr r3, [sp, #16]
80043ba: f003 0301 and.w r3, r3, #1
80043be: 462f mov r7, r5
80043c0: 9306 str r3, [sp, #24]
80043c2: 4605 mov r5, r0
80043c4: 9b00 ldr r3, [sp, #0]
80043c6: 9802 ldr r0, [sp, #8]
80043c8: 4621 mov r1, r4
80043ca: f103 3bff add.w fp, r3, #4294967295
80043ce: f7ff fa88 bl 80038e2 <quorem>
80043d2: 4603 mov r3, r0
80043d4: 3330 adds r3, #48 @ 0x30
80043d6: 9003 str r0, [sp, #12]
80043d8: 4639 mov r1, r7
80043da: 9802 ldr r0, [sp, #8]
80043dc: 9309 str r3, [sp, #36] @ 0x24
80043de: f000 fc4d bl 8004c7c <__mcmp>
80043e2: 462a mov r2, r5
80043e4: 9004 str r0, [sp, #16]
80043e6: 4621 mov r1, r4
80043e8: 4648 mov r0, r9
80043ea: f000 fc63 bl 8004cb4 <__mdiff>
80043ee: 68c2 ldr r2, [r0, #12]
80043f0: 9b09 ldr r3, [sp, #36] @ 0x24
80043f2: 4606 mov r6, r0
80043f4: bb02 cbnz r2, 8004438 <_dtoa_r+0xa40>
80043f6: 4601 mov r1, r0
80043f8: 9802 ldr r0, [sp, #8]
80043fa: f000 fc3f bl 8004c7c <__mcmp>
80043fe: 9b09 ldr r3, [sp, #36] @ 0x24
8004400: 4602 mov r2, r0
8004402: 4631 mov r1, r6
8004404: 4648 mov r0, r9
8004406: 920c str r2, [sp, #48] @ 0x30
8004408: 9309 str r3, [sp, #36] @ 0x24
800440a: f000 fa05 bl 8004818 <_Bfree>
800440e: 9b07 ldr r3, [sp, #28]
8004410: 9a0c ldr r2, [sp, #48] @ 0x30
8004412: 9e00 ldr r6, [sp, #0]
8004414: ea42 0103 orr.w r1, r2, r3
8004418: 9b06 ldr r3, [sp, #24]
800441a: 4319 orrs r1, r3
800441c: 9b09 ldr r3, [sp, #36] @ 0x24
800441e: d10d bne.n 800443c <_dtoa_r+0xa44>
8004420: 2b39 cmp r3, #57 @ 0x39
8004422: d027 beq.n 8004474 <_dtoa_r+0xa7c>
8004424: 9a04 ldr r2, [sp, #16]
8004426: 2a00 cmp r2, #0
8004428: dd01 ble.n 800442e <_dtoa_r+0xa36>
800442a: 9b03 ldr r3, [sp, #12]
800442c: 3331 adds r3, #49 @ 0x31
800442e: f88b 3000 strb.w r3, [fp]
8004432: e52e b.n 8003e92 <_dtoa_r+0x49a>
8004434: 4628 mov r0, r5
8004436: e7b9 b.n 80043ac <_dtoa_r+0x9b4>
8004438: 2201 movs r2, #1
800443a: e7e2 b.n 8004402 <_dtoa_r+0xa0a>
800443c: 9904 ldr r1, [sp, #16]
800443e: 2900 cmp r1, #0
8004440: db04 blt.n 800444c <_dtoa_r+0xa54>
8004442: 9807 ldr r0, [sp, #28]
8004444: 4301 orrs r1, r0
8004446: 9806 ldr r0, [sp, #24]
8004448: 4301 orrs r1, r0
800444a: d120 bne.n 800448e <_dtoa_r+0xa96>
800444c: 2a00 cmp r2, #0
800444e: ddee ble.n 800442e <_dtoa_r+0xa36>
8004450: 9902 ldr r1, [sp, #8]
8004452: 9300 str r3, [sp, #0]
8004454: 2201 movs r2, #1
8004456: 4648 mov r0, r9
8004458: f000 fba4 bl 8004ba4 <__lshift>
800445c: 4621 mov r1, r4
800445e: 9002 str r0, [sp, #8]
8004460: f000 fc0c bl 8004c7c <__mcmp>
8004464: 2800 cmp r0, #0
8004466: 9b00 ldr r3, [sp, #0]
8004468: dc02 bgt.n 8004470 <_dtoa_r+0xa78>
800446a: d1e0 bne.n 800442e <_dtoa_r+0xa36>
800446c: 07da lsls r2, r3, #31
800446e: d5de bpl.n 800442e <_dtoa_r+0xa36>
8004470: 2b39 cmp r3, #57 @ 0x39
8004472: d1da bne.n 800442a <_dtoa_r+0xa32>
8004474: 2339 movs r3, #57 @ 0x39
8004476: f88b 3000 strb.w r3, [fp]
800447a: 4633 mov r3, r6
800447c: 461e mov r6, r3
800447e: 3b01 subs r3, #1
8004480: f816 2c01 ldrb.w r2, [r6, #-1]
8004484: 2a39 cmp r2, #57 @ 0x39
8004486: d04e beq.n 8004526 <_dtoa_r+0xb2e>
8004488: 3201 adds r2, #1
800448a: 701a strb r2, [r3, #0]
800448c: e501 b.n 8003e92 <_dtoa_r+0x49a>
800448e: 2a00 cmp r2, #0
8004490: dd03 ble.n 800449a <_dtoa_r+0xaa2>
8004492: 2b39 cmp r3, #57 @ 0x39
8004494: d0ee beq.n 8004474 <_dtoa_r+0xa7c>
8004496: 3301 adds r3, #1
8004498: e7c9 b.n 800442e <_dtoa_r+0xa36>
800449a: 9a00 ldr r2, [sp, #0]
800449c: 9908 ldr r1, [sp, #32]
800449e: f802 3c01 strb.w r3, [r2, #-1]
80044a2: 428a cmp r2, r1
80044a4: d028 beq.n 80044f8 <_dtoa_r+0xb00>
80044a6: 9902 ldr r1, [sp, #8]
80044a8: 2300 movs r3, #0
80044aa: 220a movs r2, #10
80044ac: 4648 mov r0, r9
80044ae: f000 f9d5 bl 800485c <__multadd>
80044b2: 42af cmp r7, r5
80044b4: 9002 str r0, [sp, #8]
80044b6: f04f 0300 mov.w r3, #0
80044ba: f04f 020a mov.w r2, #10
80044be: 4639 mov r1, r7
80044c0: 4648 mov r0, r9
80044c2: d107 bne.n 80044d4 <_dtoa_r+0xadc>
80044c4: f000 f9ca bl 800485c <__multadd>
80044c8: 4607 mov r7, r0
80044ca: 4605 mov r5, r0
80044cc: 9b00 ldr r3, [sp, #0]
80044ce: 3301 adds r3, #1
80044d0: 9300 str r3, [sp, #0]
80044d2: e777 b.n 80043c4 <_dtoa_r+0x9cc>
80044d4: f000 f9c2 bl 800485c <__multadd>
80044d8: 4629 mov r1, r5
80044da: 4607 mov r7, r0
80044dc: 2300 movs r3, #0
80044de: 220a movs r2, #10
80044e0: 4648 mov r0, r9
80044e2: f000 f9bb bl 800485c <__multadd>
80044e6: 4605 mov r5, r0
80044e8: e7f0 b.n 80044cc <_dtoa_r+0xad4>
80044ea: f1bb 0f00 cmp.w fp, #0
80044ee: bfcc ite gt
80044f0: 465e movgt r6, fp
80044f2: 2601 movle r6, #1
80044f4: 4456 add r6, sl
80044f6: 2700 movs r7, #0
80044f8: 9902 ldr r1, [sp, #8]
80044fa: 9300 str r3, [sp, #0]
80044fc: 2201 movs r2, #1
80044fe: 4648 mov r0, r9
8004500: f000 fb50 bl 8004ba4 <__lshift>
8004504: 4621 mov r1, r4
8004506: 9002 str r0, [sp, #8]
8004508: f000 fbb8 bl 8004c7c <__mcmp>
800450c: 2800 cmp r0, #0
800450e: dcb4 bgt.n 800447a <_dtoa_r+0xa82>
8004510: d102 bne.n 8004518 <_dtoa_r+0xb20>
8004512: 9b00 ldr r3, [sp, #0]
8004514: 07db lsls r3, r3, #31
8004516: d4b0 bmi.n 800447a <_dtoa_r+0xa82>
8004518: 4633 mov r3, r6
800451a: 461e mov r6, r3
800451c: f813 2d01 ldrb.w r2, [r3, #-1]!
8004520: 2a30 cmp r2, #48 @ 0x30
8004522: d0fa beq.n 800451a <_dtoa_r+0xb22>
8004524: e4b5 b.n 8003e92 <_dtoa_r+0x49a>
8004526: 459a cmp sl, r3
8004528: d1a8 bne.n 800447c <_dtoa_r+0xa84>
800452a: 2331 movs r3, #49 @ 0x31
800452c: f108 0801 add.w r8, r8, #1
8004530: f88a 3000 strb.w r3, [sl]
8004534: e4ad b.n 8003e92 <_dtoa_r+0x49a>
8004536: 9b21 ldr r3, [sp, #132] @ 0x84
8004538: f8df a058 ldr.w sl, [pc, #88] @ 8004594 <_dtoa_r+0xb9c>
800453c: b11b cbz r3, 8004546 <_dtoa_r+0xb4e>
800453e: f10a 0308 add.w r3, sl, #8
8004542: 9a21 ldr r2, [sp, #132] @ 0x84
8004544: 6013 str r3, [r2, #0]
8004546: 4650 mov r0, sl
8004548: b017 add sp, #92 @ 0x5c
800454a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
800454e: 9b07 ldr r3, [sp, #28]
8004550: 2b01 cmp r3, #1
8004552: f77f ae2e ble.w 80041b2 <_dtoa_r+0x7ba>
8004556: 9b0d ldr r3, [sp, #52] @ 0x34
8004558: 9308 str r3, [sp, #32]
800455a: 2001 movs r0, #1
800455c: e64d b.n 80041fa <_dtoa_r+0x802>
800455e: f1bb 0f00 cmp.w fp, #0
8004562: f77f aed9 ble.w 8004318 <_dtoa_r+0x920>
8004566: 4656 mov r6, sl
8004568: 9802 ldr r0, [sp, #8]
800456a: 4621 mov r1, r4
800456c: f7ff f9b9 bl 80038e2 <quorem>
8004570: f100 0330 add.w r3, r0, #48 @ 0x30
8004574: f806 3b01 strb.w r3, [r6], #1
8004578: eba6 020a sub.w r2, r6, sl
800457c: 4593 cmp fp, r2
800457e: ddb4 ble.n 80044ea <_dtoa_r+0xaf2>
8004580: 9902 ldr r1, [sp, #8]
8004582: 2300 movs r3, #0
8004584: 220a movs r2, #10
8004586: 4648 mov r0, r9
8004588: f000 f968 bl 800485c <__multadd>
800458c: 9002 str r0, [sp, #8]
800458e: e7eb b.n 8004568 <_dtoa_r+0xb70>
8004590: 08005738 .word 0x08005738
8004594: 080056bc .word 0x080056bc
08004598 <_free_r>:
8004598: b538 push {r3, r4, r5, lr}
800459a: 4605 mov r5, r0
800459c: 2900 cmp r1, #0
800459e: d041 beq.n 8004624 <_free_r+0x8c>
80045a0: f851 3c04 ldr.w r3, [r1, #-4]
80045a4: 1f0c subs r4, r1, #4
80045a6: 2b00 cmp r3, #0
80045a8: bfb8 it lt
80045aa: 18e4 addlt r4, r4, r3
80045ac: f000 f8e8 bl 8004780 <__malloc_lock>
80045b0: 4a1d ldr r2, [pc, #116] @ (8004628 <_free_r+0x90>)
80045b2: 6813 ldr r3, [r2, #0]
80045b4: b933 cbnz r3, 80045c4 <_free_r+0x2c>
80045b6: 6063 str r3, [r4, #4]
80045b8: 6014 str r4, [r2, #0]
80045ba: 4628 mov r0, r5
80045bc: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
80045c0: f000 b8e4 b.w 800478c <__malloc_unlock>
80045c4: 42a3 cmp r3, r4
80045c6: d908 bls.n 80045da <_free_r+0x42>
80045c8: 6820 ldr r0, [r4, #0]
80045ca: 1821 adds r1, r4, r0
80045cc: 428b cmp r3, r1
80045ce: bf01 itttt eq
80045d0: 6819 ldreq r1, [r3, #0]
80045d2: 685b ldreq r3, [r3, #4]
80045d4: 1809 addeq r1, r1, r0
80045d6: 6021 streq r1, [r4, #0]
80045d8: e7ed b.n 80045b6 <_free_r+0x1e>
80045da: 461a mov r2, r3
80045dc: 685b ldr r3, [r3, #4]
80045de: b10b cbz r3, 80045e4 <_free_r+0x4c>
80045e0: 42a3 cmp r3, r4
80045e2: d9fa bls.n 80045da <_free_r+0x42>
80045e4: 6811 ldr r1, [r2, #0]
80045e6: 1850 adds r0, r2, r1
80045e8: 42a0 cmp r0, r4
80045ea: d10b bne.n 8004604 <_free_r+0x6c>
80045ec: 6820 ldr r0, [r4, #0]
80045ee: 4401 add r1, r0
80045f0: 1850 adds r0, r2, r1
80045f2: 4283 cmp r3, r0
80045f4: 6011 str r1, [r2, #0]
80045f6: d1e0 bne.n 80045ba <_free_r+0x22>
80045f8: 6818 ldr r0, [r3, #0]
80045fa: 685b ldr r3, [r3, #4]
80045fc: 6053 str r3, [r2, #4]
80045fe: 4408 add r0, r1
8004600: 6010 str r0, [r2, #0]
8004602: e7da b.n 80045ba <_free_r+0x22>
8004604: d902 bls.n 800460c <_free_r+0x74>
8004606: 230c movs r3, #12
8004608: 602b str r3, [r5, #0]
800460a: e7d6 b.n 80045ba <_free_r+0x22>
800460c: 6820 ldr r0, [r4, #0]
800460e: 1821 adds r1, r4, r0
8004610: 428b cmp r3, r1
8004612: bf04 itt eq
8004614: 6819 ldreq r1, [r3, #0]
8004616: 685b ldreq r3, [r3, #4]
8004618: 6063 str r3, [r4, #4]
800461a: bf04 itt eq
800461c: 1809 addeq r1, r1, r0
800461e: 6021 streq r1, [r4, #0]
8004620: 6054 str r4, [r2, #4]
8004622: e7ca b.n 80045ba <_free_r+0x22>
8004624: bd38 pop {r3, r4, r5, pc}
8004626: bf00 nop
8004628: 200007a8 .word 0x200007a8
0800462c <malloc>:
800462c: 4b02 ldr r3, [pc, #8] @ (8004638 <malloc+0xc>)
800462e: 4601 mov r1, r0
8004630: 6818 ldr r0, [r3, #0]
8004632: f000 b825 b.w 8004680 <_malloc_r>
8004636: bf00 nop
8004638: 20000018 .word 0x20000018
0800463c <sbrk_aligned>:
800463c: b570 push {r4, r5, r6, lr}
800463e: 4e0f ldr r6, [pc, #60] @ (800467c <sbrk_aligned+0x40>)
8004640: 460c mov r4, r1
8004642: 6831 ldr r1, [r6, #0]
8004644: 4605 mov r5, r0
8004646: b911 cbnz r1, 800464e <sbrk_aligned+0x12>
8004648: f000 fccc bl 8004fe4 <_sbrk_r>
800464c: 6030 str r0, [r6, #0]
800464e: 4621 mov r1, r4
8004650: 4628 mov r0, r5
8004652: f000 fcc7 bl 8004fe4 <_sbrk_r>
8004656: 1c43 adds r3, r0, #1
8004658: d103 bne.n 8004662 <sbrk_aligned+0x26>
800465a: f04f 34ff mov.w r4, #4294967295
800465e: 4620 mov r0, r4
8004660: bd70 pop {r4, r5, r6, pc}
8004662: 1cc4 adds r4, r0, #3
8004664: f024 0403 bic.w r4, r4, #3
8004668: 42a0 cmp r0, r4
800466a: d0f8 beq.n 800465e <sbrk_aligned+0x22>
800466c: 1a21 subs r1, r4, r0
800466e: 4628 mov r0, r5
8004670: f000 fcb8 bl 8004fe4 <_sbrk_r>
8004674: 3001 adds r0, #1
8004676: d1f2 bne.n 800465e <sbrk_aligned+0x22>
8004678: e7ef b.n 800465a <sbrk_aligned+0x1e>
800467a: bf00 nop
800467c: 200007a4 .word 0x200007a4
08004680 <_malloc_r>:
8004680: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
8004684: 1ccd adds r5, r1, #3
8004686: f025 0503 bic.w r5, r5, #3
800468a: 3508 adds r5, #8
800468c: 2d0c cmp r5, #12
800468e: bf38 it cc
8004690: 250c movcc r5, #12
8004692: 2d00 cmp r5, #0
8004694: 4606 mov r6, r0
8004696: db01 blt.n 800469c <_malloc_r+0x1c>
8004698: 42a9 cmp r1, r5
800469a: d904 bls.n 80046a6 <_malloc_r+0x26>
800469c: 230c movs r3, #12
800469e: 6033 str r3, [r6, #0]
80046a0: 2000 movs r0, #0
80046a2: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
80046a6: f8df 80d4 ldr.w r8, [pc, #212] @ 800477c <_malloc_r+0xfc>
80046aa: f000 f869 bl 8004780 <__malloc_lock>
80046ae: f8d8 3000 ldr.w r3, [r8]
80046b2: 461c mov r4, r3
80046b4: bb44 cbnz r4, 8004708 <_malloc_r+0x88>
80046b6: 4629 mov r1, r5
80046b8: 4630 mov r0, r6
80046ba: f7ff ffbf bl 800463c <sbrk_aligned>
80046be: 1c43 adds r3, r0, #1
80046c0: 4604 mov r4, r0
80046c2: d158 bne.n 8004776 <_malloc_r+0xf6>
80046c4: f8d8 4000 ldr.w r4, [r8]
80046c8: 4627 mov r7, r4
80046ca: 2f00 cmp r7, #0
80046cc: d143 bne.n 8004756 <_malloc_r+0xd6>
80046ce: 2c00 cmp r4, #0
80046d0: d04b beq.n 800476a <_malloc_r+0xea>
80046d2: 6823 ldr r3, [r4, #0]
80046d4: 4639 mov r1, r7
80046d6: 4630 mov r0, r6
80046d8: eb04 0903 add.w r9, r4, r3
80046dc: f000 fc82 bl 8004fe4 <_sbrk_r>
80046e0: 4581 cmp r9, r0
80046e2: d142 bne.n 800476a <_malloc_r+0xea>
80046e4: 6821 ldr r1, [r4, #0]
80046e6: 1a6d subs r5, r5, r1
80046e8: 4629 mov r1, r5
80046ea: 4630 mov r0, r6
80046ec: f7ff ffa6 bl 800463c <sbrk_aligned>
80046f0: 3001 adds r0, #1
80046f2: d03a beq.n 800476a <_malloc_r+0xea>
80046f4: 6823 ldr r3, [r4, #0]
80046f6: 442b add r3, r5
80046f8: 6023 str r3, [r4, #0]
80046fa: f8d8 3000 ldr.w r3, [r8]
80046fe: 685a ldr r2, [r3, #4]
8004700: bb62 cbnz r2, 800475c <_malloc_r+0xdc>
8004702: f8c8 7000 str.w r7, [r8]
8004706: e00f b.n 8004728 <_malloc_r+0xa8>
8004708: 6822 ldr r2, [r4, #0]
800470a: 1b52 subs r2, r2, r5
800470c: d420 bmi.n 8004750 <_malloc_r+0xd0>
800470e: 2a0b cmp r2, #11
8004710: d917 bls.n 8004742 <_malloc_r+0xc2>
8004712: 1961 adds r1, r4, r5
8004714: 42a3 cmp r3, r4
8004716: 6025 str r5, [r4, #0]
8004718: bf18 it ne
800471a: 6059 strne r1, [r3, #4]
800471c: 6863 ldr r3, [r4, #4]
800471e: bf08 it eq
8004720: f8c8 1000 streq.w r1, [r8]
8004724: 5162 str r2, [r4, r5]
8004726: 604b str r3, [r1, #4]
8004728: 4630 mov r0, r6
800472a: f000 f82f bl 800478c <__malloc_unlock>
800472e: f104 000b add.w r0, r4, #11
8004732: 1d23 adds r3, r4, #4
8004734: f020 0007 bic.w r0, r0, #7
8004738: 1ac2 subs r2, r0, r3
800473a: bf1c itt ne
800473c: 1a1b subne r3, r3, r0
800473e: 50a3 strne r3, [r4, r2]
8004740: e7af b.n 80046a2 <_malloc_r+0x22>
8004742: 6862 ldr r2, [r4, #4]
8004744: 42a3 cmp r3, r4
8004746: bf0c ite eq
8004748: f8c8 2000 streq.w r2, [r8]
800474c: 605a strne r2, [r3, #4]
800474e: e7eb b.n 8004728 <_malloc_r+0xa8>
8004750: 4623 mov r3, r4
8004752: 6864 ldr r4, [r4, #4]
8004754: e7ae b.n 80046b4 <_malloc_r+0x34>
8004756: 463c mov r4, r7
8004758: 687f ldr r7, [r7, #4]
800475a: e7b6 b.n 80046ca <_malloc_r+0x4a>
800475c: 461a mov r2, r3
800475e: 685b ldr r3, [r3, #4]
8004760: 42a3 cmp r3, r4
8004762: d1fb bne.n 800475c <_malloc_r+0xdc>
8004764: 2300 movs r3, #0
8004766: 6053 str r3, [r2, #4]
8004768: e7de b.n 8004728 <_malloc_r+0xa8>
800476a: 230c movs r3, #12
800476c: 6033 str r3, [r6, #0]
800476e: 4630 mov r0, r6
8004770: f000 f80c bl 800478c <__malloc_unlock>
8004774: e794 b.n 80046a0 <_malloc_r+0x20>
8004776: 6005 str r5, [r0, #0]
8004778: e7d6 b.n 8004728 <_malloc_r+0xa8>
800477a: bf00 nop
800477c: 200007a8 .word 0x200007a8
08004780 <__malloc_lock>:
8004780: 4801 ldr r0, [pc, #4] @ (8004788 <__malloc_lock+0x8>)
8004782: f7ff b8ac b.w 80038de <__retarget_lock_acquire_recursive>
8004786: bf00 nop
8004788: 200007a0 .word 0x200007a0
0800478c <__malloc_unlock>:
800478c: 4801 ldr r0, [pc, #4] @ (8004794 <__malloc_unlock+0x8>)
800478e: f7ff b8a7 b.w 80038e0 <__retarget_lock_release_recursive>
8004792: bf00 nop
8004794: 200007a0 .word 0x200007a0
08004798 <_Balloc>:
8004798: b570 push {r4, r5, r6, lr}
800479a: 69c6 ldr r6, [r0, #28]
800479c: 4604 mov r4, r0
800479e: 460d mov r5, r1
80047a0: b976 cbnz r6, 80047c0 <_Balloc+0x28>
80047a2: 2010 movs r0, #16
80047a4: f7ff ff42 bl 800462c <malloc>
80047a8: 4602 mov r2, r0
80047aa: 61e0 str r0, [r4, #28]
80047ac: b920 cbnz r0, 80047b8 <_Balloc+0x20>
80047ae: 4b18 ldr r3, [pc, #96] @ (8004810 <_Balloc+0x78>)
80047b0: 4818 ldr r0, [pc, #96] @ (8004814 <_Balloc+0x7c>)
80047b2: 216b movs r1, #107 @ 0x6b
80047b4: f000 fc34 bl 8005020 <__assert_func>
80047b8: e9c0 6601 strd r6, r6, [r0, #4]
80047bc: 6006 str r6, [r0, #0]
80047be: 60c6 str r6, [r0, #12]
80047c0: 69e6 ldr r6, [r4, #28]
80047c2: 68f3 ldr r3, [r6, #12]
80047c4: b183 cbz r3, 80047e8 <_Balloc+0x50>
80047c6: 69e3 ldr r3, [r4, #28]
80047c8: 68db ldr r3, [r3, #12]
80047ca: f853 0025 ldr.w r0, [r3, r5, lsl #2]
80047ce: b9b8 cbnz r0, 8004800 <_Balloc+0x68>
80047d0: 2101 movs r1, #1
80047d2: fa01 f605 lsl.w r6, r1, r5
80047d6: 1d72 adds r2, r6, #5
80047d8: 0092 lsls r2, r2, #2
80047da: 4620 mov r0, r4
80047dc: f000 fc3e bl 800505c <_calloc_r>
80047e0: b160 cbz r0, 80047fc <_Balloc+0x64>
80047e2: e9c0 5601 strd r5, r6, [r0, #4]
80047e6: e00e b.n 8004806 <_Balloc+0x6e>
80047e8: 2221 movs r2, #33 @ 0x21
80047ea: 2104 movs r1, #4
80047ec: 4620 mov r0, r4
80047ee: f000 fc35 bl 800505c <_calloc_r>
80047f2: 69e3 ldr r3, [r4, #28]
80047f4: 60f0 str r0, [r6, #12]
80047f6: 68db ldr r3, [r3, #12]
80047f8: 2b00 cmp r3, #0
80047fa: d1e4 bne.n 80047c6 <_Balloc+0x2e>
80047fc: 2000 movs r0, #0
80047fe: bd70 pop {r4, r5, r6, pc}
8004800: 6802 ldr r2, [r0, #0]
8004802: f843 2025 str.w r2, [r3, r5, lsl #2]
8004806: 2300 movs r3, #0
8004808: e9c0 3303 strd r3, r3, [r0, #12]
800480c: e7f7 b.n 80047fe <_Balloc+0x66>
800480e: bf00 nop
8004810: 080056c9 .word 0x080056c9
8004814: 08005749 .word 0x08005749
08004818 <_Bfree>:
8004818: b570 push {r4, r5, r6, lr}
800481a: 69c6 ldr r6, [r0, #28]
800481c: 4605 mov r5, r0
800481e: 460c mov r4, r1
8004820: b976 cbnz r6, 8004840 <_Bfree+0x28>
8004822: 2010 movs r0, #16
8004824: f7ff ff02 bl 800462c <malloc>
8004828: 4602 mov r2, r0
800482a: 61e8 str r0, [r5, #28]
800482c: b920 cbnz r0, 8004838 <_Bfree+0x20>
800482e: 4b09 ldr r3, [pc, #36] @ (8004854 <_Bfree+0x3c>)
8004830: 4809 ldr r0, [pc, #36] @ (8004858 <_Bfree+0x40>)
8004832: 218f movs r1, #143 @ 0x8f
8004834: f000 fbf4 bl 8005020 <__assert_func>
8004838: e9c0 6601 strd r6, r6, [r0, #4]
800483c: 6006 str r6, [r0, #0]
800483e: 60c6 str r6, [r0, #12]
8004840: b13c cbz r4, 8004852 <_Bfree+0x3a>
8004842: 69eb ldr r3, [r5, #28]
8004844: 6862 ldr r2, [r4, #4]
8004846: 68db ldr r3, [r3, #12]
8004848: f853 1022 ldr.w r1, [r3, r2, lsl #2]
800484c: 6021 str r1, [r4, #0]
800484e: f843 4022 str.w r4, [r3, r2, lsl #2]
8004852: bd70 pop {r4, r5, r6, pc}
8004854: 080056c9 .word 0x080056c9
8004858: 08005749 .word 0x08005749
0800485c <__multadd>:
800485c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
8004860: 690d ldr r5, [r1, #16]
8004862: 4607 mov r7, r0
8004864: 460c mov r4, r1
8004866: 461e mov r6, r3
8004868: f101 0c14 add.w ip, r1, #20
800486c: 2000 movs r0, #0
800486e: f8dc 3000 ldr.w r3, [ip]
8004872: b299 uxth r1, r3
8004874: fb02 6101 mla r1, r2, r1, r6
8004878: 0c1e lsrs r6, r3, #16
800487a: 0c0b lsrs r3, r1, #16
800487c: fb02 3306 mla r3, r2, r6, r3
8004880: b289 uxth r1, r1
8004882: 3001 adds r0, #1
8004884: eb01 4103 add.w r1, r1, r3, lsl #16
8004888: 4285 cmp r5, r0
800488a: f84c 1b04 str.w r1, [ip], #4
800488e: ea4f 4613 mov.w r6, r3, lsr #16
8004892: dcec bgt.n 800486e <__multadd+0x12>
8004894: b30e cbz r6, 80048da <__multadd+0x7e>
8004896: 68a3 ldr r3, [r4, #8]
8004898: 42ab cmp r3, r5
800489a: dc19 bgt.n 80048d0 <__multadd+0x74>
800489c: 6861 ldr r1, [r4, #4]
800489e: 4638 mov r0, r7
80048a0: 3101 adds r1, #1
80048a2: f7ff ff79 bl 8004798 <_Balloc>
80048a6: 4680 mov r8, r0
80048a8: b928 cbnz r0, 80048b6 <__multadd+0x5a>
80048aa: 4602 mov r2, r0
80048ac: 4b0c ldr r3, [pc, #48] @ (80048e0 <__multadd+0x84>)
80048ae: 480d ldr r0, [pc, #52] @ (80048e4 <__multadd+0x88>)
80048b0: 21ba movs r1, #186 @ 0xba
80048b2: f000 fbb5 bl 8005020 <__assert_func>
80048b6: 6922 ldr r2, [r4, #16]
80048b8: 3202 adds r2, #2
80048ba: f104 010c add.w r1, r4, #12
80048be: 0092 lsls r2, r2, #2
80048c0: 300c adds r0, #12
80048c2: f000 fb9f bl 8005004 <memcpy>
80048c6: 4621 mov r1, r4
80048c8: 4638 mov r0, r7
80048ca: f7ff ffa5 bl 8004818 <_Bfree>
80048ce: 4644 mov r4, r8
80048d0: eb04 0385 add.w r3, r4, r5, lsl #2
80048d4: 3501 adds r5, #1
80048d6: 615e str r6, [r3, #20]
80048d8: 6125 str r5, [r4, #16]
80048da: 4620 mov r0, r4
80048dc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
80048e0: 08005738 .word 0x08005738
80048e4: 08005749 .word 0x08005749
080048e8 <__hi0bits>:
80048e8: f5b0 3f80 cmp.w r0, #65536 @ 0x10000
80048ec: 4603 mov r3, r0
80048ee: bf36 itet cc
80048f0: 0403 lslcc r3, r0, #16
80048f2: 2000 movcs r0, #0
80048f4: 2010 movcc r0, #16
80048f6: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
80048fa: bf3c itt cc
80048fc: 021b lslcc r3, r3, #8
80048fe: 3008 addcc r0, #8
8004900: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
8004904: bf3c itt cc
8004906: 011b lslcc r3, r3, #4
8004908: 3004 addcc r0, #4
800490a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800490e: bf3c itt cc
8004910: 009b lslcc r3, r3, #2
8004912: 3002 addcc r0, #2
8004914: 2b00 cmp r3, #0
8004916: db05 blt.n 8004924 <__hi0bits+0x3c>
8004918: f013 4f80 tst.w r3, #1073741824 @ 0x40000000
800491c: f100 0001 add.w r0, r0, #1
8004920: bf08 it eq
8004922: 2020 moveq r0, #32
8004924: 4770 bx lr
08004926 <__lo0bits>:
8004926: 6803 ldr r3, [r0, #0]
8004928: 4602 mov r2, r0
800492a: f013 0007 ands.w r0, r3, #7
800492e: d00b beq.n 8004948 <__lo0bits+0x22>
8004930: 07d9 lsls r1, r3, #31
8004932: d421 bmi.n 8004978 <__lo0bits+0x52>
8004934: 0798 lsls r0, r3, #30
8004936: bf49 itett mi
8004938: 085b lsrmi r3, r3, #1
800493a: 089b lsrpl r3, r3, #2
800493c: 2001 movmi r0, #1
800493e: 6013 strmi r3, [r2, #0]
8004940: bf5c itt pl
8004942: 6013 strpl r3, [r2, #0]
8004944: 2002 movpl r0, #2
8004946: 4770 bx lr
8004948: b299 uxth r1, r3
800494a: b909 cbnz r1, 8004950 <__lo0bits+0x2a>
800494c: 0c1b lsrs r3, r3, #16
800494e: 2010 movs r0, #16
8004950: b2d9 uxtb r1, r3
8004952: b909 cbnz r1, 8004958 <__lo0bits+0x32>
8004954: 3008 adds r0, #8
8004956: 0a1b lsrs r3, r3, #8
8004958: 0719 lsls r1, r3, #28
800495a: bf04 itt eq
800495c: 091b lsreq r3, r3, #4
800495e: 3004 addeq r0, #4
8004960: 0799 lsls r1, r3, #30
8004962: bf04 itt eq
8004964: 089b lsreq r3, r3, #2
8004966: 3002 addeq r0, #2
8004968: 07d9 lsls r1, r3, #31
800496a: d403 bmi.n 8004974 <__lo0bits+0x4e>
800496c: 085b lsrs r3, r3, #1
800496e: f100 0001 add.w r0, r0, #1
8004972: d003 beq.n 800497c <__lo0bits+0x56>
8004974: 6013 str r3, [r2, #0]
8004976: 4770 bx lr
8004978: 2000 movs r0, #0
800497a: 4770 bx lr
800497c: 2020 movs r0, #32
800497e: 4770 bx lr
08004980 <__i2b>:
8004980: b510 push {r4, lr}
8004982: 460c mov r4, r1
8004984: 2101 movs r1, #1
8004986: f7ff ff07 bl 8004798 <_Balloc>
800498a: 4602 mov r2, r0
800498c: b928 cbnz r0, 800499a <__i2b+0x1a>
800498e: 4b05 ldr r3, [pc, #20] @ (80049a4 <__i2b+0x24>)
8004990: 4805 ldr r0, [pc, #20] @ (80049a8 <__i2b+0x28>)
8004992: f240 1145 movw r1, #325 @ 0x145
8004996: f000 fb43 bl 8005020 <__assert_func>
800499a: 2301 movs r3, #1
800499c: 6144 str r4, [r0, #20]
800499e: 6103 str r3, [r0, #16]
80049a0: bd10 pop {r4, pc}
80049a2: bf00 nop
80049a4: 08005738 .word 0x08005738
80049a8: 08005749 .word 0x08005749
080049ac <__multiply>:
80049ac: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
80049b0: 4617 mov r7, r2
80049b2: 690a ldr r2, [r1, #16]
80049b4: 693b ldr r3, [r7, #16]
80049b6: 429a cmp r2, r3
80049b8: bfa8 it ge
80049ba: 463b movge r3, r7
80049bc: 4689 mov r9, r1
80049be: bfa4 itt ge
80049c0: 460f movge r7, r1
80049c2: 4699 movge r9, r3
80049c4: 693d ldr r5, [r7, #16]
80049c6: f8d9 a010 ldr.w sl, [r9, #16]
80049ca: 68bb ldr r3, [r7, #8]
80049cc: 6879 ldr r1, [r7, #4]
80049ce: eb05 060a add.w r6, r5, sl
80049d2: 42b3 cmp r3, r6
80049d4: b085 sub sp, #20
80049d6: bfb8 it lt
80049d8: 3101 addlt r1, #1
80049da: f7ff fedd bl 8004798 <_Balloc>
80049de: b930 cbnz r0, 80049ee <__multiply+0x42>
80049e0: 4602 mov r2, r0
80049e2: 4b41 ldr r3, [pc, #260] @ (8004ae8 <__multiply+0x13c>)
80049e4: 4841 ldr r0, [pc, #260] @ (8004aec <__multiply+0x140>)
80049e6: f44f 71b1 mov.w r1, #354 @ 0x162
80049ea: f000 fb19 bl 8005020 <__assert_func>
80049ee: f100 0414 add.w r4, r0, #20
80049f2: eb04 0e86 add.w lr, r4, r6, lsl #2
80049f6: 4623 mov r3, r4
80049f8: 2200 movs r2, #0
80049fa: 4573 cmp r3, lr
80049fc: d320 bcc.n 8004a40 <__multiply+0x94>
80049fe: f107 0814 add.w r8, r7, #20
8004a02: f109 0114 add.w r1, r9, #20
8004a06: eb08 0585 add.w r5, r8, r5, lsl #2
8004a0a: eb01 038a add.w r3, r1, sl, lsl #2
8004a0e: 9302 str r3, [sp, #8]
8004a10: 1beb subs r3, r5, r7
8004a12: 3b15 subs r3, #21
8004a14: f023 0303 bic.w r3, r3, #3
8004a18: 3304 adds r3, #4
8004a1a: 3715 adds r7, #21
8004a1c: 42bd cmp r5, r7
8004a1e: bf38 it cc
8004a20: 2304 movcc r3, #4
8004a22: 9301 str r3, [sp, #4]
8004a24: 9b02 ldr r3, [sp, #8]
8004a26: 9103 str r1, [sp, #12]
8004a28: 428b cmp r3, r1
8004a2a: d80c bhi.n 8004a46 <__multiply+0x9a>
8004a2c: 2e00 cmp r6, #0
8004a2e: dd03 ble.n 8004a38 <__multiply+0x8c>
8004a30: f85e 3d04 ldr.w r3, [lr, #-4]!
8004a34: 2b00 cmp r3, #0
8004a36: d055 beq.n 8004ae4 <__multiply+0x138>
8004a38: 6106 str r6, [r0, #16]
8004a3a: b005 add sp, #20
8004a3c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
8004a40: f843 2b04 str.w r2, [r3], #4
8004a44: e7d9 b.n 80049fa <__multiply+0x4e>
8004a46: f8b1 a000 ldrh.w sl, [r1]
8004a4a: f1ba 0f00 cmp.w sl, #0
8004a4e: d01f beq.n 8004a90 <__multiply+0xe4>
8004a50: 46c4 mov ip, r8
8004a52: 46a1 mov r9, r4
8004a54: 2700 movs r7, #0
8004a56: f85c 2b04 ldr.w r2, [ip], #4
8004a5a: f8d9 3000 ldr.w r3, [r9]
8004a5e: fa1f fb82 uxth.w fp, r2
8004a62: b29b uxth r3, r3
8004a64: fb0a 330b mla r3, sl, fp, r3
8004a68: 443b add r3, r7
8004a6a: f8d9 7000 ldr.w r7, [r9]
8004a6e: 0c12 lsrs r2, r2, #16
8004a70: 0c3f lsrs r7, r7, #16
8004a72: fb0a 7202 mla r2, sl, r2, r7
8004a76: eb02 4213 add.w r2, r2, r3, lsr #16
8004a7a: b29b uxth r3, r3
8004a7c: ea43 4302 orr.w r3, r3, r2, lsl #16
8004a80: 4565 cmp r5, ip
8004a82: f849 3b04 str.w r3, [r9], #4
8004a86: ea4f 4712 mov.w r7, r2, lsr #16
8004a8a: d8e4 bhi.n 8004a56 <__multiply+0xaa>
8004a8c: 9b01 ldr r3, [sp, #4]
8004a8e: 50e7 str r7, [r4, r3]
8004a90: 9b03 ldr r3, [sp, #12]
8004a92: f8b3 9002 ldrh.w r9, [r3, #2]
8004a96: 3104 adds r1, #4
8004a98: f1b9 0f00 cmp.w r9, #0
8004a9c: d020 beq.n 8004ae0 <__multiply+0x134>
8004a9e: 6823 ldr r3, [r4, #0]
8004aa0: 4647 mov r7, r8
8004aa2: 46a4 mov ip, r4
8004aa4: f04f 0a00 mov.w sl, #0
8004aa8: f8b7 b000 ldrh.w fp, [r7]
8004aac: f8bc 2002 ldrh.w r2, [ip, #2]
8004ab0: fb09 220b mla r2, r9, fp, r2
8004ab4: 4452 add r2, sl
8004ab6: b29b uxth r3, r3
8004ab8: ea43 4302 orr.w r3, r3, r2, lsl #16
8004abc: f84c 3b04 str.w r3, [ip], #4
8004ac0: f857 3b04 ldr.w r3, [r7], #4
8004ac4: ea4f 4a13 mov.w sl, r3, lsr #16
8004ac8: f8bc 3000 ldrh.w r3, [ip]
8004acc: fb09 330a mla r3, r9, sl, r3
8004ad0: eb03 4312 add.w r3, r3, r2, lsr #16
8004ad4: 42bd cmp r5, r7
8004ad6: ea4f 4a13 mov.w sl, r3, lsr #16
8004ada: d8e5 bhi.n 8004aa8 <__multiply+0xfc>
8004adc: 9a01 ldr r2, [sp, #4]
8004ade: 50a3 str r3, [r4, r2]
8004ae0: 3404 adds r4, #4
8004ae2: e79f b.n 8004a24 <__multiply+0x78>
8004ae4: 3e01 subs r6, #1
8004ae6: e7a1 b.n 8004a2c <__multiply+0x80>
8004ae8: 08005738 .word 0x08005738
8004aec: 08005749 .word 0x08005749
08004af0 <__pow5mult>:
8004af0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
8004af4: 4615 mov r5, r2
8004af6: f012 0203 ands.w r2, r2, #3
8004afa: 4607 mov r7, r0
8004afc: 460e mov r6, r1
8004afe: d007 beq.n 8004b10 <__pow5mult+0x20>
8004b00: 4c25 ldr r4, [pc, #148] @ (8004b98 <__pow5mult+0xa8>)
8004b02: 3a01 subs r2, #1
8004b04: 2300 movs r3, #0
8004b06: f854 2022 ldr.w r2, [r4, r2, lsl #2]
8004b0a: f7ff fea7 bl 800485c <__multadd>
8004b0e: 4606 mov r6, r0
8004b10: 10ad asrs r5, r5, #2
8004b12: d03d beq.n 8004b90 <__pow5mult+0xa0>
8004b14: 69fc ldr r4, [r7, #28]
8004b16: b97c cbnz r4, 8004b38 <__pow5mult+0x48>
8004b18: 2010 movs r0, #16
8004b1a: f7ff fd87 bl 800462c <malloc>
8004b1e: 4602 mov r2, r0
8004b20: 61f8 str r0, [r7, #28]
8004b22: b928 cbnz r0, 8004b30 <__pow5mult+0x40>
8004b24: 4b1d ldr r3, [pc, #116] @ (8004b9c <__pow5mult+0xac>)
8004b26: 481e ldr r0, [pc, #120] @ (8004ba0 <__pow5mult+0xb0>)
8004b28: f240 11b3 movw r1, #435 @ 0x1b3
8004b2c: f000 fa78 bl 8005020 <__assert_func>
8004b30: e9c0 4401 strd r4, r4, [r0, #4]
8004b34: 6004 str r4, [r0, #0]
8004b36: 60c4 str r4, [r0, #12]
8004b38: f8d7 801c ldr.w r8, [r7, #28]
8004b3c: f8d8 4008 ldr.w r4, [r8, #8]
8004b40: b94c cbnz r4, 8004b56 <__pow5mult+0x66>
8004b42: f240 2171 movw r1, #625 @ 0x271
8004b46: 4638 mov r0, r7
8004b48: f7ff ff1a bl 8004980 <__i2b>
8004b4c: 2300 movs r3, #0
8004b4e: f8c8 0008 str.w r0, [r8, #8]
8004b52: 4604 mov r4, r0
8004b54: 6003 str r3, [r0, #0]
8004b56: f04f 0900 mov.w r9, #0
8004b5a: 07eb lsls r3, r5, #31
8004b5c: d50a bpl.n 8004b74 <__pow5mult+0x84>
8004b5e: 4631 mov r1, r6
8004b60: 4622 mov r2, r4
8004b62: 4638 mov r0, r7
8004b64: f7ff ff22 bl 80049ac <__multiply>
8004b68: 4631 mov r1, r6
8004b6a: 4680 mov r8, r0
8004b6c: 4638 mov r0, r7
8004b6e: f7ff fe53 bl 8004818 <_Bfree>
8004b72: 4646 mov r6, r8
8004b74: 106d asrs r5, r5, #1
8004b76: d00b beq.n 8004b90 <__pow5mult+0xa0>
8004b78: 6820 ldr r0, [r4, #0]
8004b7a: b938 cbnz r0, 8004b8c <__pow5mult+0x9c>
8004b7c: 4622 mov r2, r4
8004b7e: 4621 mov r1, r4
8004b80: 4638 mov r0, r7
8004b82: f7ff ff13 bl 80049ac <__multiply>
8004b86: 6020 str r0, [r4, #0]
8004b88: f8c0 9000 str.w r9, [r0]
8004b8c: 4604 mov r4, r0
8004b8e: e7e4 b.n 8004b5a <__pow5mult+0x6a>
8004b90: 4630 mov r0, r6
8004b92: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
8004b96: bf00 nop
8004b98: 080057fc .word 0x080057fc
8004b9c: 080056c9 .word 0x080056c9
8004ba0: 08005749 .word 0x08005749
08004ba4 <__lshift>:
8004ba4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8004ba8: 460c mov r4, r1
8004baa: 6849 ldr r1, [r1, #4]
8004bac: 6923 ldr r3, [r4, #16]
8004bae: eb03 1862 add.w r8, r3, r2, asr #5
8004bb2: 68a3 ldr r3, [r4, #8]
8004bb4: 4607 mov r7, r0
8004bb6: 4691 mov r9, r2
8004bb8: ea4f 1a62 mov.w sl, r2, asr #5
8004bbc: f108 0601 add.w r6, r8, #1
8004bc0: 42b3 cmp r3, r6
8004bc2: db0b blt.n 8004bdc <__lshift+0x38>
8004bc4: 4638 mov r0, r7
8004bc6: f7ff fde7 bl 8004798 <_Balloc>
8004bca: 4605 mov r5, r0
8004bcc: b948 cbnz r0, 8004be2 <__lshift+0x3e>
8004bce: 4602 mov r2, r0
8004bd0: 4b28 ldr r3, [pc, #160] @ (8004c74 <__lshift+0xd0>)
8004bd2: 4829 ldr r0, [pc, #164] @ (8004c78 <__lshift+0xd4>)
8004bd4: f44f 71ef mov.w r1, #478 @ 0x1de
8004bd8: f000 fa22 bl 8005020 <__assert_func>
8004bdc: 3101 adds r1, #1
8004bde: 005b lsls r3, r3, #1
8004be0: e7ee b.n 8004bc0 <__lshift+0x1c>
8004be2: 2300 movs r3, #0
8004be4: f100 0114 add.w r1, r0, #20
8004be8: f100 0210 add.w r2, r0, #16
8004bec: 4618 mov r0, r3
8004bee: 4553 cmp r3, sl
8004bf0: db33 blt.n 8004c5a <__lshift+0xb6>
8004bf2: 6920 ldr r0, [r4, #16]
8004bf4: ea2a 7aea bic.w sl, sl, sl, asr #31
8004bf8: f104 0314 add.w r3, r4, #20
8004bfc: f019 091f ands.w r9, r9, #31
8004c00: eb01 018a add.w r1, r1, sl, lsl #2
8004c04: eb03 0c80 add.w ip, r3, r0, lsl #2
8004c08: d02b beq.n 8004c62 <__lshift+0xbe>
8004c0a: f1c9 0e20 rsb lr, r9, #32
8004c0e: 468a mov sl, r1
8004c10: 2200 movs r2, #0
8004c12: 6818 ldr r0, [r3, #0]
8004c14: fa00 f009 lsl.w r0, r0, r9
8004c18: 4310 orrs r0, r2
8004c1a: f84a 0b04 str.w r0, [sl], #4
8004c1e: f853 2b04 ldr.w r2, [r3], #4
8004c22: 459c cmp ip, r3
8004c24: fa22 f20e lsr.w r2, r2, lr
8004c28: d8f3 bhi.n 8004c12 <__lshift+0x6e>
8004c2a: ebac 0304 sub.w r3, ip, r4
8004c2e: 3b15 subs r3, #21
8004c30: f023 0303 bic.w r3, r3, #3
8004c34: 3304 adds r3, #4
8004c36: f104 0015 add.w r0, r4, #21
8004c3a: 4560 cmp r0, ip
8004c3c: bf88 it hi
8004c3e: 2304 movhi r3, #4
8004c40: 50ca str r2, [r1, r3]
8004c42: b10a cbz r2, 8004c48 <__lshift+0xa4>
8004c44: f108 0602 add.w r6, r8, #2
8004c48: 3e01 subs r6, #1
8004c4a: 4638 mov r0, r7
8004c4c: 612e str r6, [r5, #16]
8004c4e: 4621 mov r1, r4
8004c50: f7ff fde2 bl 8004818 <_Bfree>
8004c54: 4628 mov r0, r5
8004c56: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8004c5a: f842 0f04 str.w r0, [r2, #4]!
8004c5e: 3301 adds r3, #1
8004c60: e7c5 b.n 8004bee <__lshift+0x4a>
8004c62: 3904 subs r1, #4
8004c64: f853 2b04 ldr.w r2, [r3], #4
8004c68: f841 2f04 str.w r2, [r1, #4]!
8004c6c: 459c cmp ip, r3
8004c6e: d8f9 bhi.n 8004c64 <__lshift+0xc0>
8004c70: e7ea b.n 8004c48 <__lshift+0xa4>
8004c72: bf00 nop
8004c74: 08005738 .word 0x08005738
8004c78: 08005749 .word 0x08005749
08004c7c <__mcmp>:
8004c7c: 690a ldr r2, [r1, #16]
8004c7e: 4603 mov r3, r0
8004c80: 6900 ldr r0, [r0, #16]
8004c82: 1a80 subs r0, r0, r2
8004c84: b530 push {r4, r5, lr}
8004c86: d10e bne.n 8004ca6 <__mcmp+0x2a>
8004c88: 3314 adds r3, #20
8004c8a: 3114 adds r1, #20
8004c8c: eb03 0482 add.w r4, r3, r2, lsl #2
8004c90: eb01 0182 add.w r1, r1, r2, lsl #2
8004c94: f854 5d04 ldr.w r5, [r4, #-4]!
8004c98: f851 2d04 ldr.w r2, [r1, #-4]!
8004c9c: 4295 cmp r5, r2
8004c9e: d003 beq.n 8004ca8 <__mcmp+0x2c>
8004ca0: d205 bcs.n 8004cae <__mcmp+0x32>
8004ca2: f04f 30ff mov.w r0, #4294967295
8004ca6: bd30 pop {r4, r5, pc}
8004ca8: 42a3 cmp r3, r4
8004caa: d3f3 bcc.n 8004c94 <__mcmp+0x18>
8004cac: e7fb b.n 8004ca6 <__mcmp+0x2a>
8004cae: 2001 movs r0, #1
8004cb0: e7f9 b.n 8004ca6 <__mcmp+0x2a>
...
08004cb4 <__mdiff>:
8004cb4: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
8004cb8: 4689 mov r9, r1
8004cba: 4606 mov r6, r0
8004cbc: 4611 mov r1, r2
8004cbe: 4648 mov r0, r9
8004cc0: 4614 mov r4, r2
8004cc2: f7ff ffdb bl 8004c7c <__mcmp>
8004cc6: 1e05 subs r5, r0, #0
8004cc8: d112 bne.n 8004cf0 <__mdiff+0x3c>
8004cca: 4629 mov r1, r5
8004ccc: 4630 mov r0, r6
8004cce: f7ff fd63 bl 8004798 <_Balloc>
8004cd2: 4602 mov r2, r0
8004cd4: b928 cbnz r0, 8004ce2 <__mdiff+0x2e>
8004cd6: 4b3f ldr r3, [pc, #252] @ (8004dd4 <__mdiff+0x120>)
8004cd8: f240 2137 movw r1, #567 @ 0x237
8004cdc: 483e ldr r0, [pc, #248] @ (8004dd8 <__mdiff+0x124>)
8004cde: f000 f99f bl 8005020 <__assert_func>
8004ce2: 2301 movs r3, #1
8004ce4: e9c0 3504 strd r3, r5, [r0, #16]
8004ce8: 4610 mov r0, r2
8004cea: b003 add sp, #12
8004cec: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
8004cf0: bfbc itt lt
8004cf2: 464b movlt r3, r9
8004cf4: 46a1 movlt r9, r4
8004cf6: 4630 mov r0, r6
8004cf8: f8d9 1004 ldr.w r1, [r9, #4]
8004cfc: bfba itte lt
8004cfe: 461c movlt r4, r3
8004d00: 2501 movlt r5, #1
8004d02: 2500 movge r5, #0
8004d04: f7ff fd48 bl 8004798 <_Balloc>
8004d08: 4602 mov r2, r0
8004d0a: b918 cbnz r0, 8004d14 <__mdiff+0x60>
8004d0c: 4b31 ldr r3, [pc, #196] @ (8004dd4 <__mdiff+0x120>)
8004d0e: f240 2145 movw r1, #581 @ 0x245
8004d12: e7e3 b.n 8004cdc <__mdiff+0x28>
8004d14: f8d9 7010 ldr.w r7, [r9, #16]
8004d18: 6926 ldr r6, [r4, #16]
8004d1a: 60c5 str r5, [r0, #12]
8004d1c: f109 0310 add.w r3, r9, #16
8004d20: f109 0514 add.w r5, r9, #20
8004d24: f104 0e14 add.w lr, r4, #20
8004d28: f100 0b14 add.w fp, r0, #20
8004d2c: eb05 0887 add.w r8, r5, r7, lsl #2
8004d30: eb0e 0686 add.w r6, lr, r6, lsl #2
8004d34: 9301 str r3, [sp, #4]
8004d36: 46d9 mov r9, fp
8004d38: f04f 0c00 mov.w ip, #0
8004d3c: 9b01 ldr r3, [sp, #4]
8004d3e: f85e 0b04 ldr.w r0, [lr], #4
8004d42: f853 af04 ldr.w sl, [r3, #4]!
8004d46: 9301 str r3, [sp, #4]
8004d48: fa1f f38a uxth.w r3, sl
8004d4c: 4619 mov r1, r3
8004d4e: b283 uxth r3, r0
8004d50: 1acb subs r3, r1, r3
8004d52: 0c00 lsrs r0, r0, #16
8004d54: 4463 add r3, ip
8004d56: ebc0 401a rsb r0, r0, sl, lsr #16
8004d5a: eb00 4023 add.w r0, r0, r3, asr #16
8004d5e: b29b uxth r3, r3
8004d60: ea43 4300 orr.w r3, r3, r0, lsl #16
8004d64: 4576 cmp r6, lr
8004d66: f849 3b04 str.w r3, [r9], #4
8004d6a: ea4f 4c20 mov.w ip, r0, asr #16
8004d6e: d8e5 bhi.n 8004d3c <__mdiff+0x88>
8004d70: 1b33 subs r3, r6, r4
8004d72: 3b15 subs r3, #21
8004d74: f023 0303 bic.w r3, r3, #3
8004d78: 3415 adds r4, #21
8004d7a: 3304 adds r3, #4
8004d7c: 42a6 cmp r6, r4
8004d7e: bf38 it cc
8004d80: 2304 movcc r3, #4
8004d82: 441d add r5, r3
8004d84: 445b add r3, fp
8004d86: 461e mov r6, r3
8004d88: 462c mov r4, r5
8004d8a: 4544 cmp r4, r8
8004d8c: d30e bcc.n 8004dac <__mdiff+0xf8>
8004d8e: f108 0103 add.w r1, r8, #3
8004d92: 1b49 subs r1, r1, r5
8004d94: f021 0103 bic.w r1, r1, #3
8004d98: 3d03 subs r5, #3
8004d9a: 45a8 cmp r8, r5
8004d9c: bf38 it cc
8004d9e: 2100 movcc r1, #0
8004da0: 440b add r3, r1
8004da2: f853 1d04 ldr.w r1, [r3, #-4]!
8004da6: b191 cbz r1, 8004dce <__mdiff+0x11a>
8004da8: 6117 str r7, [r2, #16]
8004daa: e79d b.n 8004ce8 <__mdiff+0x34>
8004dac: f854 1b04 ldr.w r1, [r4], #4
8004db0: 46e6 mov lr, ip
8004db2: 0c08 lsrs r0, r1, #16
8004db4: fa1c fc81 uxtah ip, ip, r1
8004db8: 4471 add r1, lr
8004dba: eb00 402c add.w r0, r0, ip, asr #16
8004dbe: b289 uxth r1, r1
8004dc0: ea41 4100 orr.w r1, r1, r0, lsl #16
8004dc4: f846 1b04 str.w r1, [r6], #4
8004dc8: ea4f 4c20 mov.w ip, r0, asr #16
8004dcc: e7dd b.n 8004d8a <__mdiff+0xd6>
8004dce: 3f01 subs r7, #1
8004dd0: e7e7 b.n 8004da2 <__mdiff+0xee>
8004dd2: bf00 nop
8004dd4: 08005738 .word 0x08005738
8004dd8: 08005749 .word 0x08005749
08004ddc <__d2b>:
8004ddc: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
8004de0: 460f mov r7, r1
8004de2: 2101 movs r1, #1
8004de4: ec59 8b10 vmov r8, r9, d0
8004de8: 4616 mov r6, r2
8004dea: f7ff fcd5 bl 8004798 <_Balloc>
8004dee: 4604 mov r4, r0
8004df0: b930 cbnz r0, 8004e00 <__d2b+0x24>
8004df2: 4602 mov r2, r0
8004df4: 4b23 ldr r3, [pc, #140] @ (8004e84 <__d2b+0xa8>)
8004df6: 4824 ldr r0, [pc, #144] @ (8004e88 <__d2b+0xac>)
8004df8: f240 310f movw r1, #783 @ 0x30f
8004dfc: f000 f910 bl 8005020 <__assert_func>
8004e00: f3c9 550a ubfx r5, r9, #20, #11
8004e04: f3c9 0313 ubfx r3, r9, #0, #20
8004e08: b10d cbz r5, 8004e0e <__d2b+0x32>
8004e0a: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8004e0e: 9301 str r3, [sp, #4]
8004e10: f1b8 0300 subs.w r3, r8, #0
8004e14: d023 beq.n 8004e5e <__d2b+0x82>
8004e16: 4668 mov r0, sp
8004e18: 9300 str r3, [sp, #0]
8004e1a: f7ff fd84 bl 8004926 <__lo0bits>
8004e1e: e9dd 1200 ldrd r1, r2, [sp]
8004e22: b1d0 cbz r0, 8004e5a <__d2b+0x7e>
8004e24: f1c0 0320 rsb r3, r0, #32
8004e28: fa02 f303 lsl.w r3, r2, r3
8004e2c: 430b orrs r3, r1
8004e2e: 40c2 lsrs r2, r0
8004e30: 6163 str r3, [r4, #20]
8004e32: 9201 str r2, [sp, #4]
8004e34: 9b01 ldr r3, [sp, #4]
8004e36: 61a3 str r3, [r4, #24]
8004e38: 2b00 cmp r3, #0
8004e3a: bf0c ite eq
8004e3c: 2201 moveq r2, #1
8004e3e: 2202 movne r2, #2
8004e40: 6122 str r2, [r4, #16]
8004e42: b1a5 cbz r5, 8004e6e <__d2b+0x92>
8004e44: f2a5 4533 subw r5, r5, #1075 @ 0x433
8004e48: 4405 add r5, r0
8004e4a: 603d str r5, [r7, #0]
8004e4c: f1c0 0035 rsb r0, r0, #53 @ 0x35
8004e50: 6030 str r0, [r6, #0]
8004e52: 4620 mov r0, r4
8004e54: b003 add sp, #12
8004e56: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
8004e5a: 6161 str r1, [r4, #20]
8004e5c: e7ea b.n 8004e34 <__d2b+0x58>
8004e5e: a801 add r0, sp, #4
8004e60: f7ff fd61 bl 8004926 <__lo0bits>
8004e64: 9b01 ldr r3, [sp, #4]
8004e66: 6163 str r3, [r4, #20]
8004e68: 3020 adds r0, #32
8004e6a: 2201 movs r2, #1
8004e6c: e7e8 b.n 8004e40 <__d2b+0x64>
8004e6e: eb04 0382 add.w r3, r4, r2, lsl #2
8004e72: f2a0 4032 subw r0, r0, #1074 @ 0x432
8004e76: 6038 str r0, [r7, #0]
8004e78: 6918 ldr r0, [r3, #16]
8004e7a: f7ff fd35 bl 80048e8 <__hi0bits>
8004e7e: ebc0 1042 rsb r0, r0, r2, lsl #5
8004e82: e7e5 b.n 8004e50 <__d2b+0x74>
8004e84: 08005738 .word 0x08005738
8004e88: 08005749 .word 0x08005749
08004e8c <__sflush_r>:
8004e8c: f9b1 200c ldrsh.w r2, [r1, #12]
8004e90: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
8004e94: 0716 lsls r6, r2, #28
8004e96: 4605 mov r5, r0
8004e98: 460c mov r4, r1
8004e9a: d454 bmi.n 8004f46 <__sflush_r+0xba>
8004e9c: 684b ldr r3, [r1, #4]
8004e9e: 2b00 cmp r3, #0
8004ea0: dc02 bgt.n 8004ea8 <__sflush_r+0x1c>
8004ea2: 6c0b ldr r3, [r1, #64] @ 0x40
8004ea4: 2b00 cmp r3, #0
8004ea6: dd48 ble.n 8004f3a <__sflush_r+0xae>
8004ea8: 6ae6 ldr r6, [r4, #44] @ 0x2c
8004eaa: 2e00 cmp r6, #0
8004eac: d045 beq.n 8004f3a <__sflush_r+0xae>
8004eae: 2300 movs r3, #0
8004eb0: f412 5280 ands.w r2, r2, #4096 @ 0x1000
8004eb4: 682f ldr r7, [r5, #0]
8004eb6: 6a21 ldr r1, [r4, #32]
8004eb8: 602b str r3, [r5, #0]
8004eba: d030 beq.n 8004f1e <__sflush_r+0x92>
8004ebc: 6d62 ldr r2, [r4, #84] @ 0x54
8004ebe: 89a3 ldrh r3, [r4, #12]
8004ec0: 0759 lsls r1, r3, #29
8004ec2: d505 bpl.n 8004ed0 <__sflush_r+0x44>
8004ec4: 6863 ldr r3, [r4, #4]
8004ec6: 1ad2 subs r2, r2, r3
8004ec8: 6b63 ldr r3, [r4, #52] @ 0x34
8004eca: b10b cbz r3, 8004ed0 <__sflush_r+0x44>
8004ecc: 6c23 ldr r3, [r4, #64] @ 0x40
8004ece: 1ad2 subs r2, r2, r3
8004ed0: 2300 movs r3, #0
8004ed2: 6ae6 ldr r6, [r4, #44] @ 0x2c
8004ed4: 6a21 ldr r1, [r4, #32]
8004ed6: 4628 mov r0, r5
8004ed8: 47b0 blx r6
8004eda: 1c43 adds r3, r0, #1
8004edc: 89a3 ldrh r3, [r4, #12]
8004ede: d106 bne.n 8004eee <__sflush_r+0x62>
8004ee0: 6829 ldr r1, [r5, #0]
8004ee2: 291d cmp r1, #29
8004ee4: d82b bhi.n 8004f3e <__sflush_r+0xb2>
8004ee6: 4a2a ldr r2, [pc, #168] @ (8004f90 <__sflush_r+0x104>)
8004ee8: 40ca lsrs r2, r1
8004eea: 07d6 lsls r6, r2, #31
8004eec: d527 bpl.n 8004f3e <__sflush_r+0xb2>
8004eee: 2200 movs r2, #0
8004ef0: 6062 str r2, [r4, #4]
8004ef2: 04d9 lsls r1, r3, #19
8004ef4: 6922 ldr r2, [r4, #16]
8004ef6: 6022 str r2, [r4, #0]
8004ef8: d504 bpl.n 8004f04 <__sflush_r+0x78>
8004efa: 1c42 adds r2, r0, #1
8004efc: d101 bne.n 8004f02 <__sflush_r+0x76>
8004efe: 682b ldr r3, [r5, #0]
8004f00: b903 cbnz r3, 8004f04 <__sflush_r+0x78>
8004f02: 6560 str r0, [r4, #84] @ 0x54
8004f04: 6b61 ldr r1, [r4, #52] @ 0x34
8004f06: 602f str r7, [r5, #0]
8004f08: b1b9 cbz r1, 8004f3a <__sflush_r+0xae>
8004f0a: f104 0344 add.w r3, r4, #68 @ 0x44
8004f0e: 4299 cmp r1, r3
8004f10: d002 beq.n 8004f18 <__sflush_r+0x8c>
8004f12: 4628 mov r0, r5
8004f14: f7ff fb40 bl 8004598 <_free_r>
8004f18: 2300 movs r3, #0
8004f1a: 6363 str r3, [r4, #52] @ 0x34
8004f1c: e00d b.n 8004f3a <__sflush_r+0xae>
8004f1e: 2301 movs r3, #1
8004f20: 4628 mov r0, r5
8004f22: 47b0 blx r6
8004f24: 4602 mov r2, r0
8004f26: 1c50 adds r0, r2, #1
8004f28: d1c9 bne.n 8004ebe <__sflush_r+0x32>
8004f2a: 682b ldr r3, [r5, #0]
8004f2c: 2b00 cmp r3, #0
8004f2e: d0c6 beq.n 8004ebe <__sflush_r+0x32>
8004f30: 2b1d cmp r3, #29
8004f32: d001 beq.n 8004f38 <__sflush_r+0xac>
8004f34: 2b16 cmp r3, #22
8004f36: d11e bne.n 8004f76 <__sflush_r+0xea>
8004f38: 602f str r7, [r5, #0]
8004f3a: 2000 movs r0, #0
8004f3c: e022 b.n 8004f84 <__sflush_r+0xf8>
8004f3e: f043 0340 orr.w r3, r3, #64 @ 0x40
8004f42: b21b sxth r3, r3
8004f44: e01b b.n 8004f7e <__sflush_r+0xf2>
8004f46: 690f ldr r7, [r1, #16]
8004f48: 2f00 cmp r7, #0
8004f4a: d0f6 beq.n 8004f3a <__sflush_r+0xae>
8004f4c: 0793 lsls r3, r2, #30
8004f4e: 680e ldr r6, [r1, #0]
8004f50: bf08 it eq
8004f52: 694b ldreq r3, [r1, #20]
8004f54: 600f str r7, [r1, #0]
8004f56: bf18 it ne
8004f58: 2300 movne r3, #0
8004f5a: eba6 0807 sub.w r8, r6, r7
8004f5e: 608b str r3, [r1, #8]
8004f60: f1b8 0f00 cmp.w r8, #0
8004f64: dde9 ble.n 8004f3a <__sflush_r+0xae>
8004f66: 6a21 ldr r1, [r4, #32]
8004f68: 6aa6 ldr r6, [r4, #40] @ 0x28
8004f6a: 4643 mov r3, r8
8004f6c: 463a mov r2, r7
8004f6e: 4628 mov r0, r5
8004f70: 47b0 blx r6
8004f72: 2800 cmp r0, #0
8004f74: dc08 bgt.n 8004f88 <__sflush_r+0xfc>
8004f76: f9b4 300c ldrsh.w r3, [r4, #12]
8004f7a: f043 0340 orr.w r3, r3, #64 @ 0x40
8004f7e: 81a3 strh r3, [r4, #12]
8004f80: f04f 30ff mov.w r0, #4294967295
8004f84: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
8004f88: 4407 add r7, r0
8004f8a: eba8 0800 sub.w r8, r8, r0
8004f8e: e7e7 b.n 8004f60 <__sflush_r+0xd4>
8004f90: 20400001 .word 0x20400001
08004f94 <_fflush_r>:
8004f94: b538 push {r3, r4, r5, lr}
8004f96: 690b ldr r3, [r1, #16]
8004f98: 4605 mov r5, r0
8004f9a: 460c mov r4, r1
8004f9c: b913 cbnz r3, 8004fa4 <_fflush_r+0x10>
8004f9e: 2500 movs r5, #0
8004fa0: 4628 mov r0, r5
8004fa2: bd38 pop {r3, r4, r5, pc}
8004fa4: b118 cbz r0, 8004fae <_fflush_r+0x1a>
8004fa6: 6a03 ldr r3, [r0, #32]
8004fa8: b90b cbnz r3, 8004fae <_fflush_r+0x1a>
8004faa: f7fe fba1 bl 80036f0 <__sinit>
8004fae: f9b4 300c ldrsh.w r3, [r4, #12]
8004fb2: 2b00 cmp r3, #0
8004fb4: d0f3 beq.n 8004f9e <_fflush_r+0xa>
8004fb6: 6e62 ldr r2, [r4, #100] @ 0x64
8004fb8: 07d0 lsls r0, r2, #31
8004fba: d404 bmi.n 8004fc6 <_fflush_r+0x32>
8004fbc: 0599 lsls r1, r3, #22
8004fbe: d402 bmi.n 8004fc6 <_fflush_r+0x32>
8004fc0: 6da0 ldr r0, [r4, #88] @ 0x58
8004fc2: f7fe fc8c bl 80038de <__retarget_lock_acquire_recursive>
8004fc6: 4628 mov r0, r5
8004fc8: 4621 mov r1, r4
8004fca: f7ff ff5f bl 8004e8c <__sflush_r>
8004fce: 6e63 ldr r3, [r4, #100] @ 0x64
8004fd0: 07da lsls r2, r3, #31
8004fd2: 4605 mov r5, r0
8004fd4: d4e4 bmi.n 8004fa0 <_fflush_r+0xc>
8004fd6: 89a3 ldrh r3, [r4, #12]
8004fd8: 059b lsls r3, r3, #22
8004fda: d4e1 bmi.n 8004fa0 <_fflush_r+0xc>
8004fdc: 6da0 ldr r0, [r4, #88] @ 0x58
8004fde: f7fe fc7f bl 80038e0 <__retarget_lock_release_recursive>
8004fe2: e7dd b.n 8004fa0 <_fflush_r+0xc>
08004fe4 <_sbrk_r>:
8004fe4: b538 push {r3, r4, r5, lr}
8004fe6: 4d06 ldr r5, [pc, #24] @ (8005000 <_sbrk_r+0x1c>)
8004fe8: 2300 movs r3, #0
8004fea: 4604 mov r4, r0
8004fec: 4608 mov r0, r1
8004fee: 602b str r3, [r5, #0]
8004ff0: f7fc f986 bl 8001300 <_sbrk>
8004ff4: 1c43 adds r3, r0, #1
8004ff6: d102 bne.n 8004ffe <_sbrk_r+0x1a>
8004ff8: 682b ldr r3, [r5, #0]
8004ffa: b103 cbz r3, 8004ffe <_sbrk_r+0x1a>
8004ffc: 6023 str r3, [r4, #0]
8004ffe: bd38 pop {r3, r4, r5, pc}
8005000: 2000079c .word 0x2000079c
08005004 <memcpy>:
8005004: 440a add r2, r1
8005006: 4291 cmp r1, r2
8005008: f100 33ff add.w r3, r0, #4294967295
800500c: d100 bne.n 8005010 <memcpy+0xc>
800500e: 4770 bx lr
8005010: b510 push {r4, lr}
8005012: f811 4b01 ldrb.w r4, [r1], #1
8005016: f803 4f01 strb.w r4, [r3, #1]!
800501a: 4291 cmp r1, r2
800501c: d1f9 bne.n 8005012 <memcpy+0xe>
800501e: bd10 pop {r4, pc}
08005020 <__assert_func>:
8005020: b51f push {r0, r1, r2, r3, r4, lr}
8005022: 4614 mov r4, r2
8005024: 461a mov r2, r3
8005026: 4b09 ldr r3, [pc, #36] @ (800504c <__assert_func+0x2c>)
8005028: 681b ldr r3, [r3, #0]
800502a: 4605 mov r5, r0
800502c: 68d8 ldr r0, [r3, #12]
800502e: b14c cbz r4, 8005044 <__assert_func+0x24>
8005030: 4b07 ldr r3, [pc, #28] @ (8005050 <__assert_func+0x30>)
8005032: 9100 str r1, [sp, #0]
8005034: e9cd 3401 strd r3, r4, [sp, #4]
8005038: 4906 ldr r1, [pc, #24] @ (8005054 <__assert_func+0x34>)
800503a: 462b mov r3, r5
800503c: f000 f842 bl 80050c4 <fiprintf>
8005040: f000 f852 bl 80050e8 <abort>
8005044: 4b04 ldr r3, [pc, #16] @ (8005058 <__assert_func+0x38>)
8005046: 461c mov r4, r3
8005048: e7f3 b.n 8005032 <__assert_func+0x12>
800504a: bf00 nop
800504c: 20000018 .word 0x20000018
8005050: 080057ac .word 0x080057ac
8005054: 080057b9 .word 0x080057b9
8005058: 080057e7 .word 0x080057e7
0800505c <_calloc_r>:
800505c: b570 push {r4, r5, r6, lr}
800505e: fba1 5402 umull r5, r4, r1, r2
8005062: b934 cbnz r4, 8005072 <_calloc_r+0x16>
8005064: 4629 mov r1, r5
8005066: f7ff fb0b bl 8004680 <_malloc_r>
800506a: 4606 mov r6, r0
800506c: b928 cbnz r0, 800507a <_calloc_r+0x1e>
800506e: 4630 mov r0, r6
8005070: bd70 pop {r4, r5, r6, pc}
8005072: 220c movs r2, #12
8005074: 6002 str r2, [r0, #0]
8005076: 2600 movs r6, #0
8005078: e7f9 b.n 800506e <_calloc_r+0x12>
800507a: 462a mov r2, r5
800507c: 4621 mov r1, r4
800507e: f7fe fbb0 bl 80037e2 <memset>
8005082: e7f4 b.n 800506e <_calloc_r+0x12>
08005084 <__ascii_mbtowc>:
8005084: b082 sub sp, #8
8005086: b901 cbnz r1, 800508a <__ascii_mbtowc+0x6>
8005088: a901 add r1, sp, #4
800508a: b142 cbz r2, 800509e <__ascii_mbtowc+0x1a>
800508c: b14b cbz r3, 80050a2 <__ascii_mbtowc+0x1e>
800508e: 7813 ldrb r3, [r2, #0]
8005090: 600b str r3, [r1, #0]
8005092: 7812 ldrb r2, [r2, #0]
8005094: 1e10 subs r0, r2, #0
8005096: bf18 it ne
8005098: 2001 movne r0, #1
800509a: b002 add sp, #8
800509c: 4770 bx lr
800509e: 4610 mov r0, r2
80050a0: e7fb b.n 800509a <__ascii_mbtowc+0x16>
80050a2: f06f 0001 mvn.w r0, #1
80050a6: e7f8 b.n 800509a <__ascii_mbtowc+0x16>
080050a8 <__ascii_wctomb>:
80050a8: 4603 mov r3, r0
80050aa: 4608 mov r0, r1
80050ac: b141 cbz r1, 80050c0 <__ascii_wctomb+0x18>
80050ae: 2aff cmp r2, #255 @ 0xff
80050b0: d904 bls.n 80050bc <__ascii_wctomb+0x14>
80050b2: 228a movs r2, #138 @ 0x8a
80050b4: 601a str r2, [r3, #0]
80050b6: f04f 30ff mov.w r0, #4294967295
80050ba: 4770 bx lr
80050bc: 700a strb r2, [r1, #0]
80050be: 2001 movs r0, #1
80050c0: 4770 bx lr
...
080050c4 <fiprintf>:
80050c4: b40e push {r1, r2, r3}
80050c6: b503 push {r0, r1, lr}
80050c8: 4601 mov r1, r0
80050ca: ab03 add r3, sp, #12
80050cc: 4805 ldr r0, [pc, #20] @ (80050e4 <fiprintf+0x20>)
80050ce: f853 2b04 ldr.w r2, [r3], #4
80050d2: 6800 ldr r0, [r0, #0]
80050d4: 9301 str r3, [sp, #4]
80050d6: f000 f837 bl 8005148 <_vfiprintf_r>
80050da: b002 add sp, #8
80050dc: f85d eb04 ldr.w lr, [sp], #4
80050e0: b003 add sp, #12
80050e2: 4770 bx lr
80050e4: 20000018 .word 0x20000018
080050e8 <abort>:
80050e8: b508 push {r3, lr}
80050ea: 2006 movs r0, #6
80050ec: f000 fa00 bl 80054f0 <raise>
80050f0: 2001 movs r0, #1
80050f2: f7fc f88c bl 800120e <_exit>
080050f6 <__sfputc_r>:
80050f6: 6893 ldr r3, [r2, #8]
80050f8: 3b01 subs r3, #1
80050fa: 2b00 cmp r3, #0
80050fc: b410 push {r4}
80050fe: 6093 str r3, [r2, #8]
8005100: da08 bge.n 8005114 <__sfputc_r+0x1e>
8005102: 6994 ldr r4, [r2, #24]
8005104: 42a3 cmp r3, r4
8005106: db01 blt.n 800510c <__sfputc_r+0x16>
8005108: 290a cmp r1, #10
800510a: d103 bne.n 8005114 <__sfputc_r+0x1e>
800510c: f85d 4b04 ldr.w r4, [sp], #4
8005110: f000 b932 b.w 8005378 <__swbuf_r>
8005114: 6813 ldr r3, [r2, #0]
8005116: 1c58 adds r0, r3, #1
8005118: 6010 str r0, [r2, #0]
800511a: 7019 strb r1, [r3, #0]
800511c: 4608 mov r0, r1
800511e: f85d 4b04 ldr.w r4, [sp], #4
8005122: 4770 bx lr
08005124 <__sfputs_r>:
8005124: b5f8 push {r3, r4, r5, r6, r7, lr}
8005126: 4606 mov r6, r0
8005128: 460f mov r7, r1
800512a: 4614 mov r4, r2
800512c: 18d5 adds r5, r2, r3
800512e: 42ac cmp r4, r5
8005130: d101 bne.n 8005136 <__sfputs_r+0x12>
8005132: 2000 movs r0, #0
8005134: e007 b.n 8005146 <__sfputs_r+0x22>
8005136: f814 1b01 ldrb.w r1, [r4], #1
800513a: 463a mov r2, r7
800513c: 4630 mov r0, r6
800513e: f7ff ffda bl 80050f6 <__sfputc_r>
8005142: 1c43 adds r3, r0, #1
8005144: d1f3 bne.n 800512e <__sfputs_r+0xa>
8005146: bdf8 pop {r3, r4, r5, r6, r7, pc}
08005148 <_vfiprintf_r>:
8005148: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800514c: 460d mov r5, r1
800514e: b09d sub sp, #116 @ 0x74
8005150: 4614 mov r4, r2
8005152: 4698 mov r8, r3
8005154: 4606 mov r6, r0
8005156: b118 cbz r0, 8005160 <_vfiprintf_r+0x18>
8005158: 6a03 ldr r3, [r0, #32]
800515a: b90b cbnz r3, 8005160 <_vfiprintf_r+0x18>
800515c: f7fe fac8 bl 80036f0 <__sinit>
8005160: 6e6b ldr r3, [r5, #100] @ 0x64
8005162: 07d9 lsls r1, r3, #31
8005164: d405 bmi.n 8005172 <_vfiprintf_r+0x2a>
8005166: 89ab ldrh r3, [r5, #12]
8005168: 059a lsls r2, r3, #22
800516a: d402 bmi.n 8005172 <_vfiprintf_r+0x2a>
800516c: 6da8 ldr r0, [r5, #88] @ 0x58
800516e: f7fe fbb6 bl 80038de <__retarget_lock_acquire_recursive>
8005172: 89ab ldrh r3, [r5, #12]
8005174: 071b lsls r3, r3, #28
8005176: d501 bpl.n 800517c <_vfiprintf_r+0x34>
8005178: 692b ldr r3, [r5, #16]
800517a: b99b cbnz r3, 80051a4 <_vfiprintf_r+0x5c>
800517c: 4629 mov r1, r5
800517e: 4630 mov r0, r6
8005180: f000 f938 bl 80053f4 <__swsetup_r>
8005184: b170 cbz r0, 80051a4 <_vfiprintf_r+0x5c>
8005186: 6e6b ldr r3, [r5, #100] @ 0x64
8005188: 07dc lsls r4, r3, #31
800518a: d504 bpl.n 8005196 <_vfiprintf_r+0x4e>
800518c: f04f 30ff mov.w r0, #4294967295
8005190: b01d add sp, #116 @ 0x74
8005192: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
8005196: 89ab ldrh r3, [r5, #12]
8005198: 0598 lsls r0, r3, #22
800519a: d4f7 bmi.n 800518c <_vfiprintf_r+0x44>
800519c: 6da8 ldr r0, [r5, #88] @ 0x58
800519e: f7fe fb9f bl 80038e0 <__retarget_lock_release_recursive>
80051a2: e7f3 b.n 800518c <_vfiprintf_r+0x44>
80051a4: 2300 movs r3, #0
80051a6: 9309 str r3, [sp, #36] @ 0x24
80051a8: 2320 movs r3, #32
80051aa: f88d 3029 strb.w r3, [sp, #41] @ 0x29
80051ae: f8cd 800c str.w r8, [sp, #12]
80051b2: 2330 movs r3, #48 @ 0x30
80051b4: f8df 81ac ldr.w r8, [pc, #428] @ 8005364 <_vfiprintf_r+0x21c>
80051b8: f88d 302a strb.w r3, [sp, #42] @ 0x2a
80051bc: f04f 0901 mov.w r9, #1
80051c0: 4623 mov r3, r4
80051c2: 469a mov sl, r3
80051c4: f813 2b01 ldrb.w r2, [r3], #1
80051c8: b10a cbz r2, 80051ce <_vfiprintf_r+0x86>
80051ca: 2a25 cmp r2, #37 @ 0x25
80051cc: d1f9 bne.n 80051c2 <_vfiprintf_r+0x7a>
80051ce: ebba 0b04 subs.w fp, sl, r4
80051d2: d00b beq.n 80051ec <_vfiprintf_r+0xa4>
80051d4: 465b mov r3, fp
80051d6: 4622 mov r2, r4
80051d8: 4629 mov r1, r5
80051da: 4630 mov r0, r6
80051dc: f7ff ffa2 bl 8005124 <__sfputs_r>
80051e0: 3001 adds r0, #1
80051e2: f000 80a7 beq.w 8005334 <_vfiprintf_r+0x1ec>
80051e6: 9a09 ldr r2, [sp, #36] @ 0x24
80051e8: 445a add r2, fp
80051ea: 9209 str r2, [sp, #36] @ 0x24
80051ec: f89a 3000 ldrb.w r3, [sl]
80051f0: 2b00 cmp r3, #0
80051f2: f000 809f beq.w 8005334 <_vfiprintf_r+0x1ec>
80051f6: 2300 movs r3, #0
80051f8: f04f 32ff mov.w r2, #4294967295
80051fc: e9cd 2305 strd r2, r3, [sp, #20]
8005200: f10a 0a01 add.w sl, sl, #1
8005204: 9304 str r3, [sp, #16]
8005206: 9307 str r3, [sp, #28]
8005208: f88d 3053 strb.w r3, [sp, #83] @ 0x53
800520c: 931a str r3, [sp, #104] @ 0x68
800520e: 4654 mov r4, sl
8005210: 2205 movs r2, #5
8005212: f814 1b01 ldrb.w r1, [r4], #1
8005216: 4853 ldr r0, [pc, #332] @ (8005364 <_vfiprintf_r+0x21c>)
8005218: f7fa ffe2 bl 80001e0 <memchr>
800521c: 9a04 ldr r2, [sp, #16]
800521e: b9d8 cbnz r0, 8005258 <_vfiprintf_r+0x110>
8005220: 06d1 lsls r1, r2, #27
8005222: bf44 itt mi
8005224: 2320 movmi r3, #32
8005226: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
800522a: 0713 lsls r3, r2, #28
800522c: bf44 itt mi
800522e: 232b movmi r3, #43 @ 0x2b
8005230: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
8005234: f89a 3000 ldrb.w r3, [sl]
8005238: 2b2a cmp r3, #42 @ 0x2a
800523a: d015 beq.n 8005268 <_vfiprintf_r+0x120>
800523c: 9a07 ldr r2, [sp, #28]
800523e: 4654 mov r4, sl
8005240: 2000 movs r0, #0
8005242: f04f 0c0a mov.w ip, #10
8005246: 4621 mov r1, r4
8005248: f811 3b01 ldrb.w r3, [r1], #1
800524c: 3b30 subs r3, #48 @ 0x30
800524e: 2b09 cmp r3, #9
8005250: d94b bls.n 80052ea <_vfiprintf_r+0x1a2>
8005252: b1b0 cbz r0, 8005282 <_vfiprintf_r+0x13a>
8005254: 9207 str r2, [sp, #28]
8005256: e014 b.n 8005282 <_vfiprintf_r+0x13a>
8005258: eba0 0308 sub.w r3, r0, r8
800525c: fa09 f303 lsl.w r3, r9, r3
8005260: 4313 orrs r3, r2
8005262: 9304 str r3, [sp, #16]
8005264: 46a2 mov sl, r4
8005266: e7d2 b.n 800520e <_vfiprintf_r+0xc6>
8005268: 9b03 ldr r3, [sp, #12]
800526a: 1d19 adds r1, r3, #4
800526c: 681b ldr r3, [r3, #0]
800526e: 9103 str r1, [sp, #12]
8005270: 2b00 cmp r3, #0
8005272: bfbb ittet lt
8005274: 425b neglt r3, r3
8005276: f042 0202 orrlt.w r2, r2, #2
800527a: 9307 strge r3, [sp, #28]
800527c: 9307 strlt r3, [sp, #28]
800527e: bfb8 it lt
8005280: 9204 strlt r2, [sp, #16]
8005282: 7823 ldrb r3, [r4, #0]
8005284: 2b2e cmp r3, #46 @ 0x2e
8005286: d10a bne.n 800529e <_vfiprintf_r+0x156>
8005288: 7863 ldrb r3, [r4, #1]
800528a: 2b2a cmp r3, #42 @ 0x2a
800528c: d132 bne.n 80052f4 <_vfiprintf_r+0x1ac>
800528e: 9b03 ldr r3, [sp, #12]
8005290: 1d1a adds r2, r3, #4
8005292: 681b ldr r3, [r3, #0]
8005294: 9203 str r2, [sp, #12]
8005296: ea43 73e3 orr.w r3, r3, r3, asr #31
800529a: 3402 adds r4, #2
800529c: 9305 str r3, [sp, #20]
800529e: f8df a0d4 ldr.w sl, [pc, #212] @ 8005374 <_vfiprintf_r+0x22c>
80052a2: 7821 ldrb r1, [r4, #0]
80052a4: 2203 movs r2, #3
80052a6: 4650 mov r0, sl
80052a8: f7fa ff9a bl 80001e0 <memchr>
80052ac: b138 cbz r0, 80052be <_vfiprintf_r+0x176>
80052ae: 9b04 ldr r3, [sp, #16]
80052b0: eba0 000a sub.w r0, r0, sl
80052b4: 2240 movs r2, #64 @ 0x40
80052b6: 4082 lsls r2, r0
80052b8: 4313 orrs r3, r2
80052ba: 3401 adds r4, #1
80052bc: 9304 str r3, [sp, #16]
80052be: f814 1b01 ldrb.w r1, [r4], #1
80052c2: 4829 ldr r0, [pc, #164] @ (8005368 <_vfiprintf_r+0x220>)
80052c4: f88d 1028 strb.w r1, [sp, #40] @ 0x28
80052c8: 2206 movs r2, #6
80052ca: f7fa ff89 bl 80001e0 <memchr>
80052ce: 2800 cmp r0, #0
80052d0: d03f beq.n 8005352 <_vfiprintf_r+0x20a>
80052d2: 4b26 ldr r3, [pc, #152] @ (800536c <_vfiprintf_r+0x224>)
80052d4: bb1b cbnz r3, 800531e <_vfiprintf_r+0x1d6>
80052d6: 9b03 ldr r3, [sp, #12]
80052d8: 3307 adds r3, #7
80052da: f023 0307 bic.w r3, r3, #7
80052de: 3308 adds r3, #8
80052e0: 9303 str r3, [sp, #12]
80052e2: 9b09 ldr r3, [sp, #36] @ 0x24
80052e4: 443b add r3, r7
80052e6: 9309 str r3, [sp, #36] @ 0x24
80052e8: e76a b.n 80051c0 <_vfiprintf_r+0x78>
80052ea: fb0c 3202 mla r2, ip, r2, r3
80052ee: 460c mov r4, r1
80052f0: 2001 movs r0, #1
80052f2: e7a8 b.n 8005246 <_vfiprintf_r+0xfe>
80052f4: 2300 movs r3, #0
80052f6: 3401 adds r4, #1
80052f8: 9305 str r3, [sp, #20]
80052fa: 4619 mov r1, r3
80052fc: f04f 0c0a mov.w ip, #10
8005300: 4620 mov r0, r4
8005302: f810 2b01 ldrb.w r2, [r0], #1
8005306: 3a30 subs r2, #48 @ 0x30
8005308: 2a09 cmp r2, #9
800530a: d903 bls.n 8005314 <_vfiprintf_r+0x1cc>
800530c: 2b00 cmp r3, #0
800530e: d0c6 beq.n 800529e <_vfiprintf_r+0x156>
8005310: 9105 str r1, [sp, #20]
8005312: e7c4 b.n 800529e <_vfiprintf_r+0x156>
8005314: fb0c 2101 mla r1, ip, r1, r2
8005318: 4604 mov r4, r0
800531a: 2301 movs r3, #1
800531c: e7f0 b.n 8005300 <_vfiprintf_r+0x1b8>
800531e: ab03 add r3, sp, #12
8005320: 9300 str r3, [sp, #0]
8005322: 462a mov r2, r5
8005324: 4b12 ldr r3, [pc, #72] @ (8005370 <_vfiprintf_r+0x228>)
8005326: a904 add r1, sp, #16
8005328: 4630 mov r0, r6
800532a: f7fd fd9f bl 8002e6c <_printf_float>
800532e: 4607 mov r7, r0
8005330: 1c78 adds r0, r7, #1
8005332: d1d6 bne.n 80052e2 <_vfiprintf_r+0x19a>
8005334: 6e6b ldr r3, [r5, #100] @ 0x64
8005336: 07d9 lsls r1, r3, #31
8005338: d405 bmi.n 8005346 <_vfiprintf_r+0x1fe>
800533a: 89ab ldrh r3, [r5, #12]
800533c: 059a lsls r2, r3, #22
800533e: d402 bmi.n 8005346 <_vfiprintf_r+0x1fe>
8005340: 6da8 ldr r0, [r5, #88] @ 0x58
8005342: f7fe facd bl 80038e0 <__retarget_lock_release_recursive>
8005346: 89ab ldrh r3, [r5, #12]
8005348: 065b lsls r3, r3, #25
800534a: f53f af1f bmi.w 800518c <_vfiprintf_r+0x44>
800534e: 9809 ldr r0, [sp, #36] @ 0x24
8005350: e71e b.n 8005190 <_vfiprintf_r+0x48>
8005352: ab03 add r3, sp, #12
8005354: 9300 str r3, [sp, #0]
8005356: 462a mov r2, r5
8005358: 4b05 ldr r3, [pc, #20] @ (8005370 <_vfiprintf_r+0x228>)
800535a: a904 add r1, sp, #16
800535c: 4630 mov r0, r6
800535e: f7fe f81d bl 800339c <_printf_i>
8005362: e7e4 b.n 800532e <_vfiprintf_r+0x1e6>
8005364: 080057e8 .word 0x080057e8
8005368: 080057f2 .word 0x080057f2
800536c: 08002e6d .word 0x08002e6d
8005370: 08005125 .word 0x08005125
8005374: 080057ee .word 0x080057ee
08005378 <__swbuf_r>:
8005378: b5f8 push {r3, r4, r5, r6, r7, lr}
800537a: 460e mov r6, r1
800537c: 4614 mov r4, r2
800537e: 4605 mov r5, r0
8005380: b118 cbz r0, 800538a <__swbuf_r+0x12>
8005382: 6a03 ldr r3, [r0, #32]
8005384: b90b cbnz r3, 800538a <__swbuf_r+0x12>
8005386: f7fe f9b3 bl 80036f0 <__sinit>
800538a: 69a3 ldr r3, [r4, #24]
800538c: 60a3 str r3, [r4, #8]
800538e: 89a3 ldrh r3, [r4, #12]
8005390: 071a lsls r2, r3, #28
8005392: d501 bpl.n 8005398 <__swbuf_r+0x20>
8005394: 6923 ldr r3, [r4, #16]
8005396: b943 cbnz r3, 80053aa <__swbuf_r+0x32>
8005398: 4621 mov r1, r4
800539a: 4628 mov r0, r5
800539c: f000 f82a bl 80053f4 <__swsetup_r>
80053a0: b118 cbz r0, 80053aa <__swbuf_r+0x32>
80053a2: f04f 37ff mov.w r7, #4294967295
80053a6: 4638 mov r0, r7
80053a8: bdf8 pop {r3, r4, r5, r6, r7, pc}
80053aa: 6823 ldr r3, [r4, #0]
80053ac: 6922 ldr r2, [r4, #16]
80053ae: 1a98 subs r0, r3, r2
80053b0: 6963 ldr r3, [r4, #20]
80053b2: b2f6 uxtb r6, r6
80053b4: 4283 cmp r3, r0
80053b6: 4637 mov r7, r6
80053b8: dc05 bgt.n 80053c6 <__swbuf_r+0x4e>
80053ba: 4621 mov r1, r4
80053bc: 4628 mov r0, r5
80053be: f7ff fde9 bl 8004f94 <_fflush_r>
80053c2: 2800 cmp r0, #0
80053c4: d1ed bne.n 80053a2 <__swbuf_r+0x2a>
80053c6: 68a3 ldr r3, [r4, #8]
80053c8: 3b01 subs r3, #1
80053ca: 60a3 str r3, [r4, #8]
80053cc: 6823 ldr r3, [r4, #0]
80053ce: 1c5a adds r2, r3, #1
80053d0: 6022 str r2, [r4, #0]
80053d2: 701e strb r6, [r3, #0]
80053d4: 6962 ldr r2, [r4, #20]
80053d6: 1c43 adds r3, r0, #1
80053d8: 429a cmp r2, r3
80053da: d004 beq.n 80053e6 <__swbuf_r+0x6e>
80053dc: 89a3 ldrh r3, [r4, #12]
80053de: 07db lsls r3, r3, #31
80053e0: d5e1 bpl.n 80053a6 <__swbuf_r+0x2e>
80053e2: 2e0a cmp r6, #10
80053e4: d1df bne.n 80053a6 <__swbuf_r+0x2e>
80053e6: 4621 mov r1, r4
80053e8: 4628 mov r0, r5
80053ea: f7ff fdd3 bl 8004f94 <_fflush_r>
80053ee: 2800 cmp r0, #0
80053f0: d0d9 beq.n 80053a6 <__swbuf_r+0x2e>
80053f2: e7d6 b.n 80053a2 <__swbuf_r+0x2a>
080053f4 <__swsetup_r>:
80053f4: b538 push {r3, r4, r5, lr}
80053f6: 4b29 ldr r3, [pc, #164] @ (800549c <__swsetup_r+0xa8>)
80053f8: 4605 mov r5, r0
80053fa: 6818 ldr r0, [r3, #0]
80053fc: 460c mov r4, r1
80053fe: b118 cbz r0, 8005408 <__swsetup_r+0x14>
8005400: 6a03 ldr r3, [r0, #32]
8005402: b90b cbnz r3, 8005408 <__swsetup_r+0x14>
8005404: f7fe f974 bl 80036f0 <__sinit>
8005408: f9b4 300c ldrsh.w r3, [r4, #12]
800540c: 0719 lsls r1, r3, #28
800540e: d422 bmi.n 8005456 <__swsetup_r+0x62>
8005410: 06da lsls r2, r3, #27
8005412: d407 bmi.n 8005424 <__swsetup_r+0x30>
8005414: 2209 movs r2, #9
8005416: 602a str r2, [r5, #0]
8005418: f043 0340 orr.w r3, r3, #64 @ 0x40
800541c: 81a3 strh r3, [r4, #12]
800541e: f04f 30ff mov.w r0, #4294967295
8005422: e033 b.n 800548c <__swsetup_r+0x98>
8005424: 0758 lsls r0, r3, #29
8005426: d512 bpl.n 800544e <__swsetup_r+0x5a>
8005428: 6b61 ldr r1, [r4, #52] @ 0x34
800542a: b141 cbz r1, 800543e <__swsetup_r+0x4a>
800542c: f104 0344 add.w r3, r4, #68 @ 0x44
8005430: 4299 cmp r1, r3
8005432: d002 beq.n 800543a <__swsetup_r+0x46>
8005434: 4628 mov r0, r5
8005436: f7ff f8af bl 8004598 <_free_r>
800543a: 2300 movs r3, #0
800543c: 6363 str r3, [r4, #52] @ 0x34
800543e: 89a3 ldrh r3, [r4, #12]
8005440: f023 0324 bic.w r3, r3, #36 @ 0x24
8005444: 81a3 strh r3, [r4, #12]
8005446: 2300 movs r3, #0
8005448: 6063 str r3, [r4, #4]
800544a: 6923 ldr r3, [r4, #16]
800544c: 6023 str r3, [r4, #0]
800544e: 89a3 ldrh r3, [r4, #12]
8005450: f043 0308 orr.w r3, r3, #8
8005454: 81a3 strh r3, [r4, #12]
8005456: 6923 ldr r3, [r4, #16]
8005458: b94b cbnz r3, 800546e <__swsetup_r+0x7a>
800545a: 89a3 ldrh r3, [r4, #12]
800545c: f403 7320 and.w r3, r3, #640 @ 0x280
8005460: f5b3 7f00 cmp.w r3, #512 @ 0x200
8005464: d003 beq.n 800546e <__swsetup_r+0x7a>
8005466: 4621 mov r1, r4
8005468: 4628 mov r0, r5
800546a: f000 f883 bl 8005574 <__smakebuf_r>
800546e: f9b4 300c ldrsh.w r3, [r4, #12]
8005472: f013 0201 ands.w r2, r3, #1
8005476: d00a beq.n 800548e <__swsetup_r+0x9a>
8005478: 2200 movs r2, #0
800547a: 60a2 str r2, [r4, #8]
800547c: 6962 ldr r2, [r4, #20]
800547e: 4252 negs r2, r2
8005480: 61a2 str r2, [r4, #24]
8005482: 6922 ldr r2, [r4, #16]
8005484: b942 cbnz r2, 8005498 <__swsetup_r+0xa4>
8005486: f013 0080 ands.w r0, r3, #128 @ 0x80
800548a: d1c5 bne.n 8005418 <__swsetup_r+0x24>
800548c: bd38 pop {r3, r4, r5, pc}
800548e: 0799 lsls r1, r3, #30
8005490: bf58 it pl
8005492: 6962 ldrpl r2, [r4, #20]
8005494: 60a2 str r2, [r4, #8]
8005496: e7f4 b.n 8005482 <__swsetup_r+0x8e>
8005498: 2000 movs r0, #0
800549a: e7f7 b.n 800548c <__swsetup_r+0x98>
800549c: 20000018 .word 0x20000018
080054a0 <_raise_r>:
80054a0: 291f cmp r1, #31
80054a2: b538 push {r3, r4, r5, lr}
80054a4: 4605 mov r5, r0
80054a6: 460c mov r4, r1
80054a8: d904 bls.n 80054b4 <_raise_r+0x14>
80054aa: 2316 movs r3, #22
80054ac: 6003 str r3, [r0, #0]
80054ae: f04f 30ff mov.w r0, #4294967295
80054b2: bd38 pop {r3, r4, r5, pc}
80054b4: 6bc2 ldr r2, [r0, #60] @ 0x3c
80054b6: b112 cbz r2, 80054be <_raise_r+0x1e>
80054b8: f852 3021 ldr.w r3, [r2, r1, lsl #2]
80054bc: b94b cbnz r3, 80054d2 <_raise_r+0x32>
80054be: 4628 mov r0, r5
80054c0: f000 f830 bl 8005524 <_getpid_r>
80054c4: 4622 mov r2, r4
80054c6: 4601 mov r1, r0
80054c8: 4628 mov r0, r5
80054ca: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
80054ce: f000 b817 b.w 8005500 <_kill_r>
80054d2: 2b01 cmp r3, #1
80054d4: d00a beq.n 80054ec <_raise_r+0x4c>
80054d6: 1c59 adds r1, r3, #1
80054d8: d103 bne.n 80054e2 <_raise_r+0x42>
80054da: 2316 movs r3, #22
80054dc: 6003 str r3, [r0, #0]
80054de: 2001 movs r0, #1
80054e0: e7e7 b.n 80054b2 <_raise_r+0x12>
80054e2: 2100 movs r1, #0
80054e4: f842 1024 str.w r1, [r2, r4, lsl #2]
80054e8: 4620 mov r0, r4
80054ea: 4798 blx r3
80054ec: 2000 movs r0, #0
80054ee: e7e0 b.n 80054b2 <_raise_r+0x12>
080054f0 <raise>:
80054f0: 4b02 ldr r3, [pc, #8] @ (80054fc <raise+0xc>)
80054f2: 4601 mov r1, r0
80054f4: 6818 ldr r0, [r3, #0]
80054f6: f7ff bfd3 b.w 80054a0 <_raise_r>
80054fa: bf00 nop
80054fc: 20000018 .word 0x20000018
08005500 <_kill_r>:
8005500: b538 push {r3, r4, r5, lr}
8005502: 4d07 ldr r5, [pc, #28] @ (8005520 <_kill_r+0x20>)
8005504: 2300 movs r3, #0
8005506: 4604 mov r4, r0
8005508: 4608 mov r0, r1
800550a: 4611 mov r1, r2
800550c: 602b str r3, [r5, #0]
800550e: f7fb fe6e bl 80011ee <_kill>
8005512: 1c43 adds r3, r0, #1
8005514: d102 bne.n 800551c <_kill_r+0x1c>
8005516: 682b ldr r3, [r5, #0]
8005518: b103 cbz r3, 800551c <_kill_r+0x1c>
800551a: 6023 str r3, [r4, #0]
800551c: bd38 pop {r3, r4, r5, pc}
800551e: bf00 nop
8005520: 2000079c .word 0x2000079c
08005524 <_getpid_r>:
8005524: f7fb be5b b.w 80011de <_getpid>
08005528 <__swhatbuf_r>:
8005528: b570 push {r4, r5, r6, lr}
800552a: 460c mov r4, r1
800552c: f9b1 100e ldrsh.w r1, [r1, #14]
8005530: 2900 cmp r1, #0
8005532: b096 sub sp, #88 @ 0x58
8005534: 4615 mov r5, r2
8005536: 461e mov r6, r3
8005538: da0d bge.n 8005556 <__swhatbuf_r+0x2e>
800553a: 89a3 ldrh r3, [r4, #12]
800553c: f013 0f80 tst.w r3, #128 @ 0x80
8005540: f04f 0100 mov.w r1, #0
8005544: bf14 ite ne
8005546: 2340 movne r3, #64 @ 0x40
8005548: f44f 6380 moveq.w r3, #1024 @ 0x400
800554c: 2000 movs r0, #0
800554e: 6031 str r1, [r6, #0]
8005550: 602b str r3, [r5, #0]
8005552: b016 add sp, #88 @ 0x58
8005554: bd70 pop {r4, r5, r6, pc}
8005556: 466a mov r2, sp
8005558: f000 f848 bl 80055ec <_fstat_r>
800555c: 2800 cmp r0, #0
800555e: dbec blt.n 800553a <__swhatbuf_r+0x12>
8005560: 9901 ldr r1, [sp, #4]
8005562: f401 4170 and.w r1, r1, #61440 @ 0xf000
8005566: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000
800556a: 4259 negs r1, r3
800556c: 4159 adcs r1, r3
800556e: f44f 6380 mov.w r3, #1024 @ 0x400
8005572: e7eb b.n 800554c <__swhatbuf_r+0x24>
08005574 <__smakebuf_r>:
8005574: 898b ldrh r3, [r1, #12]
8005576: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
8005578: 079d lsls r5, r3, #30
800557a: 4606 mov r6, r0
800557c: 460c mov r4, r1
800557e: d507 bpl.n 8005590 <__smakebuf_r+0x1c>
8005580: f104 0347 add.w r3, r4, #71 @ 0x47
8005584: 6023 str r3, [r4, #0]
8005586: 6123 str r3, [r4, #16]
8005588: 2301 movs r3, #1
800558a: 6163 str r3, [r4, #20]
800558c: b003 add sp, #12
800558e: bdf0 pop {r4, r5, r6, r7, pc}
8005590: ab01 add r3, sp, #4
8005592: 466a mov r2, sp
8005594: f7ff ffc8 bl 8005528 <__swhatbuf_r>
8005598: 9f00 ldr r7, [sp, #0]
800559a: 4605 mov r5, r0
800559c: 4639 mov r1, r7
800559e: 4630 mov r0, r6
80055a0: f7ff f86e bl 8004680 <_malloc_r>
80055a4: b948 cbnz r0, 80055ba <__smakebuf_r+0x46>
80055a6: f9b4 300c ldrsh.w r3, [r4, #12]
80055aa: 059a lsls r2, r3, #22
80055ac: d4ee bmi.n 800558c <__smakebuf_r+0x18>
80055ae: f023 0303 bic.w r3, r3, #3
80055b2: f043 0302 orr.w r3, r3, #2
80055b6: 81a3 strh r3, [r4, #12]
80055b8: e7e2 b.n 8005580 <__smakebuf_r+0xc>
80055ba: 89a3 ldrh r3, [r4, #12]
80055bc: 6020 str r0, [r4, #0]
80055be: f043 0380 orr.w r3, r3, #128 @ 0x80
80055c2: 81a3 strh r3, [r4, #12]
80055c4: 9b01 ldr r3, [sp, #4]
80055c6: e9c4 0704 strd r0, r7, [r4, #16]
80055ca: b15b cbz r3, 80055e4 <__smakebuf_r+0x70>
80055cc: f9b4 100e ldrsh.w r1, [r4, #14]
80055d0: 4630 mov r0, r6
80055d2: f000 f81d bl 8005610 <_isatty_r>
80055d6: b128 cbz r0, 80055e4 <__smakebuf_r+0x70>
80055d8: 89a3 ldrh r3, [r4, #12]
80055da: f023 0303 bic.w r3, r3, #3
80055de: f043 0301 orr.w r3, r3, #1
80055e2: 81a3 strh r3, [r4, #12]
80055e4: 89a3 ldrh r3, [r4, #12]
80055e6: 431d orrs r5, r3
80055e8: 81a5 strh r5, [r4, #12]
80055ea: e7cf b.n 800558c <__smakebuf_r+0x18>
080055ec <_fstat_r>:
80055ec: b538 push {r3, r4, r5, lr}
80055ee: 4d07 ldr r5, [pc, #28] @ (800560c <_fstat_r+0x20>)
80055f0: 2300 movs r3, #0
80055f2: 4604 mov r4, r0
80055f4: 4608 mov r0, r1
80055f6: 4611 mov r1, r2
80055f8: 602b str r3, [r5, #0]
80055fa: f7fb fe58 bl 80012ae <_fstat>
80055fe: 1c43 adds r3, r0, #1
8005600: d102 bne.n 8005608 <_fstat_r+0x1c>
8005602: 682b ldr r3, [r5, #0]
8005604: b103 cbz r3, 8005608 <_fstat_r+0x1c>
8005606: 6023 str r3, [r4, #0]
8005608: bd38 pop {r3, r4, r5, pc}
800560a: bf00 nop
800560c: 2000079c .word 0x2000079c
08005610 <_isatty_r>:
8005610: b538 push {r3, r4, r5, lr}
8005612: 4d06 ldr r5, [pc, #24] @ (800562c <_isatty_r+0x1c>)
8005614: 2300 movs r3, #0
8005616: 4604 mov r4, r0
8005618: 4608 mov r0, r1
800561a: 602b str r3, [r5, #0]
800561c: f7fb fe57 bl 80012ce <_isatty>
8005620: 1c43 adds r3, r0, #1
8005622: d102 bne.n 800562a <_isatty_r+0x1a>
8005624: 682b ldr r3, [r5, #0]
8005626: b103 cbz r3, 800562a <_isatty_r+0x1a>
8005628: 6023 str r3, [r4, #0]
800562a: bd38 pop {r3, r4, r5, pc}
800562c: 2000079c .word 0x2000079c
08005630 <_init>:
8005630: b5f8 push {r3, r4, r5, r6, r7, lr}
8005632: bf00 nop
8005634: bcf8 pop {r3, r4, r5, r6, r7}
8005636: bc08 pop {r3}
8005638: 469e mov lr, r3
800563a: 4770 bx lr
0800563c <_fini>:
800563c: b5f8 push {r3, r4, r5, r6, r7, lr}
800563e: bf00 nop
8005640: bcf8 pop {r3, r4, r5, r6, r7}
8005642: bc08 pop {r3}
8005644: 469e mov lr, r3
8005646: 4770 bx lr
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