stm32-moto/Debug/moto-perf.list

moto-perf.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   00000194  08000000  08000000  00001000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         0000b58c  080001a0  080001a0  000011a0  2**4
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       000009a4  0800b730  0800b730  0000c730  2**3
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .ARM.extab    00000000  0800c0d4  0800c0d4  0000e1d4  2**0
                  CONTENTS, READONLY
  4 .ARM          00000008  0800c0d4  0800c0d4  0000d0d4  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  5 .preinit_array 00000000  0800c0dc  0800c0dc  0000e1d4  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  6 .init_array   00000004  0800c0dc  0800c0dc  0000d0dc  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  7 .fini_array   00000004  0800c0e0  0800c0e0  0000d0e0  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  8 .data         000001d4  20000000  0800c0e4  0000e000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  9 .bss          0000031c  200001d4  0800c2b8  0000e1d4  2**2
                  ALLOC
 10 ._user_heap_stack 00000c00  200004f0  0800c2b8  0000e4f0  2**0
                  ALLOC
 11 .ARM.attributes 00000030  00000000  00000000  0000e1d4  2**0
                  CONTENTS, READONLY
 12 .debug_info   0001083b  00000000  00000000  0000e204  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 13 .debug_abbrev 00002713  00000000  00000000  0001ea3f  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 14 .debug_aranges 00000ec8  00000000  00000000  00021158  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 15 .debug_rnglists 00000b71  00000000  00000000  00022020  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 16 .debug_macro  0002408b  00000000  00000000  00022b91  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 17 .debug_line   00012411  00000000  00000000  00046c1c  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 18 .debug_str    000d3fc4  00000000  00000000  0005902d  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 19 .comment      00000043  00000000  00000000  0012cff1  2**0
                  CONTENTS, READONLY
 20 .debug_frame  00005328  00000000  00000000  0012d034  2**2
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 21 .debug_line_str 00000063  00000000  00000000  0013235c  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS

Disassembly of section .text:

080001a0 <__do_global_dtors_aux>:
 80001a0:	b510      	push	{r4, lr}
 80001a2:	4c05      	ldr	r4, [pc, #20]	@ (80001b8 <__do_global_dtors_aux+0x18>)
 80001a4:	7823      	ldrb	r3, [r4, #0]
 80001a6:	b933      	cbnz	r3, 80001b6 <__do_global_dtors_aux+0x16>
 80001a8:	4b04      	ldr	r3, [pc, #16]	@ (80001bc <__do_global_dtors_aux+0x1c>)
 80001aa:	b113      	cbz	r3, 80001b2 <__do_global_dtors_aux+0x12>
 80001ac:	4804      	ldr	r0, [pc, #16]	@ (80001c0 <__do_global_dtors_aux+0x20>)
 80001ae:	f3af 8000 	nop.w
 80001b2:	2301      	movs	r3, #1
 80001b4:	7023      	strb	r3, [r4, #0]
 80001b6:	bd10      	pop	{r4, pc}
 80001b8:	200001d4 	.word	0x200001d4
 80001bc:	00000000 	.word	0x00000000
 80001c0:	0800b714 	.word	0x0800b714

080001c4 <frame_dummy>:
 80001c4:	b508      	push	{r3, lr}
 80001c6:	4b03      	ldr	r3, [pc, #12]	@ (80001d4 <frame_dummy+0x10>)
 80001c8:	b11b      	cbz	r3, 80001d2 <frame_dummy+0xe>
 80001ca:	4903      	ldr	r1, [pc, #12]	@ (80001d8 <frame_dummy+0x14>)
 80001cc:	4803      	ldr	r0, [pc, #12]	@ (80001dc <frame_dummy+0x18>)
 80001ce:	f3af 8000 	nop.w
 80001d2:	bd08      	pop	{r3, pc}
 80001d4:	00000000 	.word	0x00000000
 80001d8:	200001d8 	.word	0x200001d8
 80001dc:	0800b714 	.word	0x0800b714

080001e0 <memchr>:
 80001e0:	f001 01ff 	and.w	r1, r1, #255	@ 0xff
 80001e4:	2a10      	cmp	r2, #16
 80001e6:	db2b      	blt.n	8000240 <memchr+0x60>
 80001e8:	f010 0f07 	tst.w	r0, #7
 80001ec:	d008      	beq.n	8000200 <memchr+0x20>
 80001ee:	f810 3b01 	ldrb.w	r3, [r0], #1
 80001f2:	3a01      	subs	r2, #1
 80001f4:	428b      	cmp	r3, r1
 80001f6:	d02d      	beq.n	8000254 <memchr+0x74>
 80001f8:	f010 0f07 	tst.w	r0, #7
 80001fc:	b342      	cbz	r2, 8000250 <memchr+0x70>
 80001fe:	d1f6      	bne.n	80001ee <memchr+0xe>
 8000200:	b4f0      	push	{r4, r5, r6, r7}
 8000202:	ea41 2101 	orr.w	r1, r1, r1, lsl #8
 8000206:	ea41 4101 	orr.w	r1, r1, r1, lsl #16
 800020a:	f022 0407 	bic.w	r4, r2, #7
 800020e:	f07f 0700 	mvns.w	r7, #0
 8000212:	2300      	movs	r3, #0
 8000214:	e8f0 5602 	ldrd	r5, r6, [r0], #8
 8000218:	3c08      	subs	r4, #8
 800021a:	ea85 0501 	eor.w	r5, r5, r1
 800021e:	ea86 0601 	eor.w	r6, r6, r1
 8000222:	fa85 f547 	uadd8	r5, r5, r7
 8000226:	faa3 f587 	sel	r5, r3, r7
 800022a:	fa86 f647 	uadd8	r6, r6, r7
 800022e:	faa5 f687 	sel	r6, r5, r7
 8000232:	b98e      	cbnz	r6, 8000258 <memchr+0x78>
 8000234:	d1ee      	bne.n	8000214 <memchr+0x34>
 8000236:	bcf0      	pop	{r4, r5, r6, r7}
 8000238:	f001 01ff 	and.w	r1, r1, #255	@ 0xff
 800023c:	f002 0207 	and.w	r2, r2, #7
 8000240:	b132      	cbz	r2, 8000250 <memchr+0x70>
 8000242:	f810 3b01 	ldrb.w	r3, [r0], #1
 8000246:	3a01      	subs	r2, #1
 8000248:	ea83 0301 	eor.w	r3, r3, r1
 800024c:	b113      	cbz	r3, 8000254 <memchr+0x74>
 800024e:	d1f8      	bne.n	8000242 <memchr+0x62>
 8000250:	2000      	movs	r0, #0
 8000252:	4770      	bx	lr
 8000254:	3801      	subs	r0, #1
 8000256:	4770      	bx	lr
 8000258:	2d00      	cmp	r5, #0
 800025a:	bf06      	itte	eq
 800025c:	4635      	moveq	r5, r6
 800025e:	3803      	subeq	r0, #3
 8000260:	3807      	subne	r0, #7
 8000262:	f015 0f01 	tst.w	r5, #1
 8000266:	d107      	bne.n	8000278 <memchr+0x98>
 8000268:	3001      	adds	r0, #1
 800026a:	f415 7f80 	tst.w	r5, #256	@ 0x100
 800026e:	bf02      	ittt	eq
 8000270:	3001      	addeq	r0, #1
 8000272:	f415 3fc0 	tsteq.w	r5, #98304	@ 0x18000
 8000276:	3001      	addeq	r0, #1
 8000278:	bcf0      	pop	{r4, r5, r6, r7}
 800027a:	3801      	subs	r0, #1
 800027c:	4770      	bx	lr
 800027e:	bf00      	nop

08000280 <strlen>:
 8000280:	4603      	mov	r3, r0
 8000282:	f813 2b01 	ldrb.w	r2, [r3], #1
 8000286:	2a00      	cmp	r2, #0
 8000288:	d1fb      	bne.n	8000282 <strlen+0x2>
 800028a:	1a18      	subs	r0, r3, r0
 800028c:	3801      	subs	r0, #1
 800028e:	4770      	bx	lr

08000290 <__aeabi_drsub>:
 8000290:	f081 4100 	eor.w	r1, r1, #2147483648	@ 0x80000000
 8000294:	e002      	b.n	800029c <__adddf3>
 8000296:	bf00      	nop

08000298 <__aeabi_dsub>:
 8000298:	f083 4300 	eor.w	r3, r3, #2147483648	@ 0x80000000

0800029c <__adddf3>:
 800029c:	b530      	push	{r4, r5, lr}
 800029e:	ea4f 0441 	mov.w	r4, r1, lsl #1
 80002a2:	ea4f 0543 	mov.w	r5, r3, lsl #1
 80002a6:	ea94 0f05 	teq	r4, r5
 80002aa:	bf08      	it	eq
 80002ac:	ea90 0f02 	teqeq	r0, r2
 80002b0:	bf1f      	itttt	ne
 80002b2:	ea54 0c00 	orrsne.w	ip, r4, r0
 80002b6:	ea55 0c02 	orrsne.w	ip, r5, r2
 80002ba:	ea7f 5c64 	mvnsne.w	ip, r4, asr #21
 80002be:	ea7f 5c65 	mvnsne.w	ip, r5, asr #21
 80002c2:	f000 80e2 	beq.w	800048a <__adddf3+0x1ee>
 80002c6:	ea4f 5454 	mov.w	r4, r4, lsr #21
 80002ca:	ebd4 5555 	rsbs	r5, r4, r5, lsr #21
 80002ce:	bfb8      	it	lt
 80002d0:	426d      	neglt	r5, r5
 80002d2:	dd0c      	ble.n	80002ee <__adddf3+0x52>
 80002d4:	442c      	add	r4, r5
 80002d6:	ea80 0202 	eor.w	r2, r0, r2
 80002da:	ea81 0303 	eor.w	r3, r1, r3
 80002de:	ea82 0000 	eor.w	r0, r2, r0
 80002e2:	ea83 0101 	eor.w	r1, r3, r1
 80002e6:	ea80 0202 	eor.w	r2, r0, r2
 80002ea:	ea81 0303 	eor.w	r3, r1, r3
 80002ee:	2d36      	cmp	r5, #54	@ 0x36
 80002f0:	bf88      	it	hi
 80002f2:	bd30      	pophi	{r4, r5, pc}
 80002f4:	f011 4f00 	tst.w	r1, #2147483648	@ 0x80000000
 80002f8:	ea4f 3101 	mov.w	r1, r1, lsl #12
 80002fc:	f44f 1c80 	mov.w	ip, #1048576	@ 0x100000
 8000300:	ea4c 3111 	orr.w	r1, ip, r1, lsr #12
 8000304:	d002      	beq.n	800030c <__adddf3+0x70>
 8000306:	4240      	negs	r0, r0
 8000308:	eb61 0141 	sbc.w	r1, r1, r1, lsl #1
 800030c:	f013 4f00 	tst.w	r3, #2147483648	@ 0x80000000
 8000310:	ea4f 3303 	mov.w	r3, r3, lsl #12
 8000314:	ea4c 3313 	orr.w	r3, ip, r3, lsr #12
 8000318:	d002      	beq.n	8000320 <__adddf3+0x84>
 800031a:	4252      	negs	r2, r2
 800031c:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
 8000320:	ea94 0f05 	teq	r4, r5
 8000324:	f000 80a7 	beq.w	8000476 <__adddf3+0x1da>
 8000328:	f1a4 0401 	sub.w	r4, r4, #1
 800032c:	f1d5 0e20 	rsbs	lr, r5, #32
 8000330:	db0d      	blt.n	800034e <__adddf3+0xb2>
 8000332:	fa02 fc0e 	lsl.w	ip, r2, lr
 8000336:	fa22 f205 	lsr.w	r2, r2, r5
 800033a:	1880      	adds	r0, r0, r2
 800033c:	f141 0100 	adc.w	r1, r1, #0
 8000340:	fa03 f20e 	lsl.w	r2, r3, lr
 8000344:	1880      	adds	r0, r0, r2
 8000346:	fa43 f305 	asr.w	r3, r3, r5
 800034a:	4159      	adcs	r1, r3
 800034c:	e00e      	b.n	800036c <__adddf3+0xd0>
 800034e:	f1a5 0520 	sub.w	r5, r5, #32
 8000352:	f10e 0e20 	add.w	lr, lr, #32
 8000356:	2a01      	cmp	r2, #1
 8000358:	fa03 fc0e 	lsl.w	ip, r3, lr
 800035c:	bf28      	it	cs
 800035e:	f04c 0c02 	orrcs.w	ip, ip, #2
 8000362:	fa43 f305 	asr.w	r3, r3, r5
 8000366:	18c0      	adds	r0, r0, r3
 8000368:	eb51 71e3 	adcs.w	r1, r1, r3, asr #31
 800036c:	f001 4500 	and.w	r5, r1, #2147483648	@ 0x80000000
 8000370:	d507      	bpl.n	8000382 <__adddf3+0xe6>
 8000372:	f04f 0e00 	mov.w	lr, #0
 8000376:	f1dc 0c00 	rsbs	ip, ip, #0
 800037a:	eb7e 0000 	sbcs.w	r0, lr, r0
 800037e:	eb6e 0101 	sbc.w	r1, lr, r1
 8000382:	f5b1 1f80 	cmp.w	r1, #1048576	@ 0x100000
 8000386:	d31b      	bcc.n	80003c0 <__adddf3+0x124>
 8000388:	f5b1 1f00 	cmp.w	r1, #2097152	@ 0x200000
 800038c:	d30c      	bcc.n	80003a8 <__adddf3+0x10c>
 800038e:	0849      	lsrs	r1, r1, #1
 8000390:	ea5f 0030 	movs.w	r0, r0, rrx
 8000394:	ea4f 0c3c 	mov.w	ip, ip, rrx
 8000398:	f104 0401 	add.w	r4, r4, #1
 800039c:	ea4f 5244 	mov.w	r2, r4, lsl #21
 80003a0:	f512 0f80 	cmn.w	r2, #4194304	@ 0x400000
 80003a4:	f080 809a 	bcs.w	80004dc <__adddf3+0x240>
 80003a8:	f1bc 4f00 	cmp.w	ip, #2147483648	@ 0x80000000
 80003ac:	bf08      	it	eq
 80003ae:	ea5f 0c50 	movseq.w	ip, r0, lsr #1
 80003b2:	f150 0000 	adcs.w	r0, r0, #0
 80003b6:	eb41 5104 	adc.w	r1, r1, r4, lsl #20
 80003ba:	ea41 0105 	orr.w	r1, r1, r5
 80003be:	bd30      	pop	{r4, r5, pc}
 80003c0:	ea5f 0c4c 	movs.w	ip, ip, lsl #1
 80003c4:	4140      	adcs	r0, r0
 80003c6:	eb41 0101 	adc.w	r1, r1, r1
 80003ca:	3c01      	subs	r4, #1
 80003cc:	bf28      	it	cs
 80003ce:	f5b1 1f80 	cmpcs.w	r1, #1048576	@ 0x100000
 80003d2:	d2e9      	bcs.n	80003a8 <__adddf3+0x10c>
 80003d4:	f091 0f00 	teq	r1, #0
 80003d8:	bf04      	itt	eq
 80003da:	4601      	moveq	r1, r0
 80003dc:	2000      	moveq	r0, #0
 80003de:	fab1 f381 	clz	r3, r1
 80003e2:	bf08      	it	eq
 80003e4:	3320      	addeq	r3, #32
 80003e6:	f1a3 030b 	sub.w	r3, r3, #11
 80003ea:	f1b3 0220 	subs.w	r2, r3, #32
 80003ee:	da0c      	bge.n	800040a <__adddf3+0x16e>
 80003f0:	320c      	adds	r2, #12
 80003f2:	dd08      	ble.n	8000406 <__adddf3+0x16a>
 80003f4:	f102 0c14 	add.w	ip, r2, #20
 80003f8:	f1c2 020c 	rsb	r2, r2, #12
 80003fc:	fa01 f00c 	lsl.w	r0, r1, ip
 8000400:	fa21 f102 	lsr.w	r1, r1, r2
 8000404:	e00c      	b.n	8000420 <__adddf3+0x184>
 8000406:	f102 0214 	add.w	r2, r2, #20
 800040a:	bfd8      	it	le
 800040c:	f1c2 0c20 	rsble	ip, r2, #32
 8000410:	fa01 f102 	lsl.w	r1, r1, r2
 8000414:	fa20 fc0c 	lsr.w	ip, r0, ip
 8000418:	bfdc      	itt	le
 800041a:	ea41 010c 	orrle.w	r1, r1, ip
 800041e:	4090      	lslle	r0, r2
 8000420:	1ae4      	subs	r4, r4, r3
 8000422:	bfa2      	ittt	ge
 8000424:	eb01 5104 	addge.w	r1, r1, r4, lsl #20
 8000428:	4329      	orrge	r1, r5
 800042a:	bd30      	popge	{r4, r5, pc}
 800042c:	ea6f 0404 	mvn.w	r4, r4
 8000430:	3c1f      	subs	r4, #31
 8000432:	da1c      	bge.n	800046e <__adddf3+0x1d2>
 8000434:	340c      	adds	r4, #12
 8000436:	dc0e      	bgt.n	8000456 <__adddf3+0x1ba>
 8000438:	f104 0414 	add.w	r4, r4, #20
 800043c:	f1c4 0220 	rsb	r2, r4, #32
 8000440:	fa20 f004 	lsr.w	r0, r0, r4
 8000444:	fa01 f302 	lsl.w	r3, r1, r2
 8000448:	ea40 0003 	orr.w	r0, r0, r3
 800044c:	fa21 f304 	lsr.w	r3, r1, r4
 8000450:	ea45 0103 	orr.w	r1, r5, r3
 8000454:	bd30      	pop	{r4, r5, pc}
 8000456:	f1c4 040c 	rsb	r4, r4, #12
 800045a:	f1c4 0220 	rsb	r2, r4, #32
 800045e:	fa20 f002 	lsr.w	r0, r0, r2
 8000462:	fa01 f304 	lsl.w	r3, r1, r4
 8000466:	ea40 0003 	orr.w	r0, r0, r3
 800046a:	4629      	mov	r1, r5
 800046c:	bd30      	pop	{r4, r5, pc}
 800046e:	fa21 f004 	lsr.w	r0, r1, r4
 8000472:	4629      	mov	r1, r5
 8000474:	bd30      	pop	{r4, r5, pc}
 8000476:	f094 0f00 	teq	r4, #0
 800047a:	f483 1380 	eor.w	r3, r3, #1048576	@ 0x100000
 800047e:	bf06      	itte	eq
 8000480:	f481 1180 	eoreq.w	r1, r1, #1048576	@ 0x100000
 8000484:	3401      	addeq	r4, #1
 8000486:	3d01      	subne	r5, #1
 8000488:	e74e      	b.n	8000328 <__adddf3+0x8c>
 800048a:	ea7f 5c64 	mvns.w	ip, r4, asr #21
 800048e:	bf18      	it	ne
 8000490:	ea7f 5c65 	mvnsne.w	ip, r5, asr #21
 8000494:	d029      	beq.n	80004ea <__adddf3+0x24e>
 8000496:	ea94 0f05 	teq	r4, r5
 800049a:	bf08      	it	eq
 800049c:	ea90 0f02 	teqeq	r0, r2
 80004a0:	d005      	beq.n	80004ae <__adddf3+0x212>
 80004a2:	ea54 0c00 	orrs.w	ip, r4, r0
 80004a6:	bf04      	itt	eq
 80004a8:	4619      	moveq	r1, r3
 80004aa:	4610      	moveq	r0, r2
 80004ac:	bd30      	pop	{r4, r5, pc}
 80004ae:	ea91 0f03 	teq	r1, r3
 80004b2:	bf1e      	ittt	ne
 80004b4:	2100      	movne	r1, #0
 80004b6:	2000      	movne	r0, #0
 80004b8:	bd30      	popne	{r4, r5, pc}
 80004ba:	ea5f 5c54 	movs.w	ip, r4, lsr #21
 80004be:	d105      	bne.n	80004cc <__adddf3+0x230>
 80004c0:	0040      	lsls	r0, r0, #1
 80004c2:	4149      	adcs	r1, r1
 80004c4:	bf28      	it	cs
 80004c6:	f041 4100 	orrcs.w	r1, r1, #2147483648	@ 0x80000000
 80004ca:	bd30      	pop	{r4, r5, pc}
 80004cc:	f514 0480 	adds.w	r4, r4, #4194304	@ 0x400000
 80004d0:	bf3c      	itt	cc
 80004d2:	f501 1180 	addcc.w	r1, r1, #1048576	@ 0x100000
 80004d6:	bd30      	popcc	{r4, r5, pc}
 80004d8:	f001 4500 	and.w	r5, r1, #2147483648	@ 0x80000000
 80004dc:	f045 41fe 	orr.w	r1, r5, #2130706432	@ 0x7f000000
 80004e0:	f441 0170 	orr.w	r1, r1, #15728640	@ 0xf00000
 80004e4:	f04f 0000 	mov.w	r0, #0
 80004e8:	bd30      	pop	{r4, r5, pc}
 80004ea:	ea7f 5c64 	mvns.w	ip, r4, asr #21
 80004ee:	bf1a      	itte	ne
 80004f0:	4619      	movne	r1, r3
 80004f2:	4610      	movne	r0, r2
 80004f4:	ea7f 5c65 	mvnseq.w	ip, r5, asr #21
 80004f8:	bf1c      	itt	ne
 80004fa:	460b      	movne	r3, r1
 80004fc:	4602      	movne	r2, r0
 80004fe:	ea50 3401 	orrs.w	r4, r0, r1, lsl #12
 8000502:	bf06      	itte	eq
 8000504:	ea52 3503 	orrseq.w	r5, r2, r3, lsl #12
 8000508:	ea91 0f03 	teqeq	r1, r3
 800050c:	f441 2100 	orrne.w	r1, r1, #524288	@ 0x80000
 8000510:	bd30      	pop	{r4, r5, pc}
 8000512:	bf00      	nop

08000514 <__aeabi_ui2d>:
 8000514:	f090 0f00 	teq	r0, #0
 8000518:	bf04      	itt	eq
 800051a:	2100      	moveq	r1, #0
 800051c:	4770      	bxeq	lr
 800051e:	b530      	push	{r4, r5, lr}
 8000520:	f44f 6480 	mov.w	r4, #1024	@ 0x400
 8000524:	f104 0432 	add.w	r4, r4, #50	@ 0x32
 8000528:	f04f 0500 	mov.w	r5, #0
 800052c:	f04f 0100 	mov.w	r1, #0
 8000530:	e750      	b.n	80003d4 <__adddf3+0x138>
 8000532:	bf00      	nop

08000534 <__aeabi_i2d>:
 8000534:	f090 0f00 	teq	r0, #0
 8000538:	bf04      	itt	eq
 800053a:	2100      	moveq	r1, #0
 800053c:	4770      	bxeq	lr
 800053e:	b530      	push	{r4, r5, lr}
 8000540:	f44f 6480 	mov.w	r4, #1024	@ 0x400
 8000544:	f104 0432 	add.w	r4, r4, #50	@ 0x32
 8000548:	f010 4500 	ands.w	r5, r0, #2147483648	@ 0x80000000
 800054c:	bf48      	it	mi
 800054e:	4240      	negmi	r0, r0
 8000550:	f04f 0100 	mov.w	r1, #0
 8000554:	e73e      	b.n	80003d4 <__adddf3+0x138>
 8000556:	bf00      	nop

08000558 <__aeabi_f2d>:
 8000558:	0042      	lsls	r2, r0, #1
 800055a:	ea4f 01e2 	mov.w	r1, r2, asr #3
 800055e:	ea4f 0131 	mov.w	r1, r1, rrx
 8000562:	ea4f 7002 	mov.w	r0, r2, lsl #28
 8000566:	bf1f      	itttt	ne
 8000568:	f012 437f 	andsne.w	r3, r2, #4278190080	@ 0xff000000
 800056c:	f093 4f7f 	teqne	r3, #4278190080	@ 0xff000000
 8000570:	f081 5160 	eorne.w	r1, r1, #939524096	@ 0x38000000
 8000574:	4770      	bxne	lr
 8000576:	f032 427f 	bics.w	r2, r2, #4278190080	@ 0xff000000
 800057a:	bf08      	it	eq
 800057c:	4770      	bxeq	lr
 800057e:	f093 4f7f 	teq	r3, #4278190080	@ 0xff000000
 8000582:	bf04      	itt	eq
 8000584:	f441 2100 	orreq.w	r1, r1, #524288	@ 0x80000
 8000588:	4770      	bxeq	lr
 800058a:	b530      	push	{r4, r5, lr}
 800058c:	f44f 7460 	mov.w	r4, #896	@ 0x380
 8000590:	f001 4500 	and.w	r5, r1, #2147483648	@ 0x80000000
 8000594:	f021 4100 	bic.w	r1, r1, #2147483648	@ 0x80000000
 8000598:	e71c      	b.n	80003d4 <__adddf3+0x138>
 800059a:	bf00      	nop

0800059c <__aeabi_ul2d>:
 800059c:	ea50 0201 	orrs.w	r2, r0, r1
 80005a0:	bf08      	it	eq
 80005a2:	4770      	bxeq	lr
 80005a4:	b530      	push	{r4, r5, lr}
 80005a6:	f04f 0500 	mov.w	r5, #0
 80005aa:	e00a      	b.n	80005c2 <__aeabi_l2d+0x16>

080005ac <__aeabi_l2d>:
 80005ac:	ea50 0201 	orrs.w	r2, r0, r1
 80005b0:	bf08      	it	eq
 80005b2:	4770      	bxeq	lr
 80005b4:	b530      	push	{r4, r5, lr}
 80005b6:	f011 4500 	ands.w	r5, r1, #2147483648	@ 0x80000000
 80005ba:	d502      	bpl.n	80005c2 <__aeabi_l2d+0x16>
 80005bc:	4240      	negs	r0, r0
 80005be:	eb61 0141 	sbc.w	r1, r1, r1, lsl #1
 80005c2:	f44f 6480 	mov.w	r4, #1024	@ 0x400
 80005c6:	f104 0432 	add.w	r4, r4, #50	@ 0x32
 80005ca:	ea5f 5c91 	movs.w	ip, r1, lsr #22
 80005ce:	f43f aed8 	beq.w	8000382 <__adddf3+0xe6>
 80005d2:	f04f 0203 	mov.w	r2, #3
 80005d6:	ea5f 0cdc 	movs.w	ip, ip, lsr #3
 80005da:	bf18      	it	ne
 80005dc:	3203      	addne	r2, #3
 80005de:	ea5f 0cdc 	movs.w	ip, ip, lsr #3
 80005e2:	bf18      	it	ne
 80005e4:	3203      	addne	r2, #3
 80005e6:	eb02 02dc 	add.w	r2, r2, ip, lsr #3
 80005ea:	f1c2 0320 	rsb	r3, r2, #32
 80005ee:	fa00 fc03 	lsl.w	ip, r0, r3
 80005f2:	fa20 f002 	lsr.w	r0, r0, r2
 80005f6:	fa01 fe03 	lsl.w	lr, r1, r3
 80005fa:	ea40 000e 	orr.w	r0, r0, lr
 80005fe:	fa21 f102 	lsr.w	r1, r1, r2
 8000602:	4414      	add	r4, r2
 8000604:	e6bd      	b.n	8000382 <__adddf3+0xe6>
 8000606:	bf00      	nop

08000608 <__aeabi_dmul>:
 8000608:	b570      	push	{r4, r5, r6, lr}
 800060a:	f04f 0cff 	mov.w	ip, #255	@ 0xff
 800060e:	f44c 6ce0 	orr.w	ip, ip, #1792	@ 0x700
 8000612:	ea1c 5411 	ands.w	r4, ip, r1, lsr #20
 8000616:	bf1d      	ittte	ne
 8000618:	ea1c 5513 	andsne.w	r5, ip, r3, lsr #20
 800061c:	ea94 0f0c 	teqne	r4, ip
 8000620:	ea95 0f0c 	teqne	r5, ip
 8000624:	f000 f8de 	bleq	80007e4 <__aeabi_dmul+0x1dc>
 8000628:	442c      	add	r4, r5
 800062a:	ea81 0603 	eor.w	r6, r1, r3
 800062e:	ea21 514c 	bic.w	r1, r1, ip, lsl #21
 8000632:	ea23 534c 	bic.w	r3, r3, ip, lsl #21
 8000636:	ea50 3501 	orrs.w	r5, r0, r1, lsl #12
 800063a:	bf18      	it	ne
 800063c:	ea52 3503 	orrsne.w	r5, r2, r3, lsl #12
 8000640:	f441 1180 	orr.w	r1, r1, #1048576	@ 0x100000
 8000644:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
 8000648:	d038      	beq.n	80006bc <__aeabi_dmul+0xb4>
 800064a:	fba0 ce02 	umull	ip, lr, r0, r2
 800064e:	f04f 0500 	mov.w	r5, #0
 8000652:	fbe1 e502 	umlal	lr, r5, r1, r2
 8000656:	f006 4200 	and.w	r2, r6, #2147483648	@ 0x80000000
 800065a:	fbe0 e503 	umlal	lr, r5, r0, r3
 800065e:	f04f 0600 	mov.w	r6, #0
 8000662:	fbe1 5603 	umlal	r5, r6, r1, r3
 8000666:	f09c 0f00 	teq	ip, #0
 800066a:	bf18      	it	ne
 800066c:	f04e 0e01 	orrne.w	lr, lr, #1
 8000670:	f1a4 04ff 	sub.w	r4, r4, #255	@ 0xff
 8000674:	f5b6 7f00 	cmp.w	r6, #512	@ 0x200
 8000678:	f564 7440 	sbc.w	r4, r4, #768	@ 0x300
 800067c:	d204      	bcs.n	8000688 <__aeabi_dmul+0x80>
 800067e:	ea5f 0e4e 	movs.w	lr, lr, lsl #1
 8000682:	416d      	adcs	r5, r5
 8000684:	eb46 0606 	adc.w	r6, r6, r6
 8000688:	ea42 21c6 	orr.w	r1, r2, r6, lsl #11
 800068c:	ea41 5155 	orr.w	r1, r1, r5, lsr #21
 8000690:	ea4f 20c5 	mov.w	r0, r5, lsl #11
 8000694:	ea40 505e 	orr.w	r0, r0, lr, lsr #21
 8000698:	ea4f 2ece 	mov.w	lr, lr, lsl #11
 800069c:	f1b4 0cfd 	subs.w	ip, r4, #253	@ 0xfd
 80006a0:	bf88      	it	hi
 80006a2:	f5bc 6fe0 	cmphi.w	ip, #1792	@ 0x700
 80006a6:	d81e      	bhi.n	80006e6 <__aeabi_dmul+0xde>
 80006a8:	f1be 4f00 	cmp.w	lr, #2147483648	@ 0x80000000
 80006ac:	bf08      	it	eq
 80006ae:	ea5f 0e50 	movseq.w	lr, r0, lsr #1
 80006b2:	f150 0000 	adcs.w	r0, r0, #0
 80006b6:	eb41 5104 	adc.w	r1, r1, r4, lsl #20
 80006ba:	bd70      	pop	{r4, r5, r6, pc}
 80006bc:	f006 4600 	and.w	r6, r6, #2147483648	@ 0x80000000
 80006c0:	ea46 0101 	orr.w	r1, r6, r1
 80006c4:	ea40 0002 	orr.w	r0, r0, r2
 80006c8:	ea81 0103 	eor.w	r1, r1, r3
 80006cc:	ebb4 045c 	subs.w	r4, r4, ip, lsr #1
 80006d0:	bfc2      	ittt	gt
 80006d2:	ebd4 050c 	rsbsgt	r5, r4, ip
 80006d6:	ea41 5104 	orrgt.w	r1, r1, r4, lsl #20
 80006da:	bd70      	popgt	{r4, r5, r6, pc}
 80006dc:	f441 1180 	orr.w	r1, r1, #1048576	@ 0x100000
 80006e0:	f04f 0e00 	mov.w	lr, #0
 80006e4:	3c01      	subs	r4, #1
 80006e6:	f300 80ab 	bgt.w	8000840 <__aeabi_dmul+0x238>
 80006ea:	f114 0f36 	cmn.w	r4, #54	@ 0x36
 80006ee:	bfde      	ittt	le
 80006f0:	2000      	movle	r0, #0
 80006f2:	f001 4100 	andle.w	r1, r1, #2147483648	@ 0x80000000
 80006f6:	bd70      	pople	{r4, r5, r6, pc}
 80006f8:	f1c4 0400 	rsb	r4, r4, #0
 80006fc:	3c20      	subs	r4, #32
 80006fe:	da35      	bge.n	800076c <__aeabi_dmul+0x164>
 8000700:	340c      	adds	r4, #12
 8000702:	dc1b      	bgt.n	800073c <__aeabi_dmul+0x134>
 8000704:	f104 0414 	add.w	r4, r4, #20
 8000708:	f1c4 0520 	rsb	r5, r4, #32
 800070c:	fa00 f305 	lsl.w	r3, r0, r5
 8000710:	fa20 f004 	lsr.w	r0, r0, r4
 8000714:	fa01 f205 	lsl.w	r2, r1, r5
 8000718:	ea40 0002 	orr.w	r0, r0, r2
 800071c:	f001 4200 	and.w	r2, r1, #2147483648	@ 0x80000000
 8000720:	f021 4100 	bic.w	r1, r1, #2147483648	@ 0x80000000
 8000724:	eb10 70d3 	adds.w	r0, r0, r3, lsr #31
 8000728:	fa21 f604 	lsr.w	r6, r1, r4
 800072c:	eb42 0106 	adc.w	r1, r2, r6
 8000730:	ea5e 0e43 	orrs.w	lr, lr, r3, lsl #1
 8000734:	bf08      	it	eq
 8000736:	ea20 70d3 	biceq.w	r0, r0, r3, lsr #31
 800073a:	bd70      	pop	{r4, r5, r6, pc}
 800073c:	f1c4 040c 	rsb	r4, r4, #12
 8000740:	f1c4 0520 	rsb	r5, r4, #32
 8000744:	fa00 f304 	lsl.w	r3, r0, r4
 8000748:	fa20 f005 	lsr.w	r0, r0, r5
 800074c:	fa01 f204 	lsl.w	r2, r1, r4
 8000750:	ea40 0002 	orr.w	r0, r0, r2
 8000754:	f001 4100 	and.w	r1, r1, #2147483648	@ 0x80000000
 8000758:	eb10 70d3 	adds.w	r0, r0, r3, lsr #31
 800075c:	f141 0100 	adc.w	r1, r1, #0
 8000760:	ea5e 0e43 	orrs.w	lr, lr, r3, lsl #1
 8000764:	bf08      	it	eq
 8000766:	ea20 70d3 	biceq.w	r0, r0, r3, lsr #31
 800076a:	bd70      	pop	{r4, r5, r6, pc}
 800076c:	f1c4 0520 	rsb	r5, r4, #32
 8000770:	fa00 f205 	lsl.w	r2, r0, r5
 8000774:	ea4e 0e02 	orr.w	lr, lr, r2
 8000778:	fa20 f304 	lsr.w	r3, r0, r4
 800077c:	fa01 f205 	lsl.w	r2, r1, r5
 8000780:	ea43 0302 	orr.w	r3, r3, r2
 8000784:	fa21 f004 	lsr.w	r0, r1, r4
 8000788:	f001 4100 	and.w	r1, r1, #2147483648	@ 0x80000000
 800078c:	fa21 f204 	lsr.w	r2, r1, r4
 8000790:	ea20 0002 	bic.w	r0, r0, r2
 8000794:	eb00 70d3 	add.w	r0, r0, r3, lsr #31
 8000798:	ea5e 0e43 	orrs.w	lr, lr, r3, lsl #1
 800079c:	bf08      	it	eq
 800079e:	ea20 70d3 	biceq.w	r0, r0, r3, lsr #31
 80007a2:	bd70      	pop	{r4, r5, r6, pc}
 80007a4:	f094 0f00 	teq	r4, #0
 80007a8:	d10f      	bne.n	80007ca <__aeabi_dmul+0x1c2>
 80007aa:	f001 4600 	and.w	r6, r1, #2147483648	@ 0x80000000
 80007ae:	0040      	lsls	r0, r0, #1
 80007b0:	eb41 0101 	adc.w	r1, r1, r1
 80007b4:	f411 1f80 	tst.w	r1, #1048576	@ 0x100000
 80007b8:	bf08      	it	eq
 80007ba:	3c01      	subeq	r4, #1
 80007bc:	d0f7      	beq.n	80007ae <__aeabi_dmul+0x1a6>
 80007be:	ea41 0106 	orr.w	r1, r1, r6
 80007c2:	f095 0f00 	teq	r5, #0
 80007c6:	bf18      	it	ne
 80007c8:	4770      	bxne	lr
 80007ca:	f003 4600 	and.w	r6, r3, #2147483648	@ 0x80000000
 80007ce:	0052      	lsls	r2, r2, #1
 80007d0:	eb43 0303 	adc.w	r3, r3, r3
 80007d4:	f413 1f80 	tst.w	r3, #1048576	@ 0x100000
 80007d8:	bf08      	it	eq
 80007da:	3d01      	subeq	r5, #1
 80007dc:	d0f7      	beq.n	80007ce <__aeabi_dmul+0x1c6>
 80007de:	ea43 0306 	orr.w	r3, r3, r6
 80007e2:	4770      	bx	lr
 80007e4:	ea94 0f0c 	teq	r4, ip
 80007e8:	ea0c 5513 	and.w	r5, ip, r3, lsr #20
 80007ec:	bf18      	it	ne
 80007ee:	ea95 0f0c 	teqne	r5, ip
 80007f2:	d00c      	beq.n	800080e <__aeabi_dmul+0x206>
 80007f4:	ea50 0641 	orrs.w	r6, r0, r1, lsl #1
 80007f8:	bf18      	it	ne
 80007fa:	ea52 0643 	orrsne.w	r6, r2, r3, lsl #1
 80007fe:	d1d1      	bne.n	80007a4 <__aeabi_dmul+0x19c>
 8000800:	ea81 0103 	eor.w	r1, r1, r3
 8000804:	f001 4100 	and.w	r1, r1, #2147483648	@ 0x80000000
 8000808:	f04f 0000 	mov.w	r0, #0
 800080c:	bd70      	pop	{r4, r5, r6, pc}
 800080e:	ea50 0641 	orrs.w	r6, r0, r1, lsl #1
 8000812:	bf06      	itte	eq
 8000814:	4610      	moveq	r0, r2
 8000816:	4619      	moveq	r1, r3
 8000818:	ea52 0643 	orrsne.w	r6, r2, r3, lsl #1
 800081c:	d019      	beq.n	8000852 <__aeabi_dmul+0x24a>
 800081e:	ea94 0f0c 	teq	r4, ip
 8000822:	d102      	bne.n	800082a <__aeabi_dmul+0x222>
 8000824:	ea50 3601 	orrs.w	r6, r0, r1, lsl #12
 8000828:	d113      	bne.n	8000852 <__aeabi_dmul+0x24a>
 800082a:	ea95 0f0c 	teq	r5, ip
 800082e:	d105      	bne.n	800083c <__aeabi_dmul+0x234>
 8000830:	ea52 3603 	orrs.w	r6, r2, r3, lsl #12
 8000834:	bf1c      	itt	ne
 8000836:	4610      	movne	r0, r2
 8000838:	4619      	movne	r1, r3
 800083a:	d10a      	bne.n	8000852 <__aeabi_dmul+0x24a>
 800083c:	ea81 0103 	eor.w	r1, r1, r3
 8000840:	f001 4100 	and.w	r1, r1, #2147483648	@ 0x80000000
 8000844:	f041 41fe 	orr.w	r1, r1, #2130706432	@ 0x7f000000
 8000848:	f441 0170 	orr.w	r1, r1, #15728640	@ 0xf00000
 800084c:	f04f 0000 	mov.w	r0, #0
 8000850:	bd70      	pop	{r4, r5, r6, pc}
 8000852:	f041 41fe 	orr.w	r1, r1, #2130706432	@ 0x7f000000
 8000856:	f441 0178 	orr.w	r1, r1, #16252928	@ 0xf80000
 800085a:	bd70      	pop	{r4, r5, r6, pc}

0800085c <__aeabi_ddiv>:
 800085c:	b570      	push	{r4, r5, r6, lr}
 800085e:	f04f 0cff 	mov.w	ip, #255	@ 0xff
 8000862:	f44c 6ce0 	orr.w	ip, ip, #1792	@ 0x700
 8000866:	ea1c 5411 	ands.w	r4, ip, r1, lsr #20
 800086a:	bf1d      	ittte	ne
 800086c:	ea1c 5513 	andsne.w	r5, ip, r3, lsr #20
 8000870:	ea94 0f0c 	teqne	r4, ip
 8000874:	ea95 0f0c 	teqne	r5, ip
 8000878:	f000 f8a7 	bleq	80009ca <__aeabi_ddiv+0x16e>
 800087c:	eba4 0405 	sub.w	r4, r4, r5
 8000880:	ea81 0e03 	eor.w	lr, r1, r3
 8000884:	ea52 3503 	orrs.w	r5, r2, r3, lsl #12
 8000888:	ea4f 3101 	mov.w	r1, r1, lsl #12
 800088c:	f000 8088 	beq.w	80009a0 <__aeabi_ddiv+0x144>
 8000890:	ea4f 3303 	mov.w	r3, r3, lsl #12
 8000894:	f04f 5580 	mov.w	r5, #268435456	@ 0x10000000
 8000898:	ea45 1313 	orr.w	r3, r5, r3, lsr #4
 800089c:	ea43 6312 	orr.w	r3, r3, r2, lsr #24
 80008a0:	ea4f 2202 	mov.w	r2, r2, lsl #8
 80008a4:	ea45 1511 	orr.w	r5, r5, r1, lsr #4
 80008a8:	ea45 6510 	orr.w	r5, r5, r0, lsr #24
 80008ac:	ea4f 2600 	mov.w	r6, r0, lsl #8
 80008b0:	f00e 4100 	and.w	r1, lr, #2147483648	@ 0x80000000
 80008b4:	429d      	cmp	r5, r3
 80008b6:	bf08      	it	eq
 80008b8:	4296      	cmpeq	r6, r2
 80008ba:	f144 04fd 	adc.w	r4, r4, #253	@ 0xfd
 80008be:	f504 7440 	add.w	r4, r4, #768	@ 0x300
 80008c2:	d202      	bcs.n	80008ca <__aeabi_ddiv+0x6e>
 80008c4:	085b      	lsrs	r3, r3, #1
 80008c6:	ea4f 0232 	mov.w	r2, r2, rrx
 80008ca:	1ab6      	subs	r6, r6, r2
 80008cc:	eb65 0503 	sbc.w	r5, r5, r3
 80008d0:	085b      	lsrs	r3, r3, #1
 80008d2:	ea4f 0232 	mov.w	r2, r2, rrx
 80008d6:	f44f 1080 	mov.w	r0, #1048576	@ 0x100000
 80008da:	f44f 2c00 	mov.w	ip, #524288	@ 0x80000
 80008de:	ebb6 0e02 	subs.w	lr, r6, r2
 80008e2:	eb75 0e03 	sbcs.w	lr, r5, r3
 80008e6:	bf22      	ittt	cs
 80008e8:	1ab6      	subcs	r6, r6, r2
 80008ea:	4675      	movcs	r5, lr
 80008ec:	ea40 000c 	orrcs.w	r0, r0, ip
 80008f0:	085b      	lsrs	r3, r3, #1
 80008f2:	ea4f 0232 	mov.w	r2, r2, rrx
 80008f6:	ebb6 0e02 	subs.w	lr, r6, r2
 80008fa:	eb75 0e03 	sbcs.w	lr, r5, r3
 80008fe:	bf22      	ittt	cs
 8000900:	1ab6      	subcs	r6, r6, r2
 8000902:	4675      	movcs	r5, lr
 8000904:	ea40 005c 	orrcs.w	r0, r0, ip, lsr #1
 8000908:	085b      	lsrs	r3, r3, #1
 800090a:	ea4f 0232 	mov.w	r2, r2, rrx
 800090e:	ebb6 0e02 	subs.w	lr, r6, r2
 8000912:	eb75 0e03 	sbcs.w	lr, r5, r3
 8000916:	bf22      	ittt	cs
 8000918:	1ab6      	subcs	r6, r6, r2
 800091a:	4675      	movcs	r5, lr
 800091c:	ea40 009c 	orrcs.w	r0, r0, ip, lsr #2
 8000920:	085b      	lsrs	r3, r3, #1
 8000922:	ea4f 0232 	mov.w	r2, r2, rrx
 8000926:	ebb6 0e02 	subs.w	lr, r6, r2
 800092a:	eb75 0e03 	sbcs.w	lr, r5, r3
 800092e:	bf22      	ittt	cs
 8000930:	1ab6      	subcs	r6, r6, r2
 8000932:	4675      	movcs	r5, lr
 8000934:	ea40 00dc 	orrcs.w	r0, r0, ip, lsr #3
 8000938:	ea55 0e06 	orrs.w	lr, r5, r6
 800093c:	d018      	beq.n	8000970 <__aeabi_ddiv+0x114>
 800093e:	ea4f 1505 	mov.w	r5, r5, lsl #4
 8000942:	ea45 7516 	orr.w	r5, r5, r6, lsr #28
 8000946:	ea4f 1606 	mov.w	r6, r6, lsl #4
 800094a:	ea4f 03c3 	mov.w	r3, r3, lsl #3
 800094e:	ea43 7352 	orr.w	r3, r3, r2, lsr #29
 8000952:	ea4f 02c2 	mov.w	r2, r2, lsl #3
 8000956:	ea5f 1c1c 	movs.w	ip, ip, lsr #4
 800095a:	d1c0      	bne.n	80008de <__aeabi_ddiv+0x82>
 800095c:	f411 1f80 	tst.w	r1, #1048576	@ 0x100000
 8000960:	d10b      	bne.n	800097a <__aeabi_ddiv+0x11e>
 8000962:	ea41 0100 	orr.w	r1, r1, r0
 8000966:	f04f 0000 	mov.w	r0, #0
 800096a:	f04f 4c00 	mov.w	ip, #2147483648	@ 0x80000000
 800096e:	e7b6      	b.n	80008de <__aeabi_ddiv+0x82>
 8000970:	f411 1f80 	tst.w	r1, #1048576	@ 0x100000
 8000974:	bf04      	itt	eq
 8000976:	4301      	orreq	r1, r0
 8000978:	2000      	moveq	r0, #0
 800097a:	f1b4 0cfd 	subs.w	ip, r4, #253	@ 0xfd
 800097e:	bf88      	it	hi
 8000980:	f5bc 6fe0 	cmphi.w	ip, #1792	@ 0x700
 8000984:	f63f aeaf 	bhi.w	80006e6 <__aeabi_dmul+0xde>
 8000988:	ebb5 0c03 	subs.w	ip, r5, r3
 800098c:	bf04      	itt	eq
 800098e:	ebb6 0c02 	subseq.w	ip, r6, r2
 8000992:	ea5f 0c50 	movseq.w	ip, r0, lsr #1
 8000996:	f150 0000 	adcs.w	r0, r0, #0
 800099a:	eb41 5104 	adc.w	r1, r1, r4, lsl #20
 800099e:	bd70      	pop	{r4, r5, r6, pc}
 80009a0:	f00e 4e00 	and.w	lr, lr, #2147483648	@ 0x80000000
 80009a4:	ea4e 3111 	orr.w	r1, lr, r1, lsr #12
 80009a8:	eb14 045c 	adds.w	r4, r4, ip, lsr #1
 80009ac:	bfc2      	ittt	gt
 80009ae:	ebd4 050c 	rsbsgt	r5, r4, ip
 80009b2:	ea41 5104 	orrgt.w	r1, r1, r4, lsl #20
 80009b6:	bd70      	popgt	{r4, r5, r6, pc}
 80009b8:	f441 1180 	orr.w	r1, r1, #1048576	@ 0x100000
 80009bc:	f04f 0e00 	mov.w	lr, #0
 80009c0:	3c01      	subs	r4, #1
 80009c2:	e690      	b.n	80006e6 <__aeabi_dmul+0xde>
 80009c4:	ea45 0e06 	orr.w	lr, r5, r6
 80009c8:	e68d      	b.n	80006e6 <__aeabi_dmul+0xde>
 80009ca:	ea0c 5513 	and.w	r5, ip, r3, lsr #20
 80009ce:	ea94 0f0c 	teq	r4, ip
 80009d2:	bf08      	it	eq
 80009d4:	ea95 0f0c 	teqeq	r5, ip
 80009d8:	f43f af3b 	beq.w	8000852 <__aeabi_dmul+0x24a>
 80009dc:	ea94 0f0c 	teq	r4, ip
 80009e0:	d10a      	bne.n	80009f8 <__aeabi_ddiv+0x19c>
 80009e2:	ea50 3401 	orrs.w	r4, r0, r1, lsl #12
 80009e6:	f47f af34 	bne.w	8000852 <__aeabi_dmul+0x24a>
 80009ea:	ea95 0f0c 	teq	r5, ip
 80009ee:	f47f af25 	bne.w	800083c <__aeabi_dmul+0x234>
 80009f2:	4610      	mov	r0, r2
 80009f4:	4619      	mov	r1, r3
 80009f6:	e72c      	b.n	8000852 <__aeabi_dmul+0x24a>
 80009f8:	ea95 0f0c 	teq	r5, ip
 80009fc:	d106      	bne.n	8000a0c <__aeabi_ddiv+0x1b0>
 80009fe:	ea52 3503 	orrs.w	r5, r2, r3, lsl #12
 8000a02:	f43f aefd 	beq.w	8000800 <__aeabi_dmul+0x1f8>
 8000a06:	4610      	mov	r0, r2
 8000a08:	4619      	mov	r1, r3
 8000a0a:	e722      	b.n	8000852 <__aeabi_dmul+0x24a>
 8000a0c:	ea50 0641 	orrs.w	r6, r0, r1, lsl #1
 8000a10:	bf18      	it	ne
 8000a12:	ea52 0643 	orrsne.w	r6, r2, r3, lsl #1
 8000a16:	f47f aec5 	bne.w	80007a4 <__aeabi_dmul+0x19c>
 8000a1a:	ea50 0441 	orrs.w	r4, r0, r1, lsl #1
 8000a1e:	f47f af0d 	bne.w	800083c <__aeabi_dmul+0x234>
 8000a22:	ea52 0543 	orrs.w	r5, r2, r3, lsl #1
 8000a26:	f47f aeeb 	bne.w	8000800 <__aeabi_dmul+0x1f8>
 8000a2a:	e712      	b.n	8000852 <__aeabi_dmul+0x24a>

08000a2c <__gedf2>:
 8000a2c:	f04f 3cff 	mov.w	ip, #4294967295
 8000a30:	e006      	b.n	8000a40 <__cmpdf2+0x4>
 8000a32:	bf00      	nop

08000a34 <__ledf2>:
 8000a34:	f04f 0c01 	mov.w	ip, #1
 8000a38:	e002      	b.n	8000a40 <__cmpdf2+0x4>
 8000a3a:	bf00      	nop

08000a3c <__cmpdf2>:
 8000a3c:	f04f 0c01 	mov.w	ip, #1
 8000a40:	f84d cd04 	str.w	ip, [sp, #-4]!
 8000a44:	ea4f 0c41 	mov.w	ip, r1, lsl #1
 8000a48:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 8000a4c:	ea4f 0c43 	mov.w	ip, r3, lsl #1
 8000a50:	bf18      	it	ne
 8000a52:	ea7f 5c6c 	mvnsne.w	ip, ip, asr #21
 8000a56:	d01b      	beq.n	8000a90 <__cmpdf2+0x54>
 8000a58:	b001      	add	sp, #4
 8000a5a:	ea50 0c41 	orrs.w	ip, r0, r1, lsl #1
 8000a5e:	bf0c      	ite	eq
 8000a60:	ea52 0c43 	orrseq.w	ip, r2, r3, lsl #1
 8000a64:	ea91 0f03 	teqne	r1, r3
 8000a68:	bf02      	ittt	eq
 8000a6a:	ea90 0f02 	teqeq	r0, r2
 8000a6e:	2000      	moveq	r0, #0
 8000a70:	4770      	bxeq	lr
 8000a72:	f110 0f00 	cmn.w	r0, #0
 8000a76:	ea91 0f03 	teq	r1, r3
 8000a7a:	bf58      	it	pl
 8000a7c:	4299      	cmppl	r1, r3
 8000a7e:	bf08      	it	eq
 8000a80:	4290      	cmpeq	r0, r2
 8000a82:	bf2c      	ite	cs
 8000a84:	17d8      	asrcs	r0, r3, #31
 8000a86:	ea6f 70e3 	mvncc.w	r0, r3, asr #31
 8000a8a:	f040 0001 	orr.w	r0, r0, #1
 8000a8e:	4770      	bx	lr
 8000a90:	ea4f 0c41 	mov.w	ip, r1, lsl #1
 8000a94:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 8000a98:	d102      	bne.n	8000aa0 <__cmpdf2+0x64>
 8000a9a:	ea50 3c01 	orrs.w	ip, r0, r1, lsl #12
 8000a9e:	d107      	bne.n	8000ab0 <__cmpdf2+0x74>
 8000aa0:	ea4f 0c43 	mov.w	ip, r3, lsl #1
 8000aa4:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 8000aa8:	d1d6      	bne.n	8000a58 <__cmpdf2+0x1c>
 8000aaa:	ea52 3c03 	orrs.w	ip, r2, r3, lsl #12
 8000aae:	d0d3      	beq.n	8000a58 <__cmpdf2+0x1c>
 8000ab0:	f85d 0b04 	ldr.w	r0, [sp], #4
 8000ab4:	4770      	bx	lr
 8000ab6:	bf00      	nop

08000ab8 <__aeabi_cdrcmple>:
 8000ab8:	4684      	mov	ip, r0
 8000aba:	4610      	mov	r0, r2
 8000abc:	4662      	mov	r2, ip
 8000abe:	468c      	mov	ip, r1
 8000ac0:	4619      	mov	r1, r3
 8000ac2:	4663      	mov	r3, ip
 8000ac4:	e000      	b.n	8000ac8 <__aeabi_cdcmpeq>
 8000ac6:	bf00      	nop

08000ac8 <__aeabi_cdcmpeq>:
 8000ac8:	b501      	push	{r0, lr}
 8000aca:	f7ff ffb7 	bl	8000a3c <__cmpdf2>
 8000ace:	2800      	cmp	r0, #0
 8000ad0:	bf48      	it	mi
 8000ad2:	f110 0f00 	cmnmi.w	r0, #0
 8000ad6:	bd01      	pop	{r0, pc}

08000ad8 <__aeabi_dcmpeq>:
 8000ad8:	f84d ed08 	str.w	lr, [sp, #-8]!
 8000adc:	f7ff fff4 	bl	8000ac8 <__aeabi_cdcmpeq>
 8000ae0:	bf0c      	ite	eq
 8000ae2:	2001      	moveq	r0, #1
 8000ae4:	2000      	movne	r0, #0
 8000ae6:	f85d fb08 	ldr.w	pc, [sp], #8
 8000aea:	bf00      	nop

08000aec <__aeabi_dcmplt>:
 8000aec:	f84d ed08 	str.w	lr, [sp, #-8]!
 8000af0:	f7ff ffea 	bl	8000ac8 <__aeabi_cdcmpeq>
 8000af4:	bf34      	ite	cc
 8000af6:	2001      	movcc	r0, #1
 8000af8:	2000      	movcs	r0, #0
 8000afa:	f85d fb08 	ldr.w	pc, [sp], #8
 8000afe:	bf00      	nop

08000b00 <__aeabi_dcmple>:
 8000b00:	f84d ed08 	str.w	lr, [sp, #-8]!
 8000b04:	f7ff ffe0 	bl	8000ac8 <__aeabi_cdcmpeq>
 8000b08:	bf94      	ite	ls
 8000b0a:	2001      	movls	r0, #1
 8000b0c:	2000      	movhi	r0, #0
 8000b0e:	f85d fb08 	ldr.w	pc, [sp], #8
 8000b12:	bf00      	nop

08000b14 <__aeabi_dcmpge>:
 8000b14:	f84d ed08 	str.w	lr, [sp, #-8]!
 8000b18:	f7ff ffce 	bl	8000ab8 <__aeabi_cdrcmple>
 8000b1c:	bf94      	ite	ls
 8000b1e:	2001      	movls	r0, #1
 8000b20:	2000      	movhi	r0, #0
 8000b22:	f85d fb08 	ldr.w	pc, [sp], #8
 8000b26:	bf00      	nop

08000b28 <__aeabi_dcmpgt>:
 8000b28:	f84d ed08 	str.w	lr, [sp, #-8]!
 8000b2c:	f7ff ffc4 	bl	8000ab8 <__aeabi_cdrcmple>
 8000b30:	bf34      	ite	cc
 8000b32:	2001      	movcc	r0, #1
 8000b34:	2000      	movcs	r0, #0
 8000b36:	f85d fb08 	ldr.w	pc, [sp], #8
 8000b3a:	bf00      	nop

08000b3c <__aeabi_dcmpun>:
 8000b3c:	ea4f 0c41 	mov.w	ip, r1, lsl #1
 8000b40:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 8000b44:	d102      	bne.n	8000b4c <__aeabi_dcmpun+0x10>
 8000b46:	ea50 3c01 	orrs.w	ip, r0, r1, lsl #12
 8000b4a:	d10a      	bne.n	8000b62 <__aeabi_dcmpun+0x26>
 8000b4c:	ea4f 0c43 	mov.w	ip, r3, lsl #1
 8000b50:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 8000b54:	d102      	bne.n	8000b5c <__aeabi_dcmpun+0x20>
 8000b56:	ea52 3c03 	orrs.w	ip, r2, r3, lsl #12
 8000b5a:	d102      	bne.n	8000b62 <__aeabi_dcmpun+0x26>
 8000b5c:	f04f 0000 	mov.w	r0, #0
 8000b60:	4770      	bx	lr
 8000b62:	f04f 0001 	mov.w	r0, #1
 8000b66:	4770      	bx	lr

08000b68 <__aeabi_d2iz>:
 8000b68:	ea4f 0241 	mov.w	r2, r1, lsl #1
 8000b6c:	f512 1200 	adds.w	r2, r2, #2097152	@ 0x200000
 8000b70:	d215      	bcs.n	8000b9e <__aeabi_d2iz+0x36>
 8000b72:	d511      	bpl.n	8000b98 <__aeabi_d2iz+0x30>
 8000b74:	f46f 7378 	mvn.w	r3, #992	@ 0x3e0
 8000b78:	ebb3 5262 	subs.w	r2, r3, r2, asr #21
 8000b7c:	d912      	bls.n	8000ba4 <__aeabi_d2iz+0x3c>
 8000b7e:	ea4f 23c1 	mov.w	r3, r1, lsl #11
 8000b82:	f043 4300 	orr.w	r3, r3, #2147483648	@ 0x80000000
 8000b86:	ea43 5350 	orr.w	r3, r3, r0, lsr #21
 8000b8a:	f011 4f00 	tst.w	r1, #2147483648	@ 0x80000000
 8000b8e:	fa23 f002 	lsr.w	r0, r3, r2
 8000b92:	bf18      	it	ne
 8000b94:	4240      	negne	r0, r0
 8000b96:	4770      	bx	lr
 8000b98:	f04f 0000 	mov.w	r0, #0
 8000b9c:	4770      	bx	lr
 8000b9e:	ea50 3001 	orrs.w	r0, r0, r1, lsl #12
 8000ba2:	d105      	bne.n	8000bb0 <__aeabi_d2iz+0x48>
 8000ba4:	f011 4000 	ands.w	r0, r1, #2147483648	@ 0x80000000
 8000ba8:	bf08      	it	eq
 8000baa:	f06f 4000 	mvneq.w	r0, #2147483648	@ 0x80000000
 8000bae:	4770      	bx	lr
 8000bb0:	f04f 0000 	mov.w	r0, #0
 8000bb4:	4770      	bx	lr
 8000bb6:	bf00      	nop

08000bb8 <__aeabi_uldivmod>:
 8000bb8:	b953      	cbnz	r3, 8000bd0 <__aeabi_uldivmod+0x18>
 8000bba:	b94a      	cbnz	r2, 8000bd0 <__aeabi_uldivmod+0x18>
 8000bbc:	2900      	cmp	r1, #0
 8000bbe:	bf08      	it	eq
 8000bc0:	2800      	cmpeq	r0, #0
 8000bc2:	bf1c      	itt	ne
 8000bc4:	f04f 31ff 	movne.w	r1, #4294967295
 8000bc8:	f04f 30ff 	movne.w	r0, #4294967295
 8000bcc:	f000 b988 	b.w	8000ee0 <__aeabi_idiv0>
 8000bd0:	f1ad 0c08 	sub.w	ip, sp, #8
 8000bd4:	e96d ce04 	strd	ip, lr, [sp, #-16]!
 8000bd8:	f000 f806 	bl	8000be8 <__udivmoddi4>
 8000bdc:	f8dd e004 	ldr.w	lr, [sp, #4]
 8000be0:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 8000be4:	b004      	add	sp, #16
 8000be6:	4770      	bx	lr

08000be8 <__udivmoddi4>:
 8000be8:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8000bec:	9d08      	ldr	r5, [sp, #32]
 8000bee:	468e      	mov	lr, r1
 8000bf0:	4604      	mov	r4, r0
 8000bf2:	4688      	mov	r8, r1
 8000bf4:	2b00      	cmp	r3, #0
 8000bf6:	d14a      	bne.n	8000c8e <__udivmoddi4+0xa6>
 8000bf8:	428a      	cmp	r2, r1
 8000bfa:	4617      	mov	r7, r2
 8000bfc:	d962      	bls.n	8000cc4 <__udivmoddi4+0xdc>
 8000bfe:	fab2 f682 	clz	r6, r2
 8000c02:	b14e      	cbz	r6, 8000c18 <__udivmoddi4+0x30>
 8000c04:	f1c6 0320 	rsb	r3, r6, #32
 8000c08:	fa01 f806 	lsl.w	r8, r1, r6
 8000c0c:	fa20 f303 	lsr.w	r3, r0, r3
 8000c10:	40b7      	lsls	r7, r6
 8000c12:	ea43 0808 	orr.w	r8, r3, r8
 8000c16:	40b4      	lsls	r4, r6
 8000c18:	ea4f 4e17 	mov.w	lr, r7, lsr #16
 8000c1c:	fa1f fc87 	uxth.w	ip, r7
 8000c20:	fbb8 f1fe 	udiv	r1, r8, lr
 8000c24:	0c23      	lsrs	r3, r4, #16
 8000c26:	fb0e 8811 	mls	r8, lr, r1, r8
 8000c2a:	ea43 4308 	orr.w	r3, r3, r8, lsl #16
 8000c2e:	fb01 f20c 	mul.w	r2, r1, ip
 8000c32:	429a      	cmp	r2, r3
 8000c34:	d909      	bls.n	8000c4a <__udivmoddi4+0x62>
 8000c36:	18fb      	adds	r3, r7, r3
 8000c38:	f101 30ff 	add.w	r0, r1, #4294967295
 8000c3c:	f080 80ea 	bcs.w	8000e14 <__udivmoddi4+0x22c>
 8000c40:	429a      	cmp	r2, r3
 8000c42:	f240 80e7 	bls.w	8000e14 <__udivmoddi4+0x22c>
 8000c46:	3902      	subs	r1, #2
 8000c48:	443b      	add	r3, r7
 8000c4a:	1a9a      	subs	r2, r3, r2
 8000c4c:	b2a3      	uxth	r3, r4
 8000c4e:	fbb2 f0fe 	udiv	r0, r2, lr
 8000c52:	fb0e 2210 	mls	r2, lr, r0, r2
 8000c56:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
 8000c5a:	fb00 fc0c 	mul.w	ip, r0, ip
 8000c5e:	459c      	cmp	ip, r3
 8000c60:	d909      	bls.n	8000c76 <__udivmoddi4+0x8e>
 8000c62:	18fb      	adds	r3, r7, r3
 8000c64:	f100 32ff 	add.w	r2, r0, #4294967295
 8000c68:	f080 80d6 	bcs.w	8000e18 <__udivmoddi4+0x230>
 8000c6c:	459c      	cmp	ip, r3
 8000c6e:	f240 80d3 	bls.w	8000e18 <__udivmoddi4+0x230>
 8000c72:	443b      	add	r3, r7
 8000c74:	3802      	subs	r0, #2
 8000c76:	ea40 4001 	orr.w	r0, r0, r1, lsl #16
 8000c7a:	eba3 030c 	sub.w	r3, r3, ip
 8000c7e:	2100      	movs	r1, #0
 8000c80:	b11d      	cbz	r5, 8000c8a <__udivmoddi4+0xa2>
 8000c82:	40f3      	lsrs	r3, r6
 8000c84:	2200      	movs	r2, #0
 8000c86:	e9c5 3200 	strd	r3, r2, [r5]
 8000c8a:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8000c8e:	428b      	cmp	r3, r1
 8000c90:	d905      	bls.n	8000c9e <__udivmoddi4+0xb6>
 8000c92:	b10d      	cbz	r5, 8000c98 <__udivmoddi4+0xb0>
 8000c94:	e9c5 0100 	strd	r0, r1, [r5]
 8000c98:	2100      	movs	r1, #0
 8000c9a:	4608      	mov	r0, r1
 8000c9c:	e7f5      	b.n	8000c8a <__udivmoddi4+0xa2>
 8000c9e:	fab3 f183 	clz	r1, r3
 8000ca2:	2900      	cmp	r1, #0
 8000ca4:	d146      	bne.n	8000d34 <__udivmoddi4+0x14c>
 8000ca6:	4573      	cmp	r3, lr
 8000ca8:	d302      	bcc.n	8000cb0 <__udivmoddi4+0xc8>
 8000caa:	4282      	cmp	r2, r0
 8000cac:	f200 8105 	bhi.w	8000eba <__udivmoddi4+0x2d2>
 8000cb0:	1a84      	subs	r4, r0, r2
 8000cb2:	eb6e 0203 	sbc.w	r2, lr, r3
 8000cb6:	2001      	movs	r0, #1
 8000cb8:	4690      	mov	r8, r2
 8000cba:	2d00      	cmp	r5, #0
 8000cbc:	d0e5      	beq.n	8000c8a <__udivmoddi4+0xa2>
 8000cbe:	e9c5 4800 	strd	r4, r8, [r5]
 8000cc2:	e7e2      	b.n	8000c8a <__udivmoddi4+0xa2>
 8000cc4:	2a00      	cmp	r2, #0
 8000cc6:	f000 8090 	beq.w	8000dea <__udivmoddi4+0x202>
 8000cca:	fab2 f682 	clz	r6, r2
 8000cce:	2e00      	cmp	r6, #0
 8000cd0:	f040 80a4 	bne.w	8000e1c <__udivmoddi4+0x234>
 8000cd4:	1a8a      	subs	r2, r1, r2
 8000cd6:	0c03      	lsrs	r3, r0, #16
 8000cd8:	ea4f 4e17 	mov.w	lr, r7, lsr #16
 8000cdc:	b280      	uxth	r0, r0
 8000cde:	b2bc      	uxth	r4, r7
 8000ce0:	2101      	movs	r1, #1
 8000ce2:	fbb2 fcfe 	udiv	ip, r2, lr
 8000ce6:	fb0e 221c 	mls	r2, lr, ip, r2
 8000cea:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
 8000cee:	fb04 f20c 	mul.w	r2, r4, ip
 8000cf2:	429a      	cmp	r2, r3
 8000cf4:	d907      	bls.n	8000d06 <__udivmoddi4+0x11e>
 8000cf6:	18fb      	adds	r3, r7, r3
 8000cf8:	f10c 38ff 	add.w	r8, ip, #4294967295
 8000cfc:	d202      	bcs.n	8000d04 <__udivmoddi4+0x11c>
 8000cfe:	429a      	cmp	r2, r3
 8000d00:	f200 80e0 	bhi.w	8000ec4 <__udivmoddi4+0x2dc>
 8000d04:	46c4      	mov	ip, r8
 8000d06:	1a9b      	subs	r3, r3, r2
 8000d08:	fbb3 f2fe 	udiv	r2, r3, lr
 8000d0c:	fb0e 3312 	mls	r3, lr, r2, r3
 8000d10:	ea40 4303 	orr.w	r3, r0, r3, lsl #16
 8000d14:	fb02 f404 	mul.w	r4, r2, r4
 8000d18:	429c      	cmp	r4, r3
 8000d1a:	d907      	bls.n	8000d2c <__udivmoddi4+0x144>
 8000d1c:	18fb      	adds	r3, r7, r3
 8000d1e:	f102 30ff 	add.w	r0, r2, #4294967295
 8000d22:	d202      	bcs.n	8000d2a <__udivmoddi4+0x142>
 8000d24:	429c      	cmp	r4, r3
 8000d26:	f200 80ca 	bhi.w	8000ebe <__udivmoddi4+0x2d6>
 8000d2a:	4602      	mov	r2, r0
 8000d2c:	1b1b      	subs	r3, r3, r4
 8000d2e:	ea42 400c 	orr.w	r0, r2, ip, lsl #16
 8000d32:	e7a5      	b.n	8000c80 <__udivmoddi4+0x98>
 8000d34:	f1c1 0620 	rsb	r6, r1, #32
 8000d38:	408b      	lsls	r3, r1
 8000d3a:	fa22 f706 	lsr.w	r7, r2, r6
 8000d3e:	431f      	orrs	r7, r3
 8000d40:	fa0e f401 	lsl.w	r4, lr, r1
 8000d44:	fa20 f306 	lsr.w	r3, r0, r6
 8000d48:	fa2e fe06 	lsr.w	lr, lr, r6
 8000d4c:	ea4f 4917 	mov.w	r9, r7, lsr #16
 8000d50:	4323      	orrs	r3, r4
 8000d52:	fa00 f801 	lsl.w	r8, r0, r1
 8000d56:	fa1f fc87 	uxth.w	ip, r7
 8000d5a:	fbbe f0f9 	udiv	r0, lr, r9
 8000d5e:	0c1c      	lsrs	r4, r3, #16
 8000d60:	fb09 ee10 	mls	lr, r9, r0, lr
 8000d64:	ea44 440e 	orr.w	r4, r4, lr, lsl #16
 8000d68:	fb00 fe0c 	mul.w	lr, r0, ip
 8000d6c:	45a6      	cmp	lr, r4
 8000d6e:	fa02 f201 	lsl.w	r2, r2, r1
 8000d72:	d909      	bls.n	8000d88 <__udivmoddi4+0x1a0>
 8000d74:	193c      	adds	r4, r7, r4
 8000d76:	f100 3aff 	add.w	sl, r0, #4294967295
 8000d7a:	f080 809c 	bcs.w	8000eb6 <__udivmoddi4+0x2ce>
 8000d7e:	45a6      	cmp	lr, r4
 8000d80:	f240 8099 	bls.w	8000eb6 <__udivmoddi4+0x2ce>
 8000d84:	3802      	subs	r0, #2
 8000d86:	443c      	add	r4, r7
 8000d88:	eba4 040e 	sub.w	r4, r4, lr
 8000d8c:	fa1f fe83 	uxth.w	lr, r3
 8000d90:	fbb4 f3f9 	udiv	r3, r4, r9
 8000d94:	fb09 4413 	mls	r4, r9, r3, r4
 8000d98:	ea4e 4404 	orr.w	r4, lr, r4, lsl #16
 8000d9c:	fb03 fc0c 	mul.w	ip, r3, ip
 8000da0:	45a4      	cmp	ip, r4
 8000da2:	d908      	bls.n	8000db6 <__udivmoddi4+0x1ce>
 8000da4:	193c      	adds	r4, r7, r4
 8000da6:	f103 3eff 	add.w	lr, r3, #4294967295
 8000daa:	f080 8082 	bcs.w	8000eb2 <__udivmoddi4+0x2ca>
 8000dae:	45a4      	cmp	ip, r4
 8000db0:	d97f      	bls.n	8000eb2 <__udivmoddi4+0x2ca>
 8000db2:	3b02      	subs	r3, #2
 8000db4:	443c      	add	r4, r7
 8000db6:	ea43 4000 	orr.w	r0, r3, r0, lsl #16
 8000dba:	eba4 040c 	sub.w	r4, r4, ip
 8000dbe:	fba0 ec02 	umull	lr, ip, r0, r2
 8000dc2:	4564      	cmp	r4, ip
 8000dc4:	4673      	mov	r3, lr
 8000dc6:	46e1      	mov	r9, ip
 8000dc8:	d362      	bcc.n	8000e90 <__udivmoddi4+0x2a8>
 8000dca:	d05f      	beq.n	8000e8c <__udivmoddi4+0x2a4>
 8000dcc:	b15d      	cbz	r5, 8000de6 <__udivmoddi4+0x1fe>
 8000dce:	ebb8 0203 	subs.w	r2, r8, r3
 8000dd2:	eb64 0409 	sbc.w	r4, r4, r9
 8000dd6:	fa04 f606 	lsl.w	r6, r4, r6
 8000dda:	fa22 f301 	lsr.w	r3, r2, r1
 8000dde:	431e      	orrs	r6, r3
 8000de0:	40cc      	lsrs	r4, r1
 8000de2:	e9c5 6400 	strd	r6, r4, [r5]
 8000de6:	2100      	movs	r1, #0
 8000de8:	e74f      	b.n	8000c8a <__udivmoddi4+0xa2>
 8000dea:	fbb1 fcf2 	udiv	ip, r1, r2
 8000dee:	0c01      	lsrs	r1, r0, #16
 8000df0:	ea41 410e 	orr.w	r1, r1, lr, lsl #16
 8000df4:	b280      	uxth	r0, r0
 8000df6:	ea40 4201 	orr.w	r2, r0, r1, lsl #16
 8000dfa:	463b      	mov	r3, r7
 8000dfc:	4638      	mov	r0, r7
 8000dfe:	463c      	mov	r4, r7
 8000e00:	46b8      	mov	r8, r7
 8000e02:	46be      	mov	lr, r7
 8000e04:	2620      	movs	r6, #32
 8000e06:	fbb1 f1f7 	udiv	r1, r1, r7
 8000e0a:	eba2 0208 	sub.w	r2, r2, r8
 8000e0e:	ea41 410c 	orr.w	r1, r1, ip, lsl #16
 8000e12:	e766      	b.n	8000ce2 <__udivmoddi4+0xfa>
 8000e14:	4601      	mov	r1, r0
 8000e16:	e718      	b.n	8000c4a <__udivmoddi4+0x62>
 8000e18:	4610      	mov	r0, r2
 8000e1a:	e72c      	b.n	8000c76 <__udivmoddi4+0x8e>
 8000e1c:	f1c6 0220 	rsb	r2, r6, #32
 8000e20:	fa2e f302 	lsr.w	r3, lr, r2
 8000e24:	40b7      	lsls	r7, r6
 8000e26:	40b1      	lsls	r1, r6
 8000e28:	fa20 f202 	lsr.w	r2, r0, r2
 8000e2c:	ea4f 4e17 	mov.w	lr, r7, lsr #16
 8000e30:	430a      	orrs	r2, r1
 8000e32:	fbb3 f8fe 	udiv	r8, r3, lr
 8000e36:	b2bc      	uxth	r4, r7
 8000e38:	fb0e 3318 	mls	r3, lr, r8, r3
 8000e3c:	0c11      	lsrs	r1, r2, #16
 8000e3e:	ea41 4103 	orr.w	r1, r1, r3, lsl #16
 8000e42:	fb08 f904 	mul.w	r9, r8, r4
 8000e46:	40b0      	lsls	r0, r6
 8000e48:	4589      	cmp	r9, r1
 8000e4a:	ea4f 4310 	mov.w	r3, r0, lsr #16
 8000e4e:	b280      	uxth	r0, r0
 8000e50:	d93e      	bls.n	8000ed0 <__udivmoddi4+0x2e8>
 8000e52:	1879      	adds	r1, r7, r1
 8000e54:	f108 3cff 	add.w	ip, r8, #4294967295
 8000e58:	d201      	bcs.n	8000e5e <__udivmoddi4+0x276>
 8000e5a:	4589      	cmp	r9, r1
 8000e5c:	d81f      	bhi.n	8000e9e <__udivmoddi4+0x2b6>
 8000e5e:	eba1 0109 	sub.w	r1, r1, r9
 8000e62:	fbb1 f9fe 	udiv	r9, r1, lr
 8000e66:	fb09 f804 	mul.w	r8, r9, r4
 8000e6a:	fb0e 1119 	mls	r1, lr, r9, r1
 8000e6e:	b292      	uxth	r2, r2
 8000e70:	ea42 4201 	orr.w	r2, r2, r1, lsl #16
 8000e74:	4542      	cmp	r2, r8
 8000e76:	d229      	bcs.n	8000ecc <__udivmoddi4+0x2e4>
 8000e78:	18ba      	adds	r2, r7, r2
 8000e7a:	f109 31ff 	add.w	r1, r9, #4294967295
 8000e7e:	d2c4      	bcs.n	8000e0a <__udivmoddi4+0x222>
 8000e80:	4542      	cmp	r2, r8
 8000e82:	d2c2      	bcs.n	8000e0a <__udivmoddi4+0x222>
 8000e84:	f1a9 0102 	sub.w	r1, r9, #2
 8000e88:	443a      	add	r2, r7
 8000e8a:	e7be      	b.n	8000e0a <__udivmoddi4+0x222>
 8000e8c:	45f0      	cmp	r8, lr
 8000e8e:	d29d      	bcs.n	8000dcc <__udivmoddi4+0x1e4>
 8000e90:	ebbe 0302 	subs.w	r3, lr, r2
 8000e94:	eb6c 0c07 	sbc.w	ip, ip, r7
 8000e98:	3801      	subs	r0, #1
 8000e9a:	46e1      	mov	r9, ip
 8000e9c:	e796      	b.n	8000dcc <__udivmoddi4+0x1e4>
 8000e9e:	eba7 0909 	sub.w	r9, r7, r9
 8000ea2:	4449      	add	r1, r9
 8000ea4:	f1a8 0c02 	sub.w	ip, r8, #2
 8000ea8:	fbb1 f9fe 	udiv	r9, r1, lr
 8000eac:	fb09 f804 	mul.w	r8, r9, r4
 8000eb0:	e7db      	b.n	8000e6a <__udivmoddi4+0x282>
 8000eb2:	4673      	mov	r3, lr
 8000eb4:	e77f      	b.n	8000db6 <__udivmoddi4+0x1ce>
 8000eb6:	4650      	mov	r0, sl
 8000eb8:	e766      	b.n	8000d88 <__udivmoddi4+0x1a0>
 8000eba:	4608      	mov	r0, r1
 8000ebc:	e6fd      	b.n	8000cba <__udivmoddi4+0xd2>
 8000ebe:	443b      	add	r3, r7
 8000ec0:	3a02      	subs	r2, #2
 8000ec2:	e733      	b.n	8000d2c <__udivmoddi4+0x144>
 8000ec4:	f1ac 0c02 	sub.w	ip, ip, #2
 8000ec8:	443b      	add	r3, r7
 8000eca:	e71c      	b.n	8000d06 <__udivmoddi4+0x11e>
 8000ecc:	4649      	mov	r1, r9
 8000ece:	e79c      	b.n	8000e0a <__udivmoddi4+0x222>
 8000ed0:	eba1 0109 	sub.w	r1, r1, r9
 8000ed4:	46c4      	mov	ip, r8
 8000ed6:	fbb1 f9fe 	udiv	r9, r1, lr
 8000eda:	fb09 f804 	mul.w	r8, r9, r4
 8000ede:	e7c4      	b.n	8000e6a <__udivmoddi4+0x282>

08000ee0 <__aeabi_idiv0>:
 8000ee0:	4770      	bx	lr
 8000ee2:	bf00      	nop

08000ee4 <FusionDegreesToRadians>:
/**
 * @brief Converts degrees to radians.
 * @param degrees Degrees.
 * @return Radians.
 */
static inline float FusionDegreesToRadians(const float degrees) {
 8000ee4:	b480      	push	{r7}
 8000ee6:	b083      	sub	sp, #12
 8000ee8:	af00      	add	r7, sp, #0
 8000eea:	ed87 0a01 	vstr	s0, [r7, #4]
    return degrees * ((float) M_PI / 180.0f);
 8000eee:	edd7 7a01 	vldr	s15, [r7, #4]
 8000ef2:	ed9f 7a05 	vldr	s14, [pc, #20]	@ 8000f08 <FusionDegreesToRadians+0x24>
 8000ef6:	ee67 7a87 	vmul.f32	s15, s15, s14
}
 8000efa:	eeb0 0a67 	vmov.f32	s0, s15
 8000efe:	370c      	adds	r7, #12
 8000f00:	46bd      	mov	sp, r7
 8000f02:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000f06:	4770      	bx	lr
 8000f08:	3c8efa35 	.word	0x3c8efa35

08000f0c <FusionRadiansToDegrees>:
/**
 * @brief Converts radians to degrees.
 * @param radians Radians.
 * @return Degrees.
 */
static inline float FusionRadiansToDegrees(const float radians) {
 8000f0c:	b480      	push	{r7}
 8000f0e:	b083      	sub	sp, #12
 8000f10:	af00      	add	r7, sp, #0
 8000f12:	ed87 0a01 	vstr	s0, [r7, #4]
    return radians * (180.0f / (float) M_PI);
 8000f16:	edd7 7a01 	vldr	s15, [r7, #4]
 8000f1a:	ed9f 7a05 	vldr	s14, [pc, #20]	@ 8000f30 <FusionRadiansToDegrees+0x24>
 8000f1e:	ee67 7a87 	vmul.f32	s15, s15, s14
}
 8000f22:	eeb0 0a67 	vmov.f32	s0, s15
 8000f26:	370c      	adds	r7, #12
 8000f28:	46bd      	mov	sp, r7
 8000f2a:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000f2e:	4770      	bx	lr
 8000f30:	42652ee0 	.word	0x42652ee0

08000f34 <FusionAsin>:
/**
 * @brief Returns the arc sine of the value.
 * @param value Value.
 * @return Arc sine of the value.
 */
static inline float FusionAsin(const float value) {
 8000f34:	b580      	push	{r7, lr}
 8000f36:	b082      	sub	sp, #8
 8000f38:	af00      	add	r7, sp, #0
 8000f3a:	ed87 0a01 	vstr	s0, [r7, #4]
    if (value <= -1.0f) {
 8000f3e:	edd7 7a01 	vldr	s15, [r7, #4]
 8000f42:	eebf 7a00 	vmov.f32	s14, #240	@ 0xbf800000 -1.0
 8000f46:	eef4 7ac7 	vcmpe.f32	s15, s14
 8000f4a:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8000f4e:	d802      	bhi.n	8000f56 <FusionAsin+0x22>
        return (float) M_PI / -2.0f;
 8000f50:	eddf 7a0c 	vldr	s15, [pc, #48]	@ 8000f84 <FusionAsin+0x50>
 8000f54:	e011      	b.n	8000f7a <FusionAsin+0x46>
    }
    if (value >= 1.0f) {
 8000f56:	edd7 7a01 	vldr	s15, [r7, #4]
 8000f5a:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 8000f5e:	eef4 7ac7 	vcmpe.f32	s15, s14
 8000f62:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8000f66:	db02      	blt.n	8000f6e <FusionAsin+0x3a>
        return (float) M_PI / 2.0f;
 8000f68:	eddf 7a07 	vldr	s15, [pc, #28]	@ 8000f88 <FusionAsin+0x54>
 8000f6c:	e005      	b.n	8000f7a <FusionAsin+0x46>
    }
    return asinf(value);
 8000f6e:	ed97 0a01 	vldr	s0, [r7, #4]
 8000f72:	f009 f89b 	bl	800a0ac <asinf>
 8000f76:	eef0 7a40 	vmov.f32	s15, s0
}
 8000f7a:	eeb0 0a67 	vmov.f32	s0, s15
 8000f7e:	3708      	adds	r7, #8
 8000f80:	46bd      	mov	sp, r7
 8000f82:	bd80      	pop	{r7, pc}
 8000f84:	bfc90fdb 	.word	0xbfc90fdb
 8000f88:	3fc90fdb 	.word	0x3fc90fdb

08000f8c <FusionFastInverseSqrt>:
 * @brief Calculates the reciprocal of the square root.
 * See https://pizer.wordpress.com/2008/10/12/fast-inverse-square-root/
 * @param x Operand.
 * @return Reciprocal of the square root of x.
 */
static inline float FusionFastInverseSqrt(const float x) {
 8000f8c:	b480      	push	{r7}
 8000f8e:	b085      	sub	sp, #20
 8000f90:	af00      	add	r7, sp, #0
 8000f92:	ed87 0a01 	vstr	s0, [r7, #4]
    typedef union {
        float f;
        int32_t i;
    } Union32;

    Union32 union32 = {.f = x};
 8000f96:	687b      	ldr	r3, [r7, #4]
 8000f98:	60fb      	str	r3, [r7, #12]
    union32.i = 0x5F1F1412 - (union32.i >> 1);
 8000f9a:	68fb      	ldr	r3, [r7, #12]
 8000f9c:	105a      	asrs	r2, r3, #1
 8000f9e:	4b10      	ldr	r3, [pc, #64]	@ (8000fe0 <FusionFastInverseSqrt+0x54>)
 8000fa0:	1a9b      	subs	r3, r3, r2
 8000fa2:	60fb      	str	r3, [r7, #12]
    return union32.f * (1.69000231f - 0.714158168f * x * union32.f * union32.f);
 8000fa4:	ed97 7a03 	vldr	s14, [r7, #12]
 8000fa8:	edd7 7a01 	vldr	s15, [r7, #4]
 8000fac:	eddf 6a0d 	vldr	s13, [pc, #52]	@ 8000fe4 <FusionFastInverseSqrt+0x58>
 8000fb0:	ee67 6aa6 	vmul.f32	s13, s15, s13
 8000fb4:	edd7 7a03 	vldr	s15, [r7, #12]
 8000fb8:	ee66 6aa7 	vmul.f32	s13, s13, s15
 8000fbc:	edd7 7a03 	vldr	s15, [r7, #12]
 8000fc0:	ee66 7aa7 	vmul.f32	s15, s13, s15
 8000fc4:	eddf 6a08 	vldr	s13, [pc, #32]	@ 8000fe8 <FusionFastInverseSqrt+0x5c>
 8000fc8:	ee76 7ae7 	vsub.f32	s15, s13, s15
 8000fcc:	ee67 7a27 	vmul.f32	s15, s14, s15
}
 8000fd0:	eeb0 0a67 	vmov.f32	s0, s15
 8000fd4:	3714      	adds	r7, #20
 8000fd6:	46bd      	mov	sp, r7
 8000fd8:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000fdc:	4770      	bx	lr
 8000fde:	bf00      	nop
 8000fe0:	5f1f1412 	.word	0x5f1f1412
 8000fe4:	3f36d312 	.word	0x3f36d312
 8000fe8:	3fd851ff 	.word	0x3fd851ff

08000fec <FusionVectorIsZero>:
/**
 * @brief Returns true if the vector is zero.
 * @param vector Vector.
 * @return True if the vector is zero.
 */
static inline bool FusionVectorIsZero(const FusionVector vector) {
 8000fec:	b480      	push	{r7}
 8000fee:	b085      	sub	sp, #20
 8000ff0:	af00      	add	r7, sp, #0
 8000ff2:	eef0 6a40 	vmov.f32	s13, s0
 8000ff6:	eeb0 7a60 	vmov.f32	s14, s1
 8000ffa:	eef0 7a41 	vmov.f32	s15, s2
 8000ffe:	edc7 6a01 	vstr	s13, [r7, #4]
 8001002:	ed87 7a02 	vstr	s14, [r7, #8]
 8001006:	edc7 7a03 	vstr	s15, [r7, #12]
    return (vector.axis.x == 0.0f) && (vector.axis.y == 0.0f) && (vector.axis.z == 0.0f);
 800100a:	edd7 7a01 	vldr	s15, [r7, #4]
 800100e:	eef5 7a40 	vcmp.f32	s15, #0.0
 8001012:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8001016:	d10f      	bne.n	8001038 <FusionVectorIsZero+0x4c>
 8001018:	edd7 7a02 	vldr	s15, [r7, #8]
 800101c:	eef5 7a40 	vcmp.f32	s15, #0.0
 8001020:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8001024:	d108      	bne.n	8001038 <FusionVectorIsZero+0x4c>
 8001026:	edd7 7a03 	vldr	s15, [r7, #12]
 800102a:	eef5 7a40 	vcmp.f32	s15, #0.0
 800102e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8001032:	d101      	bne.n	8001038 <FusionVectorIsZero+0x4c>
 8001034:	2301      	movs	r3, #1
 8001036:	e000      	b.n	800103a <FusionVectorIsZero+0x4e>
 8001038:	2300      	movs	r3, #0
 800103a:	f003 0301 	and.w	r3, r3, #1
 800103e:	b2db      	uxtb	r3, r3
}
 8001040:	4618      	mov	r0, r3
 8001042:	3714      	adds	r7, #20
 8001044:	46bd      	mov	sp, r7
 8001046:	f85d 7b04 	ldr.w	r7, [sp], #4
 800104a:	4770      	bx	lr

0800104c <FusionVectorAdd>:
 * @brief Returns the sum of two vectors.
 * @param vectorA Vector A.
 * @param vectorB Vector B.
 * @return Sum of two vectors.
 */
static inline FusionVector FusionVectorAdd(const FusionVector vectorA, const FusionVector vectorB) {
 800104c:	b480      	push	{r7}
 800104e:	b091      	sub	sp, #68	@ 0x44
 8001050:	af00      	add	r7, sp, #0
 8001052:	eeb0 5a40 	vmov.f32	s10, s0
 8001056:	eef0 5a60 	vmov.f32	s11, s1
 800105a:	eeb0 6a41 	vmov.f32	s12, s2
 800105e:	eef0 6a61 	vmov.f32	s13, s3
 8001062:	eeb0 7a42 	vmov.f32	s14, s4
 8001066:	eef0 7a62 	vmov.f32	s15, s5
 800106a:	ed87 5a07 	vstr	s10, [r7, #28]
 800106e:	edc7 5a08 	vstr	s11, [r7, #32]
 8001072:	ed87 6a09 	vstr	s12, [r7, #36]	@ 0x24
 8001076:	edc7 6a04 	vstr	s13, [r7, #16]
 800107a:	ed87 7a05 	vstr	s14, [r7, #20]
 800107e:	edc7 7a06 	vstr	s15, [r7, #24]
    const FusionVector result = {.axis = {
            .x = vectorA.axis.x + vectorB.axis.x,
 8001082:	ed97 7a07 	vldr	s14, [r7, #28]
 8001086:	edd7 7a04 	vldr	s15, [r7, #16]
 800108a:	ee77 7a27 	vadd.f32	s15, s14, s15
    const FusionVector result = {.axis = {
 800108e:	edc7 7a0a 	vstr	s15, [r7, #40]	@ 0x28
            .y = vectorA.axis.y + vectorB.axis.y,
 8001092:	ed97 7a08 	vldr	s14, [r7, #32]
 8001096:	edd7 7a05 	vldr	s15, [r7, #20]
 800109a:	ee77 7a27 	vadd.f32	s15, s14, s15
    const FusionVector result = {.axis = {
 800109e:	edc7 7a0b 	vstr	s15, [r7, #44]	@ 0x2c
            .z = vectorA.axis.z + vectorB.axis.z,
 80010a2:	ed97 7a09 	vldr	s14, [r7, #36]	@ 0x24
 80010a6:	edd7 7a06 	vldr	s15, [r7, #24]
 80010aa:	ee77 7a27 	vadd.f32	s15, s14, s15
    const FusionVector result = {.axis = {
 80010ae:	edc7 7a0c 	vstr	s15, [r7, #48]	@ 0x30
    }};
    return result;
 80010b2:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 80010b6:	f107 0228 	add.w	r2, r7, #40	@ 0x28
 80010ba:	ca07      	ldmia	r2, {r0, r1, r2}
 80010bc:	e883 0007 	stmia.w	r3, {r0, r1, r2}
 80010c0:	6b79      	ldr	r1, [r7, #52]	@ 0x34
 80010c2:	6bba      	ldr	r2, [r7, #56]	@ 0x38
 80010c4:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 80010c6:	ee06 1a90 	vmov	s13, r1
 80010ca:	ee07 2a10 	vmov	s14, r2
 80010ce:	ee07 3a90 	vmov	s15, r3
}
 80010d2:	eeb0 0a66 	vmov.f32	s0, s13
 80010d6:	eef0 0a47 	vmov.f32	s1, s14
 80010da:	eeb0 1a67 	vmov.f32	s2, s15
 80010de:	3744      	adds	r7, #68	@ 0x44
 80010e0:	46bd      	mov	sp, r7
 80010e2:	f85d 7b04 	ldr.w	r7, [sp], #4
 80010e6:	4770      	bx	lr

080010e8 <FusionVectorSum>:
/**
 * @brief Returns the sum of the elements.
 * @param vector Vector.
 * @return Sum of the elements.
 */
static inline float FusionVectorSum(const FusionVector vector) {
 80010e8:	b480      	push	{r7}
 80010ea:	b085      	sub	sp, #20
 80010ec:	af00      	add	r7, sp, #0
 80010ee:	eef0 6a40 	vmov.f32	s13, s0
 80010f2:	eeb0 7a60 	vmov.f32	s14, s1
 80010f6:	eef0 7a41 	vmov.f32	s15, s2
 80010fa:	edc7 6a01 	vstr	s13, [r7, #4]
 80010fe:	ed87 7a02 	vstr	s14, [r7, #8]
 8001102:	edc7 7a03 	vstr	s15, [r7, #12]
    return vector.axis.x + vector.axis.y + vector.axis.z;
 8001106:	ed97 7a01 	vldr	s14, [r7, #4]
 800110a:	edd7 7a02 	vldr	s15, [r7, #8]
 800110e:	ee37 7a27 	vadd.f32	s14, s14, s15
 8001112:	edd7 7a03 	vldr	s15, [r7, #12]
 8001116:	ee77 7a27 	vadd.f32	s15, s14, s15
}
 800111a:	eeb0 0a67 	vmov.f32	s0, s15
 800111e:	3714      	adds	r7, #20
 8001120:	46bd      	mov	sp, r7
 8001122:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001126:	4770      	bx	lr

08001128 <FusionVectorMultiplyScalar>:
 * @brief Returns the multiplication of a vector by a scalar.
 * @param vector Vector.
 * @param scalar Scalar.
 * @return Multiplication of a vector by a scalar.
 */
static inline FusionVector FusionVectorMultiplyScalar(const FusionVector vector, const float scalar) {
 8001128:	b480      	push	{r7}
 800112a:	b08f      	sub	sp, #60	@ 0x3c
 800112c:	af00      	add	r7, sp, #0
 800112e:	eef0 6a40 	vmov.f32	s13, s0
 8001132:	eeb0 7a60 	vmov.f32	s14, s1
 8001136:	eef0 7a41 	vmov.f32	s15, s2
 800113a:	edc7 1a04 	vstr	s3, [r7, #16]
 800113e:	edc7 6a05 	vstr	s13, [r7, #20]
 8001142:	ed87 7a06 	vstr	s14, [r7, #24]
 8001146:	edc7 7a07 	vstr	s15, [r7, #28]
    const FusionVector result = {.axis = {
            .x = vector.axis.x * scalar,
 800114a:	ed97 7a05 	vldr	s14, [r7, #20]
 800114e:	edd7 7a04 	vldr	s15, [r7, #16]
 8001152:	ee67 7a27 	vmul.f32	s15, s14, s15
    const FusionVector result = {.axis = {
 8001156:	edc7 7a08 	vstr	s15, [r7, #32]
            .y = vector.axis.y * scalar,
 800115a:	ed97 7a06 	vldr	s14, [r7, #24]
 800115e:	edd7 7a04 	vldr	s15, [r7, #16]
 8001162:	ee67 7a27 	vmul.f32	s15, s14, s15
    const FusionVector result = {.axis = {
 8001166:	edc7 7a09 	vstr	s15, [r7, #36]	@ 0x24
            .z = vector.axis.z * scalar,
 800116a:	ed97 7a07 	vldr	s14, [r7, #28]
 800116e:	edd7 7a04 	vldr	s15, [r7, #16]
 8001172:	ee67 7a27 	vmul.f32	s15, s14, s15
    const FusionVector result = {.axis = {
 8001176:	edc7 7a0a 	vstr	s15, [r7, #40]	@ 0x28
    }};
    return result;
 800117a:	f107 032c 	add.w	r3, r7, #44	@ 0x2c
 800117e:	f107 0220 	add.w	r2, r7, #32
 8001182:	ca07      	ldmia	r2, {r0, r1, r2}
 8001184:	e883 0007 	stmia.w	r3, {r0, r1, r2}
 8001188:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
 800118a:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 800118c:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 800118e:	ee06 1a90 	vmov	s13, r1
 8001192:	ee07 2a10 	vmov	s14, r2
 8001196:	ee07 3a90 	vmov	s15, r3
}
 800119a:	eeb0 0a66 	vmov.f32	s0, s13
 800119e:	eef0 0a47 	vmov.f32	s1, s14
 80011a2:	eeb0 1a67 	vmov.f32	s2, s15
 80011a6:	373c      	adds	r7, #60	@ 0x3c
 80011a8:	46bd      	mov	sp, r7
 80011aa:	f85d 7b04 	ldr.w	r7, [sp], #4
 80011ae:	4770      	bx	lr

080011b0 <FusionVectorHadamardProduct>:
 * @brief Calculates the Hadamard product (element-wise multiplication).
 * @param vectorA Vector A.
 * @param vectorB Vector B.
 * @return Hadamard product.
 */
static inline FusionVector FusionVectorHadamardProduct(const FusionVector vectorA, const FusionVector vectorB) {
 80011b0:	b480      	push	{r7}
 80011b2:	b091      	sub	sp, #68	@ 0x44
 80011b4:	af00      	add	r7, sp, #0
 80011b6:	eeb0 5a40 	vmov.f32	s10, s0
 80011ba:	eef0 5a60 	vmov.f32	s11, s1
 80011be:	eeb0 6a41 	vmov.f32	s12, s2
 80011c2:	eef0 6a61 	vmov.f32	s13, s3
 80011c6:	eeb0 7a42 	vmov.f32	s14, s4
 80011ca:	eef0 7a62 	vmov.f32	s15, s5
 80011ce:	ed87 5a07 	vstr	s10, [r7, #28]
 80011d2:	edc7 5a08 	vstr	s11, [r7, #32]
 80011d6:	ed87 6a09 	vstr	s12, [r7, #36]	@ 0x24
 80011da:	edc7 6a04 	vstr	s13, [r7, #16]
 80011de:	ed87 7a05 	vstr	s14, [r7, #20]
 80011e2:	edc7 7a06 	vstr	s15, [r7, #24]
    const FusionVector result = {.axis = {
            .x = vectorA.axis.x * vectorB.axis.x,
 80011e6:	ed97 7a07 	vldr	s14, [r7, #28]
 80011ea:	edd7 7a04 	vldr	s15, [r7, #16]
 80011ee:	ee67 7a27 	vmul.f32	s15, s14, s15
    const FusionVector result = {.axis = {
 80011f2:	edc7 7a0a 	vstr	s15, [r7, #40]	@ 0x28
            .y = vectorA.axis.y * vectorB.axis.y,
 80011f6:	ed97 7a08 	vldr	s14, [r7, #32]
 80011fa:	edd7 7a05 	vldr	s15, [r7, #20]
 80011fe:	ee67 7a27 	vmul.f32	s15, s14, s15
    const FusionVector result = {.axis = {
 8001202:	edc7 7a0b 	vstr	s15, [r7, #44]	@ 0x2c
            .z = vectorA.axis.z * vectorB.axis.z,
 8001206:	ed97 7a09 	vldr	s14, [r7, #36]	@ 0x24
 800120a:	edd7 7a06 	vldr	s15, [r7, #24]
 800120e:	ee67 7a27 	vmul.f32	s15, s14, s15
    const FusionVector result = {.axis = {
 8001212:	edc7 7a0c 	vstr	s15, [r7, #48]	@ 0x30
    }};
    return result;
 8001216:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 800121a:	f107 0228 	add.w	r2, r7, #40	@ 0x28
 800121e:	ca07      	ldmia	r2, {r0, r1, r2}
 8001220:	e883 0007 	stmia.w	r3, {r0, r1, r2}
 8001224:	6b79      	ldr	r1, [r7, #52]	@ 0x34
 8001226:	6bba      	ldr	r2, [r7, #56]	@ 0x38
 8001228:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 800122a:	ee06 1a90 	vmov	s13, r1
 800122e:	ee07 2a10 	vmov	s14, r2
 8001232:	ee07 3a90 	vmov	s15, r3
}
 8001236:	eeb0 0a66 	vmov.f32	s0, s13
 800123a:	eef0 0a47 	vmov.f32	s1, s14
 800123e:	eeb0 1a67 	vmov.f32	s2, s15
 8001242:	3744      	adds	r7, #68	@ 0x44
 8001244:	46bd      	mov	sp, r7
 8001246:	f85d 7b04 	ldr.w	r7, [sp], #4
 800124a:	4770      	bx	lr

0800124c <FusionVectorCrossProduct>:
 * @brief Returns the cross product.
 * @param vectorA Vector A.
 * @param vectorB Vector B.
 * @return Cross product.
 */
static inline FusionVector FusionVectorCrossProduct(const FusionVector vectorA, const FusionVector vectorB) {
 800124c:	b480      	push	{r7}
 800124e:	b091      	sub	sp, #68	@ 0x44
 8001250:	af00      	add	r7, sp, #0
 8001252:	eeb0 5a40 	vmov.f32	s10, s0
 8001256:	eef0 5a60 	vmov.f32	s11, s1
 800125a:	eeb0 6a41 	vmov.f32	s12, s2
 800125e:	eef0 6a61 	vmov.f32	s13, s3
 8001262:	eeb0 7a42 	vmov.f32	s14, s4
 8001266:	eef0 7a62 	vmov.f32	s15, s5
 800126a:	ed87 5a07 	vstr	s10, [r7, #28]
 800126e:	edc7 5a08 	vstr	s11, [r7, #32]
 8001272:	ed87 6a09 	vstr	s12, [r7, #36]	@ 0x24
 8001276:	edc7 6a04 	vstr	s13, [r7, #16]
 800127a:	ed87 7a05 	vstr	s14, [r7, #20]
 800127e:	edc7 7a06 	vstr	s15, [r7, #24]
#define A vectorA.axis
#define B vectorB.axis
    const FusionVector result = {.axis = {
            .x = A.y * B.z - A.z * B.y,
 8001282:	ed97 7a08 	vldr	s14, [r7, #32]
 8001286:	edd7 7a06 	vldr	s15, [r7, #24]
 800128a:	ee27 7a27 	vmul.f32	s14, s14, s15
 800128e:	edd7 6a09 	vldr	s13, [r7, #36]	@ 0x24
 8001292:	edd7 7a05 	vldr	s15, [r7, #20]
 8001296:	ee66 7aa7 	vmul.f32	s15, s13, s15
 800129a:	ee77 7a67 	vsub.f32	s15, s14, s15
    const FusionVector result = {.axis = {
 800129e:	edc7 7a0a 	vstr	s15, [r7, #40]	@ 0x28
            .y = A.z * B.x - A.x * B.z,
 80012a2:	ed97 7a09 	vldr	s14, [r7, #36]	@ 0x24
 80012a6:	edd7 7a04 	vldr	s15, [r7, #16]
 80012aa:	ee27 7a27 	vmul.f32	s14, s14, s15
 80012ae:	edd7 6a07 	vldr	s13, [r7, #28]
 80012b2:	edd7 7a06 	vldr	s15, [r7, #24]
 80012b6:	ee66 7aa7 	vmul.f32	s15, s13, s15
 80012ba:	ee77 7a67 	vsub.f32	s15, s14, s15
    const FusionVector result = {.axis = {
 80012be:	edc7 7a0b 	vstr	s15, [r7, #44]	@ 0x2c
            .z = A.x * B.y - A.y * B.x,
 80012c2:	ed97 7a07 	vldr	s14, [r7, #28]
 80012c6:	edd7 7a05 	vldr	s15, [r7, #20]
 80012ca:	ee27 7a27 	vmul.f32	s14, s14, s15
 80012ce:	edd7 6a08 	vldr	s13, [r7, #32]
 80012d2:	edd7 7a04 	vldr	s15, [r7, #16]
 80012d6:	ee66 7aa7 	vmul.f32	s15, s13, s15
 80012da:	ee77 7a67 	vsub.f32	s15, s14, s15
    const FusionVector result = {.axis = {
 80012de:	edc7 7a0c 	vstr	s15, [r7, #48]	@ 0x30
    }};
    return result;
 80012e2:	f107 0334 	add.w	r3, r7, #52	@ 0x34
 80012e6:	f107 0228 	add.w	r2, r7, #40	@ 0x28
 80012ea:	ca07      	ldmia	r2, {r0, r1, r2}
 80012ec:	e883 0007 	stmia.w	r3, {r0, r1, r2}
 80012f0:	6b79      	ldr	r1, [r7, #52]	@ 0x34
 80012f2:	6bba      	ldr	r2, [r7, #56]	@ 0x38
 80012f4:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 80012f6:	ee06 1a90 	vmov	s13, r1
 80012fa:	ee07 2a10 	vmov	s14, r2
 80012fe:	ee07 3a90 	vmov	s15, r3
#undef A
#undef B
}
 8001302:	eeb0 0a66 	vmov.f32	s0, s13
 8001306:	eef0 0a47 	vmov.f32	s1, s14
 800130a:	eeb0 1a67 	vmov.f32	s2, s15
 800130e:	3744      	adds	r7, #68	@ 0x44
 8001310:	46bd      	mov	sp, r7
 8001312:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001316:	4770      	bx	lr

08001318 <FusionVectorDotProduct>:
 * @brief Returns the dot product.
 * @param vectorA Vector A.
 * @param vectorB Vector B.
 * @return Dot product.
 */
static inline float FusionVectorDotProduct(const FusionVector vectorA, const FusionVector vectorB) {
 8001318:	b580      	push	{r7, lr}
 800131a:	b08a      	sub	sp, #40	@ 0x28
 800131c:	af00      	add	r7, sp, #0
 800131e:	eeb0 5a40 	vmov.f32	s10, s0
 8001322:	eef0 5a60 	vmov.f32	s11, s1
 8001326:	eeb0 6a41 	vmov.f32	s12, s2
 800132a:	eef0 6a61 	vmov.f32	s13, s3
 800132e:	eeb0 7a42 	vmov.f32	s14, s4
 8001332:	eef0 7a62 	vmov.f32	s15, s5
 8001336:	ed87 5a03 	vstr	s10, [r7, #12]
 800133a:	edc7 5a04 	vstr	s11, [r7, #16]
 800133e:	ed87 6a05 	vstr	s12, [r7, #20]
 8001342:	edc7 6a00 	vstr	s13, [r7]
 8001346:	ed87 7a01 	vstr	s14, [r7, #4]
 800134a:	edc7 7a02 	vstr	s15, [r7, #8]
    return FusionVectorSum(FusionVectorHadamardProduct(vectorA, vectorB));
 800134e:	ed97 5a00 	vldr	s10, [r7]
 8001352:	edd7 5a01 	vldr	s11, [r7, #4]
 8001356:	ed97 6a02 	vldr	s12, [r7, #8]
 800135a:	edd7 6a03 	vldr	s13, [r7, #12]
 800135e:	ed97 7a04 	vldr	s14, [r7, #16]
 8001362:	edd7 7a05 	vldr	s15, [r7, #20]
 8001366:	eef0 1a45 	vmov.f32	s3, s10
 800136a:	eeb0 2a65 	vmov.f32	s4, s11
 800136e:	eef0 2a46 	vmov.f32	s5, s12
 8001372:	eeb0 0a66 	vmov.f32	s0, s13
 8001376:	eef0 0a47 	vmov.f32	s1, s14
 800137a:	eeb0 1a67 	vmov.f32	s2, s15
 800137e:	f7ff ff17 	bl	80011b0 <FusionVectorHadamardProduct>
 8001382:	eef0 6a40 	vmov.f32	s13, s0
 8001386:	eeb0 7a60 	vmov.f32	s14, s1
 800138a:	eef0 7a41 	vmov.f32	s15, s2
 800138e:	edc7 6a07 	vstr	s13, [r7, #28]
 8001392:	ed87 7a08 	vstr	s14, [r7, #32]
 8001396:	edc7 7a09 	vstr	s15, [r7, #36]	@ 0x24
 800139a:	edd7 6a07 	vldr	s13, [r7, #28]
 800139e:	ed97 7a08 	vldr	s14, [r7, #32]
 80013a2:	edd7 7a09 	vldr	s15, [r7, #36]	@ 0x24
 80013a6:	eeb0 0a66 	vmov.f32	s0, s13
 80013aa:	eef0 0a47 	vmov.f32	s1, s14
 80013ae:	eeb0 1a67 	vmov.f32	s2, s15
 80013b2:	f7ff fe99 	bl	80010e8 <FusionVectorSum>
 80013b6:	eef0 7a40 	vmov.f32	s15, s0
}
 80013ba:	eeb0 0a67 	vmov.f32	s0, s15
 80013be:	3728      	adds	r7, #40	@ 0x28
 80013c0:	46bd      	mov	sp, r7
 80013c2:	bd80      	pop	{r7, pc}

080013c4 <FusionVectorMagnitudeSquared>:
/**
 * @brief Returns the vector magnitude squared.
 * @param vector Vector.
 * @return Vector magnitude squared.
 */
static inline float FusionVectorMagnitudeSquared(const FusionVector vector) {
 80013c4:	b580      	push	{r7, lr}
 80013c6:	b088      	sub	sp, #32
 80013c8:	af00      	add	r7, sp, #0
 80013ca:	eef0 6a40 	vmov.f32	s13, s0
 80013ce:	eeb0 7a60 	vmov.f32	s14, s1
 80013d2:	eef0 7a41 	vmov.f32	s15, s2
 80013d6:	edc7 6a01 	vstr	s13, [r7, #4]
 80013da:	ed87 7a02 	vstr	s14, [r7, #8]
 80013de:	edc7 7a03 	vstr	s15, [r7, #12]
    return FusionVectorSum(FusionVectorHadamardProduct(vector, vector));
 80013e2:	ed97 5a01 	vldr	s10, [r7, #4]
 80013e6:	edd7 5a02 	vldr	s11, [r7, #8]
 80013ea:	ed97 6a03 	vldr	s12, [r7, #12]
 80013ee:	edd7 6a01 	vldr	s13, [r7, #4]
 80013f2:	ed97 7a02 	vldr	s14, [r7, #8]
 80013f6:	edd7 7a03 	vldr	s15, [r7, #12]
 80013fa:	eef0 1a45 	vmov.f32	s3, s10
 80013fe:	eeb0 2a65 	vmov.f32	s4, s11
 8001402:	eef0 2a46 	vmov.f32	s5, s12
 8001406:	eeb0 0a66 	vmov.f32	s0, s13
 800140a:	eef0 0a47 	vmov.f32	s1, s14
 800140e:	eeb0 1a67 	vmov.f32	s2, s15
 8001412:	f7ff fecd 	bl	80011b0 <FusionVectorHadamardProduct>
 8001416:	eef0 6a40 	vmov.f32	s13, s0
 800141a:	eeb0 7a60 	vmov.f32	s14, s1
 800141e:	eef0 7a41 	vmov.f32	s15, s2
 8001422:	edc7 6a05 	vstr	s13, [r7, #20]
 8001426:	ed87 7a06 	vstr	s14, [r7, #24]
 800142a:	edc7 7a07 	vstr	s15, [r7, #28]
 800142e:	edd7 6a05 	vldr	s13, [r7, #20]
 8001432:	ed97 7a06 	vldr	s14, [r7, #24]
 8001436:	edd7 7a07 	vldr	s15, [r7, #28]
 800143a:	eeb0 0a66 	vmov.f32	s0, s13
 800143e:	eef0 0a47 	vmov.f32	s1, s14
 8001442:	eeb0 1a67 	vmov.f32	s2, s15
 8001446:	f7ff fe4f 	bl	80010e8 <FusionVectorSum>
 800144a:	eef0 7a40 	vmov.f32	s15, s0
}
 800144e:	eeb0 0a67 	vmov.f32	s0, s15
 8001452:	3720      	adds	r7, #32
 8001454:	46bd      	mov	sp, r7
 8001456:	bd80      	pop	{r7, pc}

08001458 <FusionVectorMagnitude>:
/**
 * @brief Returns the vector magnitude.
 * @param vector Vector.
 * @return Vector magnitude.
 */
static inline float FusionVectorMagnitude(const FusionVector vector) {
 8001458:	b580      	push	{r7, lr}
 800145a:	b084      	sub	sp, #16
 800145c:	af00      	add	r7, sp, #0
 800145e:	eef0 6a40 	vmov.f32	s13, s0
 8001462:	eeb0 7a60 	vmov.f32	s14, s1
 8001466:	eef0 7a41 	vmov.f32	s15, s2
 800146a:	edc7 6a01 	vstr	s13, [r7, #4]
 800146e:	ed87 7a02 	vstr	s14, [r7, #8]
 8001472:	edc7 7a03 	vstr	s15, [r7, #12]
    return sqrtf(FusionVectorMagnitudeSquared(vector));
 8001476:	edd7 6a01 	vldr	s13, [r7, #4]
 800147a:	ed97 7a02 	vldr	s14, [r7, #8]
 800147e:	edd7 7a03 	vldr	s15, [r7, #12]
 8001482:	eeb0 0a66 	vmov.f32	s0, s13
 8001486:	eef0 0a47 	vmov.f32	s1, s14
 800148a:	eeb0 1a67 	vmov.f32	s2, s15
 800148e:	f7ff ff99 	bl	80013c4 <FusionVectorMagnitudeSquared>
 8001492:	eef0 7a40 	vmov.f32	s15, s0
 8001496:	eeb0 0a67 	vmov.f32	s0, s15
 800149a:	f008 fe8d 	bl	800a1b8 <sqrtf>
 800149e:	eef0 7a40 	vmov.f32	s15, s0
}
 80014a2:	eeb0 0a67 	vmov.f32	s0, s15
 80014a6:	3710      	adds	r7, #16
 80014a8:	46bd      	mov	sp, r7
 80014aa:	bd80      	pop	{r7, pc}

080014ac <FusionVectorNormalise>:
/**
 * @brief Returns the normalised vector.
 * @param vector Vector.
 * @return Normalised vector.
 */
static inline FusionVector FusionVectorNormalise(const FusionVector vector) {
 80014ac:	b580      	push	{r7, lr}
 80014ae:	b08c      	sub	sp, #48	@ 0x30
 80014b0:	af00      	add	r7, sp, #0
 80014b2:	eef0 6a40 	vmov.f32	s13, s0
 80014b6:	eeb0 7a60 	vmov.f32	s14, s1
 80014ba:	eef0 7a41 	vmov.f32	s15, s2
 80014be:	edc7 6a05 	vstr	s13, [r7, #20]
 80014c2:	ed87 7a06 	vstr	s14, [r7, #24]
 80014c6:	edc7 7a07 	vstr	s15, [r7, #28]
#ifdef FUSION_USE_NORMAL_SQRT
    const float magnitudeReciprocal = 1.0f / sqrtf(FusionVectorMagnitudeSquared(vector));
#else
    const float magnitudeReciprocal = FusionFastInverseSqrt(FusionVectorMagnitudeSquared(vector));
 80014ca:	edd7 6a05 	vldr	s13, [r7, #20]
 80014ce:	ed97 7a06 	vldr	s14, [r7, #24]
 80014d2:	edd7 7a07 	vldr	s15, [r7, #28]
 80014d6:	eeb0 0a66 	vmov.f32	s0, s13
 80014da:	eef0 0a47 	vmov.f32	s1, s14
 80014de:	eeb0 1a67 	vmov.f32	s2, s15
 80014e2:	f7ff ff6f 	bl	80013c4 <FusionVectorMagnitudeSquared>
 80014e6:	eef0 7a40 	vmov.f32	s15, s0
 80014ea:	eeb0 0a67 	vmov.f32	s0, s15
 80014ee:	f7ff fd4d 	bl	8000f8c <FusionFastInverseSqrt>
 80014f2:	ed87 0a0b 	vstr	s0, [r7, #44]	@ 0x2c
#endif
    return FusionVectorMultiplyScalar(vector, magnitudeReciprocal);
 80014f6:	edd7 6a05 	vldr	s13, [r7, #20]
 80014fa:	ed97 7a06 	vldr	s14, [r7, #24]
 80014fe:	edd7 7a07 	vldr	s15, [r7, #28]
 8001502:	edd7 1a0b 	vldr	s3, [r7, #44]	@ 0x2c
 8001506:	eeb0 0a66 	vmov.f32	s0, s13
 800150a:	eef0 0a47 	vmov.f32	s1, s14
 800150e:	eeb0 1a67 	vmov.f32	s2, s15
 8001512:	f7ff fe09 	bl	8001128 <FusionVectorMultiplyScalar>
 8001516:	eef0 6a40 	vmov.f32	s13, s0
 800151a:	eeb0 7a60 	vmov.f32	s14, s1
 800151e:	eef0 7a41 	vmov.f32	s15, s2
 8001522:	edc7 6a08 	vstr	s13, [r7, #32]
 8001526:	ed87 7a09 	vstr	s14, [r7, #36]	@ 0x24
 800152a:	edc7 7a0a 	vstr	s15, [r7, #40]	@ 0x28
 800152e:	6a39      	ldr	r1, [r7, #32]
 8001530:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8001532:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8001534:	ee06 1a90 	vmov	s13, r1
 8001538:	ee07 2a10 	vmov	s14, r2
 800153c:	ee07 3a90 	vmov	s15, r3
}
 8001540:	eeb0 0a66 	vmov.f32	s0, s13
 8001544:	eef0 0a47 	vmov.f32	s1, s14
 8001548:	eeb0 1a67 	vmov.f32	s2, s15
 800154c:	3730      	adds	r7, #48	@ 0x30
 800154e:	46bd      	mov	sp, r7
 8001550:	bd80      	pop	{r7, pc}

08001552 <FusionQuaternionAdd>:
 * @brief Returns the sum of two quaternions.
 * @param quaternionA Quaternion A.
 * @param quaternionB Quaternion B.
 * @return Sum of two quaternions.
 */
static inline FusionQuaternion FusionQuaternionAdd(const FusionQuaternion quaternionA, const FusionQuaternion quaternionB) {
 8001552:	b490      	push	{r4, r7}
 8001554:	b094      	sub	sp, #80	@ 0x50
 8001556:	af00      	add	r7, sp, #0
 8001558:	eeb0 4a40 	vmov.f32	s8, s0
 800155c:	eef0 4a60 	vmov.f32	s9, s1
 8001560:	eeb0 5a41 	vmov.f32	s10, s2
 8001564:	eef0 5a61 	vmov.f32	s11, s3
 8001568:	eeb0 6a42 	vmov.f32	s12, s4
 800156c:	eef0 6a62 	vmov.f32	s13, s5
 8001570:	eeb0 7a43 	vmov.f32	s14, s6
 8001574:	eef0 7a63 	vmov.f32	s15, s7
 8001578:	ed87 4a08 	vstr	s8, [r7, #32]
 800157c:	edc7 4a09 	vstr	s9, [r7, #36]	@ 0x24
 8001580:	ed87 5a0a 	vstr	s10, [r7, #40]	@ 0x28
 8001584:	edc7 5a0b 	vstr	s11, [r7, #44]	@ 0x2c
 8001588:	ed87 6a04 	vstr	s12, [r7, #16]
 800158c:	edc7 6a05 	vstr	s13, [r7, #20]
 8001590:	ed87 7a06 	vstr	s14, [r7, #24]
 8001594:	edc7 7a07 	vstr	s15, [r7, #28]
    const FusionQuaternion result = {.element = {
            .w = quaternionA.element.w + quaternionB.element.w,
 8001598:	ed97 7a08 	vldr	s14, [r7, #32]
 800159c:	edd7 7a04 	vldr	s15, [r7, #16]
 80015a0:	ee77 7a27 	vadd.f32	s15, s14, s15
    const FusionQuaternion result = {.element = {
 80015a4:	edc7 7a0c 	vstr	s15, [r7, #48]	@ 0x30
            .x = quaternionA.element.x + quaternionB.element.x,
 80015a8:	ed97 7a09 	vldr	s14, [r7, #36]	@ 0x24
 80015ac:	edd7 7a05 	vldr	s15, [r7, #20]
 80015b0:	ee77 7a27 	vadd.f32	s15, s14, s15
    const FusionQuaternion result = {.element = {
 80015b4:	edc7 7a0d 	vstr	s15, [r7, #52]	@ 0x34
            .y = quaternionA.element.y + quaternionB.element.y,
 80015b8:	ed97 7a0a 	vldr	s14, [r7, #40]	@ 0x28
 80015bc:	edd7 7a06 	vldr	s15, [r7, #24]
 80015c0:	ee77 7a27 	vadd.f32	s15, s14, s15
    const FusionQuaternion result = {.element = {
 80015c4:	edc7 7a0e 	vstr	s15, [r7, #56]	@ 0x38
            .z = quaternionA.element.z + quaternionB.element.z,
 80015c8:	ed97 7a0b 	vldr	s14, [r7, #44]	@ 0x2c
 80015cc:	edd7 7a07 	vldr	s15, [r7, #28]
 80015d0:	ee77 7a27 	vadd.f32	s15, s14, s15
    const FusionQuaternion result = {.element = {
 80015d4:	edc7 7a0f 	vstr	s15, [r7, #60]	@ 0x3c
    }};
    return result;
 80015d8:	f107 0440 	add.w	r4, r7, #64	@ 0x40
 80015dc:	f107 0330 	add.w	r3, r7, #48	@ 0x30
 80015e0:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
 80015e2:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
 80015e6:	6c38      	ldr	r0, [r7, #64]	@ 0x40
 80015e8:	6c79      	ldr	r1, [r7, #68]	@ 0x44
 80015ea:	6cba      	ldr	r2, [r7, #72]	@ 0x48
 80015ec:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 80015ee:	ee06 0a10 	vmov	s12, r0
 80015f2:	ee06 1a90 	vmov	s13, r1
 80015f6:	ee07 2a10 	vmov	s14, r2
 80015fa:	ee07 3a90 	vmov	s15, r3
}
 80015fe:	eeb0 0a46 	vmov.f32	s0, s12
 8001602:	eef0 0a66 	vmov.f32	s1, s13
 8001606:	eeb0 1a47 	vmov.f32	s2, s14
 800160a:	eef0 1a67 	vmov.f32	s3, s15
 800160e:	3750      	adds	r7, #80	@ 0x50
 8001610:	46bd      	mov	sp, r7
 8001612:	bc90      	pop	{r4, r7}
 8001614:	4770      	bx	lr

08001616 <FusionQuaternionMultiplyVector>:
 * multiplied by the vector.
 * @param quaternion Quaternion.
 * @param vector Vector.
 * @return Multiplication of a quaternion with a vector.
 */
static inline FusionQuaternion FusionQuaternionMultiplyVector(const FusionQuaternion quaternion, const FusionVector vector) {
 8001616:	b490      	push	{r4, r7}
 8001618:	b094      	sub	sp, #80	@ 0x50
 800161a:	af00      	add	r7, sp, #0
 800161c:	eef0 4a40 	vmov.f32	s9, s0
 8001620:	eeb0 5a60 	vmov.f32	s10, s1
 8001624:	eef0 5a41 	vmov.f32	s11, s2
 8001628:	eeb0 6a61 	vmov.f32	s12, s3
 800162c:	eef0 6a42 	vmov.f32	s13, s4
 8001630:	eeb0 7a62 	vmov.f32	s14, s5
 8001634:	eef0 7a43 	vmov.f32	s15, s6
 8001638:	edc7 4a08 	vstr	s9, [r7, #32]
 800163c:	ed87 5a09 	vstr	s10, [r7, #36]	@ 0x24
 8001640:	edc7 5a0a 	vstr	s11, [r7, #40]	@ 0x28
 8001644:	ed87 6a0b 	vstr	s12, [r7, #44]	@ 0x2c
 8001648:	edc7 6a05 	vstr	s13, [r7, #20]
 800164c:	ed87 7a06 	vstr	s14, [r7, #24]
 8001650:	edc7 7a07 	vstr	s15, [r7, #28]
#define Q quaternion.element
#define V vector.axis
    const FusionQuaternion result = {.element = {
            .w = -Q.x * V.x - Q.y * V.y - Q.z * V.z,
 8001654:	edd7 7a09 	vldr	s15, [r7, #36]	@ 0x24
 8001658:	eeb1 7a67 	vneg.f32	s14, s15
 800165c:	edd7 7a05 	vldr	s15, [r7, #20]
 8001660:	ee27 7a27 	vmul.f32	s14, s14, s15
 8001664:	edd7 6a0a 	vldr	s13, [r7, #40]	@ 0x28
 8001668:	edd7 7a06 	vldr	s15, [r7, #24]
 800166c:	ee66 7aa7 	vmul.f32	s15, s13, s15
 8001670:	ee37 7a67 	vsub.f32	s14, s14, s15
 8001674:	edd7 6a0b 	vldr	s13, [r7, #44]	@ 0x2c
 8001678:	edd7 7a07 	vldr	s15, [r7, #28]
 800167c:	ee66 7aa7 	vmul.f32	s15, s13, s15
 8001680:	ee77 7a67 	vsub.f32	s15, s14, s15
    const FusionQuaternion result = {.element = {
 8001684:	edc7 7a0c 	vstr	s15, [r7, #48]	@ 0x30
            .x = Q.w * V.x + Q.y * V.z - Q.z * V.y,
 8001688:	ed97 7a08 	vldr	s14, [r7, #32]
 800168c:	edd7 7a05 	vldr	s15, [r7, #20]
 8001690:	ee27 7a27 	vmul.f32	s14, s14, s15
 8001694:	edd7 6a0a 	vldr	s13, [r7, #40]	@ 0x28
 8001698:	edd7 7a07 	vldr	s15, [r7, #28]
 800169c:	ee66 7aa7 	vmul.f32	s15, s13, s15
 80016a0:	ee37 7a27 	vadd.f32	s14, s14, s15
 80016a4:	edd7 6a0b 	vldr	s13, [r7, #44]	@ 0x2c
 80016a8:	edd7 7a06 	vldr	s15, [r7, #24]
 80016ac:	ee66 7aa7 	vmul.f32	s15, s13, s15
 80016b0:	ee77 7a67 	vsub.f32	s15, s14, s15
    const FusionQuaternion result = {.element = {
 80016b4:	edc7 7a0d 	vstr	s15, [r7, #52]	@ 0x34
            .y = Q.w * V.y - Q.x * V.z + Q.z * V.x,
 80016b8:	ed97 7a08 	vldr	s14, [r7, #32]
 80016bc:	edd7 7a06 	vldr	s15, [r7, #24]
 80016c0:	ee27 7a27 	vmul.f32	s14, s14, s15
 80016c4:	edd7 6a09 	vldr	s13, [r7, #36]	@ 0x24
 80016c8:	edd7 7a07 	vldr	s15, [r7, #28]
 80016cc:	ee66 7aa7 	vmul.f32	s15, s13, s15
 80016d0:	ee37 7a67 	vsub.f32	s14, s14, s15
 80016d4:	edd7 6a0b 	vldr	s13, [r7, #44]	@ 0x2c
 80016d8:	edd7 7a05 	vldr	s15, [r7, #20]
 80016dc:	ee66 7aa7 	vmul.f32	s15, s13, s15
 80016e0:	ee77 7a27 	vadd.f32	s15, s14, s15
    const FusionQuaternion result = {.element = {
 80016e4:	edc7 7a0e 	vstr	s15, [r7, #56]	@ 0x38
            .z = Q.w * V.z + Q.x * V.y - Q.y * V.x,
 80016e8:	ed97 7a08 	vldr	s14, [r7, #32]
 80016ec:	edd7 7a07 	vldr	s15, [r7, #28]
 80016f0:	ee27 7a27 	vmul.f32	s14, s14, s15
 80016f4:	edd7 6a09 	vldr	s13, [r7, #36]	@ 0x24
 80016f8:	edd7 7a06 	vldr	s15, [r7, #24]
 80016fc:	ee66 7aa7 	vmul.f32	s15, s13, s15
 8001700:	ee37 7a27 	vadd.f32	s14, s14, s15
 8001704:	edd7 6a0a 	vldr	s13, [r7, #40]	@ 0x28
 8001708:	edd7 7a05 	vldr	s15, [r7, #20]
 800170c:	ee66 7aa7 	vmul.f32	s15, s13, s15
 8001710:	ee77 7a67 	vsub.f32	s15, s14, s15
    const FusionQuaternion result = {.element = {
 8001714:	edc7 7a0f 	vstr	s15, [r7, #60]	@ 0x3c
    }};
    return result;
 8001718:	f107 0440 	add.w	r4, r7, #64	@ 0x40
 800171c:	f107 0330 	add.w	r3, r7, #48	@ 0x30
 8001720:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
 8001722:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
 8001726:	6c38      	ldr	r0, [r7, #64]	@ 0x40
 8001728:	6c79      	ldr	r1, [r7, #68]	@ 0x44
 800172a:	6cba      	ldr	r2, [r7, #72]	@ 0x48
 800172c:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 800172e:	ee06 0a10 	vmov	s12, r0
 8001732:	ee06 1a90 	vmov	s13, r1
 8001736:	ee07 2a10 	vmov	s14, r2
 800173a:	ee07 3a90 	vmov	s15, r3
#undef Q
#undef V
}
 800173e:	eeb0 0a46 	vmov.f32	s0, s12
 8001742:	eef0 0a66 	vmov.f32	s1, s13
 8001746:	eeb0 1a47 	vmov.f32	s2, s14
 800174a:	eef0 1a67 	vmov.f32	s3, s15
 800174e:	3750      	adds	r7, #80	@ 0x50
 8001750:	46bd      	mov	sp, r7
 8001752:	bc90      	pop	{r4, r7}
 8001754:	4770      	bx	lr

08001756 <FusionQuaternionNormalise>:
/**
 * @brief Returns the normalised quaternion.
 * @param quaternion Quaternion.
 * @return Normalised quaternion.
 */
static inline FusionQuaternion FusionQuaternionNormalise(const FusionQuaternion quaternion) {
 8001756:	b590      	push	{r4, r7, lr}
 8001758:	b093      	sub	sp, #76	@ 0x4c
 800175a:	af00      	add	r7, sp, #0
 800175c:	eeb0 6a40 	vmov.f32	s12, s0
 8001760:	eef0 6a60 	vmov.f32	s13, s1
 8001764:	eeb0 7a41 	vmov.f32	s14, s2
 8001768:	eef0 7a61 	vmov.f32	s15, s3
 800176c:	ed87 6a04 	vstr	s12, [r7, #16]
 8001770:	edc7 6a05 	vstr	s13, [r7, #20]
 8001774:	ed87 7a06 	vstr	s14, [r7, #24]
 8001778:	edc7 7a07 	vstr	s15, [r7, #28]
#define Q quaternion.element
#ifdef FUSION_USE_NORMAL_SQRT
    const float magnitudeReciprocal = 1.0f / sqrtf(Q.w * Q.w + Q.x * Q.x + Q.y * Q.y + Q.z * Q.z);
#else
    const float magnitudeReciprocal = FusionFastInverseSqrt(Q.w * Q.w + Q.x * Q.x + Q.y * Q.y + Q.z * Q.z);
 800177c:	ed97 7a04 	vldr	s14, [r7, #16]
 8001780:	edd7 7a04 	vldr	s15, [r7, #16]
 8001784:	ee27 7a27 	vmul.f32	s14, s14, s15
 8001788:	edd7 6a05 	vldr	s13, [r7, #20]
 800178c:	edd7 7a05 	vldr	s15, [r7, #20]
 8001790:	ee66 7aa7 	vmul.f32	s15, s13, s15
 8001794:	ee37 7a27 	vadd.f32	s14, s14, s15
 8001798:	edd7 6a06 	vldr	s13, [r7, #24]
 800179c:	edd7 7a06 	vldr	s15, [r7, #24]
 80017a0:	ee66 7aa7 	vmul.f32	s15, s13, s15
 80017a4:	ee37 7a27 	vadd.f32	s14, s14, s15
 80017a8:	edd7 6a07 	vldr	s13, [r7, #28]
 80017ac:	edd7 7a07 	vldr	s15, [r7, #28]
 80017b0:	ee66 7aa7 	vmul.f32	s15, s13, s15
 80017b4:	ee77 7a27 	vadd.f32	s15, s14, s15
 80017b8:	eeb0 0a67 	vmov.f32	s0, s15
 80017bc:	f7ff fbe6 	bl	8000f8c <FusionFastInverseSqrt>
 80017c0:	ed87 0a11 	vstr	s0, [r7, #68]	@ 0x44
#endif
    const FusionQuaternion result = {.element = {
            .w = Q.w * magnitudeReciprocal,
 80017c4:	ed97 7a04 	vldr	s14, [r7, #16]
 80017c8:	edd7 7a11 	vldr	s15, [r7, #68]	@ 0x44
 80017cc:	ee67 7a27 	vmul.f32	s15, s14, s15
    const FusionQuaternion result = {.element = {
 80017d0:	edc7 7a09 	vstr	s15, [r7, #36]	@ 0x24
            .x = Q.x * magnitudeReciprocal,
 80017d4:	ed97 7a05 	vldr	s14, [r7, #20]
 80017d8:	edd7 7a11 	vldr	s15, [r7, #68]	@ 0x44
 80017dc:	ee67 7a27 	vmul.f32	s15, s14, s15
    const FusionQuaternion result = {.element = {
 80017e0:	edc7 7a0a 	vstr	s15, [r7, #40]	@ 0x28
            .y = Q.y * magnitudeReciprocal,
 80017e4:	ed97 7a06 	vldr	s14, [r7, #24]
 80017e8:	edd7 7a11 	vldr	s15, [r7, #68]	@ 0x44
 80017ec:	ee67 7a27 	vmul.f32	s15, s14, s15
    const FusionQuaternion result = {.element = {
 80017f0:	edc7 7a0b 	vstr	s15, [r7, #44]	@ 0x2c
            .z = Q.z * magnitudeReciprocal,
 80017f4:	ed97 7a07 	vldr	s14, [r7, #28]
 80017f8:	edd7 7a11 	vldr	s15, [r7, #68]	@ 0x44
 80017fc:	ee67 7a27 	vmul.f32	s15, s14, s15
    const FusionQuaternion result = {.element = {
 8001800:	edc7 7a0c 	vstr	s15, [r7, #48]	@ 0x30
    }};
    return result;
 8001804:	f107 0434 	add.w	r4, r7, #52	@ 0x34
 8001808:	f107 0324 	add.w	r3, r7, #36	@ 0x24
 800180c:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
 800180e:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
 8001812:	6b78      	ldr	r0, [r7, #52]	@ 0x34
 8001814:	6bb9      	ldr	r1, [r7, #56]	@ 0x38
 8001816:	6bfa      	ldr	r2, [r7, #60]	@ 0x3c
 8001818:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
 800181a:	ee06 0a10 	vmov	s12, r0
 800181e:	ee06 1a90 	vmov	s13, r1
 8001822:	ee07 2a10 	vmov	s14, r2
 8001826:	ee07 3a90 	vmov	s15, r3
#undef Q
}
 800182a:	eeb0 0a46 	vmov.f32	s0, s12
 800182e:	eef0 0a66 	vmov.f32	s1, s13
 8001832:	eeb0 1a47 	vmov.f32	s2, s14
 8001836:	eef0 1a67 	vmov.f32	s3, s15
 800183a:	374c      	adds	r7, #76	@ 0x4c
 800183c:	46bd      	mov	sp, r7
 800183e:	bd90      	pop	{r4, r7, pc}

08001840 <FusionAhrsInitialise>:

/**
 * @brief Initialises the AHRS algorithm² structure.
 * @param ahrs AHRS algorithm structure.
 */
void FusionAhrsInitialise(FusionAhrs *const ahrs) {
 8001840:	b5b0      	push	{r4, r5, r7, lr}
 8001842:	b088      	sub	sp, #32
 8001844:	af00      	add	r7, sp, #0
 8001846:	6078      	str	r0, [r7, #4]
    const FusionAhrsSettings settings = {
 8001848:	4b0b      	ldr	r3, [pc, #44]	@ (8001878 <FusionAhrsInitialise+0x38>)
 800184a:	f107 0408 	add.w	r4, r7, #8
 800184e:	461d      	mov	r5, r3
 8001850:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
 8001852:	c40f      	stmia	r4!, {r0, r1, r2, r3}
 8001854:	e895 0003 	ldmia.w	r5, {r0, r1}
 8001858:	e884 0003 	stmia.w	r4, {r0, r1}
            .gyroscopeRange = 0.0f,
            .accelerationRejection = 90.0f,
            .magneticRejection = 90.0f,
            .recoveryTriggerPeriod = 0,
    };
    FusionAhrsSetSettings(ahrs, &settings);
 800185c:	f107 0308 	add.w	r3, r7, #8
 8001860:	4619      	mov	r1, r3
 8001862:	6878      	ldr	r0, [r7, #4]
 8001864:	f000 f86e 	bl	8001944 <FusionAhrsSetSettings>
    FusionAhrsReset(ahrs);
 8001868:	6878      	ldr	r0, [r7, #4]
 800186a:	f000 f807 	bl	800187c <FusionAhrsReset>
}
 800186e:	bf00      	nop
 8001870:	3720      	adds	r7, #32
 8001872:	46bd      	mov	sp, r7
 8001874:	bdb0      	pop	{r4, r5, r7, pc}
 8001876:	bf00      	nop
 8001878:	0800b730 	.word	0x0800b730

0800187c <FusionAhrsReset>:
/**
 * @brief Resets the AHRS algorithm. This is equivalent to reinitialising the
 * algorithm while maintaining the current settings.
 * @param ahrs AHRS algorithm structure.
 */
void FusionAhrsReset(FusionAhrs *const ahrs) {
 800187c:	b480      	push	{r7}
 800187e:	b091      	sub	sp, #68	@ 0x44
 8001880:	af00      	add	r7, sp, #0
 8001882:	6078      	str	r0, [r7, #4]
    ahrs->quaternion = FUSION_IDENTITY_QUATERNION;
 8001884:	687b      	ldr	r3, [r7, #4]
 8001886:	f04f 527e 	mov.w	r2, #1065353216	@ 0x3f800000
 800188a:	619a      	str	r2, [r3, #24]
 800188c:	687b      	ldr	r3, [r7, #4]
 800188e:	f04f 0200 	mov.w	r2, #0
 8001892:	61da      	str	r2, [r3, #28]
 8001894:	687b      	ldr	r3, [r7, #4]
 8001896:	f04f 0200 	mov.w	r2, #0
 800189a:	621a      	str	r2, [r3, #32]
 800189c:	687b      	ldr	r3, [r7, #4]
 800189e:	f04f 0200 	mov.w	r2, #0
 80018a2:	625a      	str	r2, [r3, #36]	@ 0x24
    ahrs->accelerometer = FUSION_VECTOR_ZERO;
 80018a4:	687b      	ldr	r3, [r7, #4]
 80018a6:	f04f 0200 	mov.w	r2, #0
 80018aa:	629a      	str	r2, [r3, #40]	@ 0x28
 80018ac:	687b      	ldr	r3, [r7, #4]
 80018ae:	f04f 0200 	mov.w	r2, #0
 80018b2:	62da      	str	r2, [r3, #44]	@ 0x2c
 80018b4:	687b      	ldr	r3, [r7, #4]
 80018b6:	f04f 0200 	mov.w	r2, #0
 80018ba:	631a      	str	r2, [r3, #48]	@ 0x30
    ahrs->initialising = true;
 80018bc:	687b      	ldr	r3, [r7, #4]
 80018be:	2201      	movs	r2, #1
 80018c0:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
    ahrs->rampedGain = INITIAL_GAIN;
 80018c4:	687b      	ldr	r3, [r7, #4]
 80018c6:	4a1e      	ldr	r2, [pc, #120]	@ (8001940 <FusionAhrsReset+0xc4>)
 80018c8:	639a      	str	r2, [r3, #56]	@ 0x38
    ahrs->angularRateRecovery = false;
 80018ca:	687b      	ldr	r3, [r7, #4]
 80018cc:	2200      	movs	r2, #0
 80018ce:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
    ahrs->halfAccelerometerFeedback = FUSION_VECTOR_ZERO;
 80018d2:	687b      	ldr	r3, [r7, #4]
 80018d4:	f04f 0200 	mov.w	r2, #0
 80018d8:	645a      	str	r2, [r3, #68]	@ 0x44
 80018da:	687b      	ldr	r3, [r7, #4]
 80018dc:	f04f 0200 	mov.w	r2, #0
 80018e0:	649a      	str	r2, [r3, #72]	@ 0x48
 80018e2:	687b      	ldr	r3, [r7, #4]
 80018e4:	f04f 0200 	mov.w	r2, #0
 80018e8:	64da      	str	r2, [r3, #76]	@ 0x4c
    ahrs->halfMagnetometerFeedback = FUSION_VECTOR_ZERO;
 80018ea:	687b      	ldr	r3, [r7, #4]
 80018ec:	f04f 0200 	mov.w	r2, #0
 80018f0:	651a      	str	r2, [r3, #80]	@ 0x50
 80018f2:	687b      	ldr	r3, [r7, #4]
 80018f4:	f04f 0200 	mov.w	r2, #0
 80018f8:	655a      	str	r2, [r3, #84]	@ 0x54
 80018fa:	687b      	ldr	r3, [r7, #4]
 80018fc:	f04f 0200 	mov.w	r2, #0
 8001900:	659a      	str	r2, [r3, #88]	@ 0x58
    ahrs->accelerometerIgnored = false;
 8001902:	687b      	ldr	r3, [r7, #4]
 8001904:	2200      	movs	r2, #0
 8001906:	f883 205c 	strb.w	r2, [r3, #92]	@ 0x5c
    ahrs->accelerationRecoveryTrigger = 0;
 800190a:	687b      	ldr	r3, [r7, #4]
 800190c:	2200      	movs	r2, #0
 800190e:	661a      	str	r2, [r3, #96]	@ 0x60
    ahrs->accelerationRecoveryTimeout = ahrs->settings.recoveryTriggerPeriod;
 8001910:	687b      	ldr	r3, [r7, #4]
 8001912:	695b      	ldr	r3, [r3, #20]
 8001914:	461a      	mov	r2, r3
 8001916:	687b      	ldr	r3, [r7, #4]
 8001918:	665a      	str	r2, [r3, #100]	@ 0x64
    ahrs->magnetometerIgnored = false;
 800191a:	687b      	ldr	r3, [r7, #4]
 800191c:	2200      	movs	r2, #0
 800191e:	f883 2068 	strb.w	r2, [r3, #104]	@ 0x68
    ahrs->magneticRecoveryTrigger = 0;
 8001922:	687b      	ldr	r3, [r7, #4]
 8001924:	2200      	movs	r2, #0
 8001926:	66da      	str	r2, [r3, #108]	@ 0x6c
    ahrs->magneticRecoveryTimeout = ahrs->settings.recoveryTriggerPeriod;
 8001928:	687b      	ldr	r3, [r7, #4]
 800192a:	695b      	ldr	r3, [r3, #20]
 800192c:	461a      	mov	r2, r3
 800192e:	687b      	ldr	r3, [r7, #4]
 8001930:	671a      	str	r2, [r3, #112]	@ 0x70
}
 8001932:	bf00      	nop
 8001934:	3744      	adds	r7, #68	@ 0x44
 8001936:	46bd      	mov	sp, r7
 8001938:	f85d 7b04 	ldr.w	r7, [sp], #4
 800193c:	4770      	bx	lr
 800193e:	bf00      	nop
 8001940:	41200000 	.word	0x41200000

08001944 <FusionAhrsSetSettings>:
/**
 * @brief Sets the AHRS algorithm settings.
 * @param ahrs AHRS algorithm structure.
 * @param settings Settings.
 */
void FusionAhrsSetSettings(FusionAhrs *const ahrs, const FusionAhrsSettings *const settings) {
 8001944:	b580      	push	{r7, lr}
 8001946:	b082      	sub	sp, #8
 8001948:	af00      	add	r7, sp, #0
 800194a:	6078      	str	r0, [r7, #4]
 800194c:	6039      	str	r1, [r7, #0]
    ahrs->settings.convention = settings->convention;
 800194e:	683b      	ldr	r3, [r7, #0]
 8001950:	781a      	ldrb	r2, [r3, #0]
 8001952:	687b      	ldr	r3, [r7, #4]
 8001954:	701a      	strb	r2, [r3, #0]
    ahrs->settings.gain = settings->gain;
 8001956:	683b      	ldr	r3, [r7, #0]
 8001958:	685a      	ldr	r2, [r3, #4]
 800195a:	687b      	ldr	r3, [r7, #4]
 800195c:	605a      	str	r2, [r3, #4]
    ahrs->settings.gyroscopeRange = settings->gyroscopeRange == 0.0f ? FLT_MAX : 0.98f * settings->gyroscopeRange;
 800195e:	683b      	ldr	r3, [r7, #0]
 8001960:	edd3 7a02 	vldr	s15, [r3, #8]
 8001964:	eef5 7a40 	vcmp.f32	s15, #0.0
 8001968:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800196c:	d007      	beq.n	800197e <FusionAhrsSetSettings+0x3a>
 800196e:	683b      	ldr	r3, [r7, #0]
 8001970:	edd3 7a02 	vldr	s15, [r3, #8]
 8001974:	ed9f 7a4c 	vldr	s14, [pc, #304]	@ 8001aa8 <FusionAhrsSetSettings+0x164>
 8001978:	ee67 7a87 	vmul.f32	s15, s15, s14
 800197c:	e001      	b.n	8001982 <FusionAhrsSetSettings+0x3e>
 800197e:	eddf 7a4b 	vldr	s15, [pc, #300]	@ 8001aac <FusionAhrsSetSettings+0x168>
 8001982:	687b      	ldr	r3, [r7, #4]
 8001984:	edc3 7a02 	vstr	s15, [r3, #8]
    ahrs->settings.accelerationRejection = settings->accelerationRejection == 0.0f ? FLT_MAX : powf(0.5f * sinf(FusionDegreesToRadians(settings->accelerationRejection)), 2);
 8001988:	683b      	ldr	r3, [r7, #0]
 800198a:	edd3 7a03 	vldr	s15, [r3, #12]
 800198e:	eef5 7a40 	vcmp.f32	s15, #0.0
 8001992:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8001996:	d01b      	beq.n	80019d0 <FusionAhrsSetSettings+0x8c>
 8001998:	683b      	ldr	r3, [r7, #0]
 800199a:	edd3 7a03 	vldr	s15, [r3, #12]
 800199e:	eeb0 0a67 	vmov.f32	s0, s15
 80019a2:	f7ff fa9f 	bl	8000ee4 <FusionDegreesToRadians>
 80019a6:	eef0 7a40 	vmov.f32	s15, s0
 80019aa:	eeb0 0a67 	vmov.f32	s0, s15
 80019ae:	f008 fc29 	bl	800a204 <sinf>
 80019b2:	eef0 7a40 	vmov.f32	s15, s0
 80019b6:	eeb6 7a00 	vmov.f32	s14, #96	@ 0x3f000000  0.5
 80019ba:	ee67 7a87 	vmul.f32	s15, s15, s14
 80019be:	eef0 0a00 	vmov.f32	s1, #0	@ 0x40000000  2.0
 80019c2:	eeb0 0a67 	vmov.f32	s0, s15
 80019c6:	f008 fb9f 	bl	800a108 <powf>
 80019ca:	eef0 7a40 	vmov.f32	s15, s0
 80019ce:	e001      	b.n	80019d4 <FusionAhrsSetSettings+0x90>
 80019d0:	eddf 7a36 	vldr	s15, [pc, #216]	@ 8001aac <FusionAhrsSetSettings+0x168>
 80019d4:	687b      	ldr	r3, [r7, #4]
 80019d6:	edc3 7a03 	vstr	s15, [r3, #12]
    ahrs->settings.magneticRejection = settings->magneticRejection == 0.0f ? FLT_MAX : powf(0.5f * sinf(FusionDegreesToRadians(settings->magneticRejection)), 2);
 80019da:	683b      	ldr	r3, [r7, #0]
 80019dc:	edd3 7a04 	vldr	s15, [r3, #16]
 80019e0:	eef5 7a40 	vcmp.f32	s15, #0.0
 80019e4:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 80019e8:	d01b      	beq.n	8001a22 <FusionAhrsSetSettings+0xde>
 80019ea:	683b      	ldr	r3, [r7, #0]
 80019ec:	edd3 7a04 	vldr	s15, [r3, #16]
 80019f0:	eeb0 0a67 	vmov.f32	s0, s15
 80019f4:	f7ff fa76 	bl	8000ee4 <FusionDegreesToRadians>
 80019f8:	eef0 7a40 	vmov.f32	s15, s0
 80019fc:	eeb0 0a67 	vmov.f32	s0, s15
 8001a00:	f008 fc00 	bl	800a204 <sinf>
 8001a04:	eef0 7a40 	vmov.f32	s15, s0
 8001a08:	eeb6 7a00 	vmov.f32	s14, #96	@ 0x3f000000  0.5
 8001a0c:	ee67 7a87 	vmul.f32	s15, s15, s14
 8001a10:	eef0 0a00 	vmov.f32	s1, #0	@ 0x40000000  2.0
 8001a14:	eeb0 0a67 	vmov.f32	s0, s15
 8001a18:	f008 fb76 	bl	800a108 <powf>
 8001a1c:	eef0 7a40 	vmov.f32	s15, s0
 8001a20:	e001      	b.n	8001a26 <FusionAhrsSetSettings+0xe2>
 8001a22:	eddf 7a22 	vldr	s15, [pc, #136]	@ 8001aac <FusionAhrsSetSettings+0x168>
 8001a26:	687b      	ldr	r3, [r7, #4]
 8001a28:	edc3 7a04 	vstr	s15, [r3, #16]
    ahrs->settings.recoveryTriggerPeriod = settings->recoveryTriggerPeriod;
 8001a2c:	683b      	ldr	r3, [r7, #0]
 8001a2e:	695a      	ldr	r2, [r3, #20]
 8001a30:	687b      	ldr	r3, [r7, #4]
 8001a32:	615a      	str	r2, [r3, #20]
    ahrs->accelerationRecoveryTimeout = ahrs->settings.recoveryTriggerPeriod;
 8001a34:	687b      	ldr	r3, [r7, #4]
 8001a36:	695b      	ldr	r3, [r3, #20]
 8001a38:	461a      	mov	r2, r3
 8001a3a:	687b      	ldr	r3, [r7, #4]
 8001a3c:	665a      	str	r2, [r3, #100]	@ 0x64
    ahrs->magneticRecoveryTimeout = ahrs->settings.recoveryTriggerPeriod;
 8001a3e:	687b      	ldr	r3, [r7, #4]
 8001a40:	695b      	ldr	r3, [r3, #20]
 8001a42:	461a      	mov	r2, r3
 8001a44:	687b      	ldr	r3, [r7, #4]
 8001a46:	671a      	str	r2, [r3, #112]	@ 0x70
    if ((settings->gain == 0.0f) || (settings->recoveryTriggerPeriod == 0)) { // disable acceleration and magnetic rejection features if gain is zero
 8001a48:	683b      	ldr	r3, [r7, #0]
 8001a4a:	edd3 7a01 	vldr	s15, [r3, #4]
 8001a4e:	eef5 7a40 	vcmp.f32	s15, #0.0
 8001a52:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8001a56:	d003      	beq.n	8001a60 <FusionAhrsSetSettings+0x11c>
 8001a58:	683b      	ldr	r3, [r7, #0]
 8001a5a:	695b      	ldr	r3, [r3, #20]
 8001a5c:	2b00      	cmp	r3, #0
 8001a5e:	d105      	bne.n	8001a6c <FusionAhrsSetSettings+0x128>
        ahrs->settings.accelerationRejection = FLT_MAX;
 8001a60:	687b      	ldr	r3, [r7, #4]
 8001a62:	4a13      	ldr	r2, [pc, #76]	@ (8001ab0 <FusionAhrsSetSettings+0x16c>)
 8001a64:	60da      	str	r2, [r3, #12]
        ahrs->settings.magneticRejection = FLT_MAX;
 8001a66:	687b      	ldr	r3, [r7, #4]
 8001a68:	4a11      	ldr	r2, [pc, #68]	@ (8001ab0 <FusionAhrsSetSettings+0x16c>)
 8001a6a:	611a      	str	r2, [r3, #16]
    }
    if (ahrs->initialising == false) {
 8001a6c:	687b      	ldr	r3, [r7, #4]
 8001a6e:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
 8001a72:	f083 0301 	eor.w	r3, r3, #1
 8001a76:	b2db      	uxtb	r3, r3
 8001a78:	2b00      	cmp	r3, #0
 8001a7a:	d003      	beq.n	8001a84 <FusionAhrsSetSettings+0x140>
        ahrs->rampedGain = ahrs->settings.gain;
 8001a7c:	687b      	ldr	r3, [r7, #4]
 8001a7e:	685a      	ldr	r2, [r3, #4]
 8001a80:	687b      	ldr	r3, [r7, #4]
 8001a82:	639a      	str	r2, [r3, #56]	@ 0x38
    }
    ahrs->rampedGainStep = (INITIAL_GAIN - ahrs->settings.gain) / INITIALISATION_PERIOD;
 8001a84:	687b      	ldr	r3, [r7, #4]
 8001a86:	edd3 7a01 	vldr	s15, [r3, #4]
 8001a8a:	eeb2 7a04 	vmov.f32	s14, #36	@ 0x41200000  10.0
 8001a8e:	ee37 7a67 	vsub.f32	s14, s14, s15
 8001a92:	eef0 6a08 	vmov.f32	s13, #8	@ 0x40400000  3.0
 8001a96:	eec7 7a26 	vdiv.f32	s15, s14, s13
 8001a9a:	687b      	ldr	r3, [r7, #4]
 8001a9c:	edc3 7a0f 	vstr	s15, [r3, #60]	@ 0x3c
}
 8001aa0:	bf00      	nop
 8001aa2:	3708      	adds	r7, #8
 8001aa4:	46bd      	mov	sp, r7
 8001aa6:	bd80      	pop	{r7, pc}
 8001aa8:	3f7ae148 	.word	0x3f7ae148
 8001aac:	7f7fffff 	.word	0x7f7fffff
 8001ab0:	7f7fffff 	.word	0x7f7fffff

08001ab4 <FusionAhrsUpdate>:
 * @param gyroscope Gyroscope measurement in degrees per second.
 * @param accelerometer Accelerometer measurement in g.
 * @param magnetometer Magnetometer measurement in arbitrary units.
 * @param deltaTime Delta time in seconds.
 */
void FusionAhrsUpdate(FusionAhrs *const ahrs, const FusionVector gyroscope, const FusionVector accelerometer, const FusionVector magnetometer, const float deltaTime) {
 8001ab4:	b590      	push	{r4, r7, lr}
 8001ab6:	b0bf      	sub	sp, #252	@ 0xfc
 8001ab8:	af00      	add	r7, sp, #0
 8001aba:	62f8      	str	r0, [r7, #44]	@ 0x2c
 8001abc:	eeb0 5a61 	vmov.f32	s10, s3
 8001ac0:	eef0 5a42 	vmov.f32	s11, s4
 8001ac4:	eeb0 6a62 	vmov.f32	s12, s5
 8001ac8:	eef0 6a43 	vmov.f32	s13, s6
 8001acc:	eeb0 7a63 	vmov.f32	s14, s7
 8001ad0:	eef0 7a44 	vmov.f32	s15, s8
 8001ad4:	edc7 4a01 	vstr	s9, [r7, #4]
 8001ad8:	ed87 0a08 	vstr	s0, [r7, #32]
 8001adc:	edc7 0a09 	vstr	s1, [r7, #36]	@ 0x24
 8001ae0:	ed87 1a0a 	vstr	s2, [r7, #40]	@ 0x28
 8001ae4:	ed87 5a05 	vstr	s10, [r7, #20]
 8001ae8:	edc7 5a06 	vstr	s11, [r7, #24]
 8001aec:	ed87 6a07 	vstr	s12, [r7, #28]
 8001af0:	edc7 6a02 	vstr	s13, [r7, #8]
 8001af4:	ed87 7a03 	vstr	s14, [r7, #12]
 8001af8:	edc7 7a04 	vstr	s15, [r7, #16]
#define Q ahrs->quaternion.element

    // Store accelerometer
    ahrs->accelerometer = accelerometer;
 8001afc:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001afe:	3328      	adds	r3, #40	@ 0x28
 8001b00:	f107 0214 	add.w	r2, r7, #20
 8001b04:	ca07      	ldmia	r2, {r0, r1, r2}
 8001b06:	e883 0007 	stmia.w	r3, {r0, r1, r2}

    // Reinitialise if gyroscope range exceeded
    if ((fabsf(gyroscope.axis.x) > ahrs->settings.gyroscopeRange) || (fabsf(gyroscope.axis.y) > ahrs->settings.gyroscopeRange) || (fabsf(gyroscope.axis.z) > ahrs->settings.gyroscopeRange)) {
 8001b0a:	edd7 7a08 	vldr	s15, [r7, #32]
 8001b0e:	eeb0 7ae7 	vabs.f32	s14, s15
 8001b12:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001b14:	edd3 7a02 	vldr	s15, [r3, #8]
 8001b18:	eeb4 7ae7 	vcmpe.f32	s14, s15
 8001b1c:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8001b20:	dc17      	bgt.n	8001b52 <FusionAhrsUpdate+0x9e>
 8001b22:	edd7 7a09 	vldr	s15, [r7, #36]	@ 0x24
 8001b26:	eeb0 7ae7 	vabs.f32	s14, s15
 8001b2a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001b2c:	edd3 7a02 	vldr	s15, [r3, #8]
 8001b30:	eeb4 7ae7 	vcmpe.f32	s14, s15
 8001b34:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8001b38:	dc0b      	bgt.n	8001b52 <FusionAhrsUpdate+0x9e>
 8001b3a:	edd7 7a0a 	vldr	s15, [r7, #40]	@ 0x28
 8001b3e:	eeb0 7ae7 	vabs.f32	s14, s15
 8001b42:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001b44:	edd3 7a02 	vldr	s15, [r3, #8]
 8001b48:	eeb4 7ae7 	vcmpe.f32	s14, s15
 8001b4c:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8001b50:	dd15      	ble.n	8001b7e <FusionAhrsUpdate+0xca>
        const FusionQuaternion quaternion = ahrs->quaternion;
 8001b52:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001b54:	f107 043c 	add.w	r4, r7, #60	@ 0x3c
 8001b58:	3318      	adds	r3, #24
 8001b5a:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
 8001b5c:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
        FusionAhrsReset(ahrs);
 8001b60:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8001b62:	f7ff fe8b 	bl	800187c <FusionAhrsReset>
        ahrs->quaternion = quaternion;
 8001b66:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001b68:	f103 0418 	add.w	r4, r3, #24
 8001b6c:	f107 033c 	add.w	r3, r7, #60	@ 0x3c
 8001b70:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
 8001b72:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
        ahrs->angularRateRecovery = true;
 8001b76:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001b78:	2201      	movs	r2, #1
 8001b7a:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
    }

    // Ramp down gain during initialisation
    if (ahrs->initialising) {
 8001b7e:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001b80:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
 8001b84:	2b00      	cmp	r3, #0
 8001b86:	d02d      	beq.n	8001be4 <FusionAhrsUpdate+0x130>
        ahrs->rampedGain -= ahrs->rampedGainStep * deltaTime;
 8001b88:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001b8a:	ed93 7a0e 	vldr	s14, [r3, #56]	@ 0x38
 8001b8e:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001b90:	edd3 6a0f 	vldr	s13, [r3, #60]	@ 0x3c
 8001b94:	edd7 7a01 	vldr	s15, [r7, #4]
 8001b98:	ee66 7aa7 	vmul.f32	s15, s13, s15
 8001b9c:	ee77 7a67 	vsub.f32	s15, s14, s15
 8001ba0:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001ba2:	edc3 7a0e 	vstr	s15, [r3, #56]	@ 0x38
        if ((ahrs->rampedGain < ahrs->settings.gain) || (ahrs->settings.gain == 0.0f)) {
 8001ba6:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001ba8:	ed93 7a0e 	vldr	s14, [r3, #56]	@ 0x38
 8001bac:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001bae:	edd3 7a01 	vldr	s15, [r3, #4]
 8001bb2:	eeb4 7ae7 	vcmpe.f32	s14, s15
 8001bb6:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8001bba:	d407      	bmi.n	8001bcc <FusionAhrsUpdate+0x118>
 8001bbc:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001bbe:	edd3 7a01 	vldr	s15, [r3, #4]
 8001bc2:	eef5 7a40 	vcmp.f32	s15, #0.0
 8001bc6:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8001bca:	d10b      	bne.n	8001be4 <FusionAhrsUpdate+0x130>
            ahrs->rampedGain = ahrs->settings.gain;
 8001bcc:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001bce:	685a      	ldr	r2, [r3, #4]
 8001bd0:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001bd2:	639a      	str	r2, [r3, #56]	@ 0x38
            ahrs->initialising = false;
 8001bd4:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001bd6:	2200      	movs	r2, #0
 8001bd8:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
            ahrs->angularRateRecovery = false;
 8001bdc:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001bde:	2200      	movs	r2, #0
 8001be0:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
        }
    }

    // Calculate direction of gravity indicated by algorithm
    const FusionVector halfGravity = HalfGravity(ahrs);
 8001be4:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8001be6:	f000 faf4 	bl	80021d2 <HalfGravity>
 8001bea:	eef0 6a40 	vmov.f32	s13, s0
 8001bee:	eeb0 7a60 	vmov.f32	s14, s1
 8001bf2:	eef0 7a41 	vmov.f32	s15, s2
 8001bf6:	edc7 6a25 	vstr	s13, [r7, #148]	@ 0x94
 8001bfa:	ed87 7a26 	vstr	s14, [r7, #152]	@ 0x98
 8001bfe:	edc7 7a27 	vstr	s15, [r7, #156]	@ 0x9c

    // Calculate accelerometer feedback
    FusionVector halfAccelerometerFeedback = FUSION_VECTOR_ZERO;
 8001c02:	f04f 0300 	mov.w	r3, #0
 8001c06:	f8c7 3088 	str.w	r3, [r7, #136]	@ 0x88
 8001c0a:	f04f 0300 	mov.w	r3, #0
 8001c0e:	f8c7 308c 	str.w	r3, [r7, #140]	@ 0x8c
 8001c12:	f04f 0300 	mov.w	r3, #0
 8001c16:	f8c7 3090 	str.w	r3, [r7, #144]	@ 0x90
    ahrs->accelerometerIgnored = true;
 8001c1a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001c1c:	2201      	movs	r2, #1
 8001c1e:	f883 205c 	strb.w	r2, [r3, #92]	@ 0x5c
    if (FusionVectorIsZero(accelerometer) == false) {
 8001c22:	edd7 6a05 	vldr	s13, [r7, #20]
 8001c26:	ed97 7a06 	vldr	s14, [r7, #24]
 8001c2a:	edd7 7a07 	vldr	s15, [r7, #28]
 8001c2e:	eeb0 0a66 	vmov.f32	s0, s13
 8001c32:	eef0 0a47 	vmov.f32	s1, s14
 8001c36:	eeb0 1a67 	vmov.f32	s2, s15
 8001c3a:	f7ff f9d7 	bl	8000fec <FusionVectorIsZero>
 8001c3e:	4603      	mov	r3, r0
 8001c40:	f083 0301 	eor.w	r3, r3, #1
 8001c44:	b2db      	uxtb	r3, r3
 8001c46:	2b00      	cmp	r3, #0
 8001c48:	f000 809c 	beq.w	8001d84 <FusionAhrsUpdate+0x2d0>

        // Calculate accelerometer feedback scaled by 0.5
        ahrs->halfAccelerometerFeedback = Feedback(FusionVectorNormalise(accelerometer), halfGravity);
 8001c4c:	edd7 6a05 	vldr	s13, [r7, #20]
 8001c50:	ed97 7a06 	vldr	s14, [r7, #24]
 8001c54:	edd7 7a07 	vldr	s15, [r7, #28]
 8001c58:	eeb0 0a66 	vmov.f32	s0, s13
 8001c5c:	eef0 0a47 	vmov.f32	s1, s14
 8001c60:	eeb0 1a67 	vmov.f32	s2, s15
 8001c64:	f7ff fc22 	bl	80014ac <FusionVectorNormalise>
 8001c68:	eef0 6a40 	vmov.f32	s13, s0
 8001c6c:	eeb0 7a60 	vmov.f32	s14, s1
 8001c70:	eef0 7a41 	vmov.f32	s15, s2
 8001c74:	edc7 6a28 	vstr	s13, [r7, #160]	@ 0xa0
 8001c78:	ed87 7a29 	vstr	s14, [r7, #164]	@ 0xa4
 8001c7c:	edc7 7a2a 	vstr	s15, [r7, #168]	@ 0xa8
 8001c80:	6afc      	ldr	r4, [r7, #44]	@ 0x2c
 8001c82:	ed97 5a25 	vldr	s10, [r7, #148]	@ 0x94
 8001c86:	edd7 5a26 	vldr	s11, [r7, #152]	@ 0x98
 8001c8a:	ed97 6a27 	vldr	s12, [r7, #156]	@ 0x9c
 8001c8e:	edd7 6a28 	vldr	s13, [r7, #160]	@ 0xa0
 8001c92:	ed97 7a29 	vldr	s14, [r7, #164]	@ 0xa4
 8001c96:	edd7 7a2a 	vldr	s15, [r7, #168]	@ 0xa8
 8001c9a:	eef0 1a45 	vmov.f32	s3, s10
 8001c9e:	eeb0 2a65 	vmov.f32	s4, s11
 8001ca2:	eef0 2a46 	vmov.f32	s5, s12
 8001ca6:	eeb0 0a66 	vmov.f32	s0, s13
 8001caa:	eef0 0a47 	vmov.f32	s1, s14
 8001cae:	eeb0 1a67 	vmov.f32	s2, s15
 8001cb2:	f000 fc55 	bl	8002560 <Feedback>
 8001cb6:	eef0 6a40 	vmov.f32	s13, s0
 8001cba:	eeb0 7a60 	vmov.f32	s14, s1
 8001cbe:	eef0 7a41 	vmov.f32	s15, s2
 8001cc2:	edc4 6a11 	vstr	s13, [r4, #68]	@ 0x44
 8001cc6:	ed84 7a12 	vstr	s14, [r4, #72]	@ 0x48
 8001cca:	edc4 7a13 	vstr	s15, [r4, #76]	@ 0x4c

        // Don't ignore accelerometer if acceleration error below threshold
        if (ahrs->initialising || ((FusionVectorMagnitudeSquared(ahrs->halfAccelerometerFeedback) <= ahrs->settings.accelerationRejection))) {
 8001cce:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001cd0:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
 8001cd4:	2b00      	cmp	r3, #0
 8001cd6:	d118      	bne.n	8001d0a <FusionAhrsUpdate+0x256>
 8001cd8:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001cda:	edd3 6a11 	vldr	s13, [r3, #68]	@ 0x44
 8001cde:	ed93 7a12 	vldr	s14, [r3, #72]	@ 0x48
 8001ce2:	edd3 7a13 	vldr	s15, [r3, #76]	@ 0x4c
 8001ce6:	eeb0 0a66 	vmov.f32	s0, s13
 8001cea:	eef0 0a47 	vmov.f32	s1, s14
 8001cee:	eeb0 1a67 	vmov.f32	s2, s15
 8001cf2:	f7ff fb67 	bl	80013c4 <FusionVectorMagnitudeSquared>
 8001cf6:	eeb0 7a40 	vmov.f32	s14, s0
 8001cfa:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001cfc:	edd3 7a03 	vldr	s15, [r3, #12]
 8001d00:	eeb4 7ae7 	vcmpe.f32	s14, s15
 8001d04:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8001d08:	d80a      	bhi.n	8001d20 <FusionAhrsUpdate+0x26c>
            ahrs->accelerometerIgnored = false;
 8001d0a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001d0c:	2200      	movs	r2, #0
 8001d0e:	f883 205c 	strb.w	r2, [r3, #92]	@ 0x5c
            ahrs->accelerationRecoveryTrigger -= 9;
 8001d12:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001d14:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8001d16:	f1a3 0209 	sub.w	r2, r3, #9
 8001d1a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001d1c:	661a      	str	r2, [r3, #96]	@ 0x60
 8001d1e:	e004      	b.n	8001d2a <FusionAhrsUpdate+0x276>
        } else {
            ahrs->accelerationRecoveryTrigger += 1;
 8001d20:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001d22:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8001d24:	1c5a      	adds	r2, r3, #1
 8001d26:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001d28:	661a      	str	r2, [r3, #96]	@ 0x60
        }

        // Don't ignore accelerometer during acceleration recovery
        if (ahrs->accelerationRecoveryTrigger > ahrs->accelerationRecoveryTimeout) {
 8001d2a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001d2c:	6e1a      	ldr	r2, [r3, #96]	@ 0x60
 8001d2e:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001d30:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 8001d32:	429a      	cmp	r2, r3
 8001d34:	dd07      	ble.n	8001d46 <FusionAhrsUpdate+0x292>
            ahrs->accelerationRecoveryTimeout = 0;
 8001d36:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001d38:	2200      	movs	r2, #0
 8001d3a:	665a      	str	r2, [r3, #100]	@ 0x64
            ahrs->accelerometerIgnored = false;
 8001d3c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001d3e:	2200      	movs	r2, #0
 8001d40:	f883 205c 	strb.w	r2, [r3, #92]	@ 0x5c
 8001d44:	e004      	b.n	8001d50 <FusionAhrsUpdate+0x29c>
        } else {
            ahrs->accelerationRecoveryTimeout = ahrs->settings.recoveryTriggerPeriod;
 8001d46:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001d48:	695b      	ldr	r3, [r3, #20]
 8001d4a:	461a      	mov	r2, r3
 8001d4c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001d4e:	665a      	str	r2, [r3, #100]	@ 0x64
        }
        ahrs->accelerationRecoveryTrigger = Clamp(ahrs->accelerationRecoveryTrigger, 0, ahrs->settings.recoveryTriggerPeriod);
 8001d50:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001d52:	6e18      	ldr	r0, [r3, #96]	@ 0x60
 8001d54:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001d56:	695b      	ldr	r3, [r3, #20]
 8001d58:	461a      	mov	r2, r3
 8001d5a:	2100      	movs	r1, #0
 8001d5c:	f000 fcb5 	bl	80026ca <Clamp>
 8001d60:	4602      	mov	r2, r0
 8001d62:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001d64:	661a      	str	r2, [r3, #96]	@ 0x60

        // Apply accelerometer feedback
        if (ahrs->accelerometerIgnored == false) {
 8001d66:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001d68:	f893 305c 	ldrb.w	r3, [r3, #92]	@ 0x5c
 8001d6c:	f083 0301 	eor.w	r3, r3, #1
 8001d70:	b2db      	uxtb	r3, r3
 8001d72:	2b00      	cmp	r3, #0
 8001d74:	d006      	beq.n	8001d84 <FusionAhrsUpdate+0x2d0>
            halfAccelerometerFeedback = ahrs->halfAccelerometerFeedback;
 8001d76:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 8001d78:	f107 0388 	add.w	r3, r7, #136	@ 0x88
 8001d7c:	3244      	adds	r2, #68	@ 0x44
 8001d7e:	ca07      	ldmia	r2, {r0, r1, r2}
 8001d80:	e883 0007 	stmia.w	r3, {r0, r1, r2}
        }
    }

    // Calculate magnetometer feedback
    FusionVector halfMagnetometerFeedback = FUSION_VECTOR_ZERO;
 8001d84:	f04f 0300 	mov.w	r3, #0
 8001d88:	673b      	str	r3, [r7, #112]	@ 0x70
 8001d8a:	f04f 0300 	mov.w	r3, #0
 8001d8e:	677b      	str	r3, [r7, #116]	@ 0x74
 8001d90:	f04f 0300 	mov.w	r3, #0
 8001d94:	67bb      	str	r3, [r7, #120]	@ 0x78
    ahrs->magnetometerIgnored = true;
 8001d96:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001d98:	2201      	movs	r2, #1
 8001d9a:	f883 2068 	strb.w	r2, [r3, #104]	@ 0x68
    if (FusionVectorIsZero(magnetometer) == false) {
 8001d9e:	edd7 6a02 	vldr	s13, [r7, #8]
 8001da2:	ed97 7a03 	vldr	s14, [r7, #12]
 8001da6:	edd7 7a04 	vldr	s15, [r7, #16]
 8001daa:	eeb0 0a66 	vmov.f32	s0, s13
 8001dae:	eef0 0a47 	vmov.f32	s1, s14
 8001db2:	eeb0 1a67 	vmov.f32	s2, s15
 8001db6:	f7ff f919 	bl	8000fec <FusionVectorIsZero>
 8001dba:	4603      	mov	r3, r0
 8001dbc:	f083 0301 	eor.w	r3, r3, #1
 8001dc0:	b2db      	uxtb	r3, r3
 8001dc2:	2b00      	cmp	r3, #0
 8001dc4:	f000 80d1 	beq.w	8001f6a <FusionAhrsUpdate+0x4b6>

        // Calculate direction of magnetic field indicated by algorithm
        const FusionVector halfMagnetic = HalfMagnetic(ahrs);
 8001dc8:	6af8      	ldr	r0, [r7, #44]	@ 0x2c
 8001dca:	f000 fabf 	bl	800234c <HalfMagnetic>
 8001dce:	eef0 6a40 	vmov.f32	s13, s0
 8001dd2:	eeb0 7a60 	vmov.f32	s14, s1
 8001dd6:	eef0 7a41 	vmov.f32	s15, s2
 8001dda:	edc7 6a0c 	vstr	s13, [r7, #48]	@ 0x30
 8001dde:	ed87 7a0d 	vstr	s14, [r7, #52]	@ 0x34
 8001de2:	edc7 7a0e 	vstr	s15, [r7, #56]	@ 0x38

        // Calculate magnetometer feedback scaled by 0.5
        ahrs->halfMagnetometerFeedback = Feedback(FusionVectorNormalise(FusionVectorCrossProduct(halfGravity, magnetometer)), halfMagnetic);
 8001de6:	ed97 5a02 	vldr	s10, [r7, #8]
 8001dea:	edd7 5a03 	vldr	s11, [r7, #12]
 8001dee:	ed97 6a04 	vldr	s12, [r7, #16]
 8001df2:	edd7 6a25 	vldr	s13, [r7, #148]	@ 0x94
 8001df6:	ed97 7a26 	vldr	s14, [r7, #152]	@ 0x98
 8001dfa:	edd7 7a27 	vldr	s15, [r7, #156]	@ 0x9c
 8001dfe:	eef0 1a45 	vmov.f32	s3, s10
 8001e02:	eeb0 2a65 	vmov.f32	s4, s11
 8001e06:	eef0 2a46 	vmov.f32	s5, s12
 8001e0a:	eeb0 0a66 	vmov.f32	s0, s13
 8001e0e:	eef0 0a47 	vmov.f32	s1, s14
 8001e12:	eeb0 1a67 	vmov.f32	s2, s15
 8001e16:	f7ff fa19 	bl	800124c <FusionVectorCrossProduct>
 8001e1a:	eef0 6a40 	vmov.f32	s13, s0
 8001e1e:	eeb0 7a60 	vmov.f32	s14, s1
 8001e22:	eef0 7a41 	vmov.f32	s15, s2
 8001e26:	edc7 6a2b 	vstr	s13, [r7, #172]	@ 0xac
 8001e2a:	ed87 7a2c 	vstr	s14, [r7, #176]	@ 0xb0
 8001e2e:	edc7 7a2d 	vstr	s15, [r7, #180]	@ 0xb4
 8001e32:	edd7 6a2b 	vldr	s13, [r7, #172]	@ 0xac
 8001e36:	ed97 7a2c 	vldr	s14, [r7, #176]	@ 0xb0
 8001e3a:	edd7 7a2d 	vldr	s15, [r7, #180]	@ 0xb4
 8001e3e:	eeb0 0a66 	vmov.f32	s0, s13
 8001e42:	eef0 0a47 	vmov.f32	s1, s14
 8001e46:	eeb0 1a67 	vmov.f32	s2, s15
 8001e4a:	f7ff fb2f 	bl	80014ac <FusionVectorNormalise>
 8001e4e:	eef0 6a40 	vmov.f32	s13, s0
 8001e52:	eeb0 7a60 	vmov.f32	s14, s1
 8001e56:	eef0 7a41 	vmov.f32	s15, s2
 8001e5a:	edc7 6a2e 	vstr	s13, [r7, #184]	@ 0xb8
 8001e5e:	ed87 7a2f 	vstr	s14, [r7, #188]	@ 0xbc
 8001e62:	edc7 7a30 	vstr	s15, [r7, #192]	@ 0xc0
 8001e66:	6afc      	ldr	r4, [r7, #44]	@ 0x2c
 8001e68:	ed97 5a0c 	vldr	s10, [r7, #48]	@ 0x30
 8001e6c:	edd7 5a0d 	vldr	s11, [r7, #52]	@ 0x34
 8001e70:	ed97 6a0e 	vldr	s12, [r7, #56]	@ 0x38
 8001e74:	edd7 6a2e 	vldr	s13, [r7, #184]	@ 0xb8
 8001e78:	ed97 7a2f 	vldr	s14, [r7, #188]	@ 0xbc
 8001e7c:	edd7 7a30 	vldr	s15, [r7, #192]	@ 0xc0
 8001e80:	eef0 1a45 	vmov.f32	s3, s10
 8001e84:	eeb0 2a65 	vmov.f32	s4, s11
 8001e88:	eef0 2a46 	vmov.f32	s5, s12
 8001e8c:	eeb0 0a66 	vmov.f32	s0, s13
 8001e90:	eef0 0a47 	vmov.f32	s1, s14
 8001e94:	eeb0 1a67 	vmov.f32	s2, s15
 8001e98:	f000 fb62 	bl	8002560 <Feedback>
 8001e9c:	eef0 6a40 	vmov.f32	s13, s0
 8001ea0:	eeb0 7a60 	vmov.f32	s14, s1
 8001ea4:	eef0 7a41 	vmov.f32	s15, s2
 8001ea8:	edc4 6a14 	vstr	s13, [r4, #80]	@ 0x50
 8001eac:	ed84 7a15 	vstr	s14, [r4, #84]	@ 0x54
 8001eb0:	edc4 7a16 	vstr	s15, [r4, #88]	@ 0x58

        // Don't ignore magnetometer if magnetic error below threshold
        if (ahrs->initialising || ((FusionVectorMagnitudeSquared(ahrs->halfMagnetometerFeedback) <= ahrs->settings.magneticRejection))) {
 8001eb4:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001eb6:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
 8001eba:	2b00      	cmp	r3, #0
 8001ebc:	d118      	bne.n	8001ef0 <FusionAhrsUpdate+0x43c>
 8001ebe:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001ec0:	edd3 6a14 	vldr	s13, [r3, #80]	@ 0x50
 8001ec4:	ed93 7a15 	vldr	s14, [r3, #84]	@ 0x54
 8001ec8:	edd3 7a16 	vldr	s15, [r3, #88]	@ 0x58
 8001ecc:	eeb0 0a66 	vmov.f32	s0, s13
 8001ed0:	eef0 0a47 	vmov.f32	s1, s14
 8001ed4:	eeb0 1a67 	vmov.f32	s2, s15
 8001ed8:	f7ff fa74 	bl	80013c4 <FusionVectorMagnitudeSquared>
 8001edc:	eeb0 7a40 	vmov.f32	s14, s0
 8001ee0:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001ee2:	edd3 7a04 	vldr	s15, [r3, #16]
 8001ee6:	eeb4 7ae7 	vcmpe.f32	s14, s15
 8001eea:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8001eee:	d80a      	bhi.n	8001f06 <FusionAhrsUpdate+0x452>
            ahrs->magnetometerIgnored = false;
 8001ef0:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001ef2:	2200      	movs	r2, #0
 8001ef4:	f883 2068 	strb.w	r2, [r3, #104]	@ 0x68
            ahrs->magneticRecoveryTrigger -= 9;
 8001ef8:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001efa:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8001efc:	f1a3 0209 	sub.w	r2, r3, #9
 8001f00:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001f02:	66da      	str	r2, [r3, #108]	@ 0x6c
 8001f04:	e004      	b.n	8001f10 <FusionAhrsUpdate+0x45c>
        } else {
            ahrs->magneticRecoveryTrigger += 1;
 8001f06:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001f08:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 8001f0a:	1c5a      	adds	r2, r3, #1
 8001f0c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001f0e:	66da      	str	r2, [r3, #108]	@ 0x6c
        }

        // Don't ignore magnetometer during magnetic recovery
        if (ahrs->magneticRecoveryTrigger > ahrs->magneticRecoveryTimeout) {
 8001f10:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001f12:	6eda      	ldr	r2, [r3, #108]	@ 0x6c
 8001f14:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001f16:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8001f18:	429a      	cmp	r2, r3
 8001f1a:	dd07      	ble.n	8001f2c <FusionAhrsUpdate+0x478>
            ahrs->magneticRecoveryTimeout = 0;
 8001f1c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001f1e:	2200      	movs	r2, #0
 8001f20:	671a      	str	r2, [r3, #112]	@ 0x70
            ahrs->magnetometerIgnored = false;
 8001f22:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001f24:	2200      	movs	r2, #0
 8001f26:	f883 2068 	strb.w	r2, [r3, #104]	@ 0x68
 8001f2a:	e004      	b.n	8001f36 <FusionAhrsUpdate+0x482>
        } else {
            ahrs->magneticRecoveryTimeout = ahrs->settings.recoveryTriggerPeriod;
 8001f2c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001f2e:	695b      	ldr	r3, [r3, #20]
 8001f30:	461a      	mov	r2, r3
 8001f32:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001f34:	671a      	str	r2, [r3, #112]	@ 0x70
        }
        ahrs->magneticRecoveryTrigger = Clamp(ahrs->magneticRecoveryTrigger, 0, ahrs->settings.recoveryTriggerPeriod);
 8001f36:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001f38:	6ed8      	ldr	r0, [r3, #108]	@ 0x6c
 8001f3a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001f3c:	695b      	ldr	r3, [r3, #20]
 8001f3e:	461a      	mov	r2, r3
 8001f40:	2100      	movs	r1, #0
 8001f42:	f000 fbc2 	bl	80026ca <Clamp>
 8001f46:	4602      	mov	r2, r0
 8001f48:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001f4a:	66da      	str	r2, [r3, #108]	@ 0x6c

        // Apply magnetometer feedback
        if (ahrs->magnetometerIgnored == false) {
 8001f4c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001f4e:	f893 3068 	ldrb.w	r3, [r3, #104]	@ 0x68
 8001f52:	f083 0301 	eor.w	r3, r3, #1
 8001f56:	b2db      	uxtb	r3, r3
 8001f58:	2b00      	cmp	r3, #0
 8001f5a:	d006      	beq.n	8001f6a <FusionAhrsUpdate+0x4b6>
            halfMagnetometerFeedback = ahrs->halfMagnetometerFeedback;
 8001f5c:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 8001f5e:	f107 0370 	add.w	r3, r7, #112	@ 0x70
 8001f62:	3250      	adds	r2, #80	@ 0x50
 8001f64:	ca07      	ldmia	r2, {r0, r1, r2}
 8001f66:	e883 0007 	stmia.w	r3, {r0, r1, r2}
        }
    }

    // Convert gyroscope to radians per second scaled by 0.5
    const FusionVector halfGyroscope = FusionVectorMultiplyScalar(gyroscope, FusionDegreesToRadians(0.5f));
 8001f6a:	eeb6 0a00 	vmov.f32	s0, #96	@ 0x3f000000  0.5
 8001f6e:	f7fe ffb9 	bl	8000ee4 <FusionDegreesToRadians>
 8001f72:	eeb0 6a40 	vmov.f32	s12, s0
 8001f76:	edd7 6a08 	vldr	s13, [r7, #32]
 8001f7a:	ed97 7a09 	vldr	s14, [r7, #36]	@ 0x24
 8001f7e:	edd7 7a0a 	vldr	s15, [r7, #40]	@ 0x28
 8001f82:	eef0 1a46 	vmov.f32	s3, s12
 8001f86:	eeb0 0a66 	vmov.f32	s0, s13
 8001f8a:	eef0 0a47 	vmov.f32	s1, s14
 8001f8e:	eeb0 1a67 	vmov.f32	s2, s15
 8001f92:	f7ff f8c9 	bl	8001128 <FusionVectorMultiplyScalar>
 8001f96:	eef0 6a40 	vmov.f32	s13, s0
 8001f9a:	eeb0 7a60 	vmov.f32	s14, s1
 8001f9e:	eef0 7a41 	vmov.f32	s15, s2
 8001fa2:	edc7 6a16 	vstr	s13, [r7, #88]	@ 0x58
 8001fa6:	ed87 7a17 	vstr	s14, [r7, #92]	@ 0x5c
 8001faa:	edc7 7a18 	vstr	s15, [r7, #96]	@ 0x60

    // Apply feedback to gyroscope
    const FusionVector adjustedHalfGyroscope = FusionVectorAdd(halfGyroscope, FusionVectorMultiplyScalar(FusionVectorAdd(halfAccelerometerFeedback, halfMagnetometerFeedback), ahrs->rampedGain));
 8001fae:	ed97 5a1c 	vldr	s10, [r7, #112]	@ 0x70
 8001fb2:	edd7 5a1d 	vldr	s11, [r7, #116]	@ 0x74
 8001fb6:	ed97 6a1e 	vldr	s12, [r7, #120]	@ 0x78
 8001fba:	edd7 6a22 	vldr	s13, [r7, #136]	@ 0x88
 8001fbe:	ed97 7a23 	vldr	s14, [r7, #140]	@ 0x8c
 8001fc2:	edd7 7a24 	vldr	s15, [r7, #144]	@ 0x90
 8001fc6:	eef0 1a45 	vmov.f32	s3, s10
 8001fca:	eeb0 2a65 	vmov.f32	s4, s11
 8001fce:	eef0 2a46 	vmov.f32	s5, s12
 8001fd2:	eeb0 0a66 	vmov.f32	s0, s13
 8001fd6:	eef0 0a47 	vmov.f32	s1, s14
 8001fda:	eeb0 1a67 	vmov.f32	s2, s15
 8001fde:	f7ff f835 	bl	800104c <FusionVectorAdd>
 8001fe2:	eef0 6a40 	vmov.f32	s13, s0
 8001fe6:	eeb0 7a60 	vmov.f32	s14, s1
 8001fea:	eef0 7a41 	vmov.f32	s15, s2
 8001fee:	edc7 6a31 	vstr	s13, [r7, #196]	@ 0xc4
 8001ff2:	ed87 7a32 	vstr	s14, [r7, #200]	@ 0xc8
 8001ff6:	edc7 7a33 	vstr	s15, [r7, #204]	@ 0xcc
 8001ffa:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8001ffc:	ed93 6a0e 	vldr	s12, [r3, #56]	@ 0x38
 8002000:	edd7 6a31 	vldr	s13, [r7, #196]	@ 0xc4
 8002004:	ed97 7a32 	vldr	s14, [r7, #200]	@ 0xc8
 8002008:	edd7 7a33 	vldr	s15, [r7, #204]	@ 0xcc
 800200c:	eef0 1a46 	vmov.f32	s3, s12
 8002010:	eeb0 0a66 	vmov.f32	s0, s13
 8002014:	eef0 0a47 	vmov.f32	s1, s14
 8002018:	eeb0 1a67 	vmov.f32	s2, s15
 800201c:	f7ff f884 	bl	8001128 <FusionVectorMultiplyScalar>
 8002020:	eef0 6a40 	vmov.f32	s13, s0
 8002024:	eeb0 7a60 	vmov.f32	s14, s1
 8002028:	eef0 7a41 	vmov.f32	s15, s2
 800202c:	edc7 6a34 	vstr	s13, [r7, #208]	@ 0xd0
 8002030:	ed87 7a35 	vstr	s14, [r7, #212]	@ 0xd4
 8002034:	edc7 7a36 	vstr	s15, [r7, #216]	@ 0xd8
 8002038:	ed97 5a34 	vldr	s10, [r7, #208]	@ 0xd0
 800203c:	edd7 5a35 	vldr	s11, [r7, #212]	@ 0xd4
 8002040:	ed97 6a36 	vldr	s12, [r7, #216]	@ 0xd8
 8002044:	edd7 6a16 	vldr	s13, [r7, #88]	@ 0x58
 8002048:	ed97 7a17 	vldr	s14, [r7, #92]	@ 0x5c
 800204c:	edd7 7a18 	vldr	s15, [r7, #96]	@ 0x60
 8002050:	eef0 1a45 	vmov.f32	s3, s10
 8002054:	eeb0 2a65 	vmov.f32	s4, s11
 8002058:	eef0 2a46 	vmov.f32	s5, s12
 800205c:	eeb0 0a66 	vmov.f32	s0, s13
 8002060:	eef0 0a47 	vmov.f32	s1, s14
 8002064:	eeb0 1a67 	vmov.f32	s2, s15
 8002068:	f7fe fff0 	bl	800104c <FusionVectorAdd>
 800206c:	eef0 6a40 	vmov.f32	s13, s0
 8002070:	eeb0 7a60 	vmov.f32	s14, s1
 8002074:	eef0 7a41 	vmov.f32	s15, s2
 8002078:	edc7 6a13 	vstr	s13, [r7, #76]	@ 0x4c
 800207c:	ed87 7a14 	vstr	s14, [r7, #80]	@ 0x50
 8002080:	edc7 7a15 	vstr	s15, [r7, #84]	@ 0x54

    // Integrate rate of change of quaternion
    ahrs->quaternion = FusionQuaternionAdd(ahrs->quaternion, FusionQuaternionMultiplyVector(ahrs->quaternion, FusionVectorMultiplyScalar(adjustedHalfGyroscope, deltaTime)));
 8002084:	edd7 6a13 	vldr	s13, [r7, #76]	@ 0x4c
 8002088:	ed97 7a14 	vldr	s14, [r7, #80]	@ 0x50
 800208c:	edd7 7a15 	vldr	s15, [r7, #84]	@ 0x54
 8002090:	edd7 1a01 	vldr	s3, [r7, #4]
 8002094:	eeb0 0a66 	vmov.f32	s0, s13
 8002098:	eef0 0a47 	vmov.f32	s1, s14
 800209c:	eeb0 1a67 	vmov.f32	s2, s15
 80020a0:	f7ff f842 	bl	8001128 <FusionVectorMultiplyScalar>
 80020a4:	eef0 6a40 	vmov.f32	s13, s0
 80020a8:	eeb0 7a60 	vmov.f32	s14, s1
 80020ac:	eef0 7a41 	vmov.f32	s15, s2
 80020b0:	edc7 6a37 	vstr	s13, [r7, #220]	@ 0xdc
 80020b4:	ed87 7a38 	vstr	s14, [r7, #224]	@ 0xe0
 80020b8:	edc7 7a39 	vstr	s15, [r7, #228]	@ 0xe4
 80020bc:	edd7 4a37 	vldr	s9, [r7, #220]	@ 0xdc
 80020c0:	ed97 5a38 	vldr	s10, [r7, #224]	@ 0xe0
 80020c4:	edd7 5a39 	vldr	s11, [r7, #228]	@ 0xe4
 80020c8:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 80020ca:	ed93 6a06 	vldr	s12, [r3, #24]
 80020ce:	edd3 6a07 	vldr	s13, [r3, #28]
 80020d2:	ed93 7a08 	vldr	s14, [r3, #32]
 80020d6:	edd3 7a09 	vldr	s15, [r3, #36]	@ 0x24
 80020da:	eeb0 2a64 	vmov.f32	s4, s9
 80020de:	eef0 2a45 	vmov.f32	s5, s10
 80020e2:	eeb0 3a65 	vmov.f32	s6, s11
 80020e6:	eeb0 0a46 	vmov.f32	s0, s12
 80020ea:	eef0 0a66 	vmov.f32	s1, s13
 80020ee:	eeb0 1a47 	vmov.f32	s2, s14
 80020f2:	eef0 1a67 	vmov.f32	s3, s15
 80020f6:	f7ff fa8e 	bl	8001616 <FusionQuaternionMultiplyVector>
 80020fa:	eeb0 6a40 	vmov.f32	s12, s0
 80020fe:	eef0 6a60 	vmov.f32	s13, s1
 8002102:	eeb0 7a41 	vmov.f32	s14, s2
 8002106:	eef0 7a61 	vmov.f32	s15, s3
 800210a:	ed87 6a3a 	vstr	s12, [r7, #232]	@ 0xe8
 800210e:	edc7 6a3b 	vstr	s13, [r7, #236]	@ 0xec
 8002112:	ed87 7a3c 	vstr	s14, [r7, #240]	@ 0xf0
 8002116:	edc7 7a3d 	vstr	s15, [r7, #244]	@ 0xf4
 800211a:	6afc      	ldr	r4, [r7, #44]	@ 0x2c
 800211c:	ed97 4a3a 	vldr	s8, [r7, #232]	@ 0xe8
 8002120:	edd7 4a3b 	vldr	s9, [r7, #236]	@ 0xec
 8002124:	ed97 5a3c 	vldr	s10, [r7, #240]	@ 0xf0
 8002128:	edd7 5a3d 	vldr	s11, [r7, #244]	@ 0xf4
 800212c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 800212e:	ed93 6a06 	vldr	s12, [r3, #24]
 8002132:	edd3 6a07 	vldr	s13, [r3, #28]
 8002136:	ed93 7a08 	vldr	s14, [r3, #32]
 800213a:	edd3 7a09 	vldr	s15, [r3, #36]	@ 0x24
 800213e:	eeb0 2a44 	vmov.f32	s4, s8
 8002142:	eef0 2a64 	vmov.f32	s5, s9
 8002146:	eeb0 3a45 	vmov.f32	s6, s10
 800214a:	eef0 3a65 	vmov.f32	s7, s11
 800214e:	eeb0 0a46 	vmov.f32	s0, s12
 8002152:	eef0 0a66 	vmov.f32	s1, s13
 8002156:	eeb0 1a47 	vmov.f32	s2, s14
 800215a:	eef0 1a67 	vmov.f32	s3, s15
 800215e:	f7ff f9f8 	bl	8001552 <FusionQuaternionAdd>
 8002162:	eeb0 6a40 	vmov.f32	s12, s0
 8002166:	eef0 6a60 	vmov.f32	s13, s1
 800216a:	eeb0 7a41 	vmov.f32	s14, s2
 800216e:	eef0 7a61 	vmov.f32	s15, s3
 8002172:	ed84 6a06 	vstr	s12, [r4, #24]
 8002176:	edc4 6a07 	vstr	s13, [r4, #28]
 800217a:	ed84 7a08 	vstr	s14, [r4, #32]
 800217e:	edc4 7a09 	vstr	s15, [r4, #36]	@ 0x24

    // Normalise quaternion
    ahrs->quaternion = FusionQuaternionNormalise(ahrs->quaternion);
 8002182:	6afc      	ldr	r4, [r7, #44]	@ 0x2c
 8002184:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
 8002186:	ed93 6a06 	vldr	s12, [r3, #24]
 800218a:	edd3 6a07 	vldr	s13, [r3, #28]
 800218e:	ed93 7a08 	vldr	s14, [r3, #32]
 8002192:	edd3 7a09 	vldr	s15, [r3, #36]	@ 0x24
 8002196:	eeb0 0a46 	vmov.f32	s0, s12
 800219a:	eef0 0a66 	vmov.f32	s1, s13
 800219e:	eeb0 1a47 	vmov.f32	s2, s14
 80021a2:	eef0 1a67 	vmov.f32	s3, s15
 80021a6:	f7ff fad6 	bl	8001756 <FusionQuaternionNormalise>
 80021aa:	eeb0 6a40 	vmov.f32	s12, s0
 80021ae:	eef0 6a60 	vmov.f32	s13, s1
 80021b2:	eeb0 7a41 	vmov.f32	s14, s2
 80021b6:	eef0 7a61 	vmov.f32	s15, s3
 80021ba:	ed84 6a06 	vstr	s12, [r4, #24]
 80021be:	edc4 6a07 	vstr	s13, [r4, #28]
 80021c2:	ed84 7a08 	vstr	s14, [r4, #32]
 80021c6:	edc4 7a09 	vstr	s15, [r4, #36]	@ 0x24
#undef Q
}
 80021ca:	bf00      	nop
 80021cc:	37fc      	adds	r7, #252	@ 0xfc
 80021ce:	46bd      	mov	sp, r7
 80021d0:	bd90      	pop	{r4, r7, pc}

080021d2 <HalfGravity>:
/**
 * @brief Returns the direction of gravity scaled by 0.5.
 * @param ahrs AHRS algorithm structure.
 * @return Direction of gravity scaled by 0.5.
 */
static inline FusionVector HalfGravity(const FusionAhrs *const ahrs) {
 80021d2:	b480      	push	{r7}
 80021d4:	b093      	sub	sp, #76	@ 0x4c
 80021d6:	af00      	add	r7, sp, #0
 80021d8:	6178      	str	r0, [r7, #20]
#define Q ahrs->quaternion.element
    switch (ahrs->settings.convention) {
 80021da:	697b      	ldr	r3, [r7, #20]
 80021dc:	781b      	ldrb	r3, [r3, #0]
 80021de:	2b01      	cmp	r3, #1
 80021e0:	dc02      	bgt.n	80021e8 <HalfGravity+0x16>
 80021e2:	2b00      	cmp	r3, #0
 80021e4:	da03      	bge.n	80021ee <HalfGravity+0x1c>
 80021e6:	e094      	b.n	8002312 <HalfGravity+0x140>
 80021e8:	2b02      	cmp	r3, #2
 80021ea:	d048      	beq.n	800227e <HalfGravity+0xac>
 80021ec:	e091      	b.n	8002312 <HalfGravity+0x140>
        case FusionConventionNwu:
        case FusionConventionEnu: {
            const FusionVector halfGravity = {.axis = {
                    .x = Q.x * Q.z - Q.w * Q.y,
 80021ee:	697b      	ldr	r3, [r7, #20]
 80021f0:	ed93 7a07 	vldr	s14, [r3, #28]
 80021f4:	697b      	ldr	r3, [r7, #20]
 80021f6:	edd3 7a09 	vldr	s15, [r3, #36]	@ 0x24
 80021fa:	ee27 7a27 	vmul.f32	s14, s14, s15
 80021fe:	697b      	ldr	r3, [r7, #20]
 8002200:	edd3 6a06 	vldr	s13, [r3, #24]
 8002204:	697b      	ldr	r3, [r7, #20]
 8002206:	edd3 7a08 	vldr	s15, [r3, #32]
 800220a:	ee66 7aa7 	vmul.f32	s15, s13, s15
 800220e:	ee77 7a67 	vsub.f32	s15, s14, s15
            const FusionVector halfGravity = {.axis = {
 8002212:	edc7 7a09 	vstr	s15, [r7, #36]	@ 0x24
                    .y = Q.y * Q.z + Q.w * Q.x,
 8002216:	697b      	ldr	r3, [r7, #20]
 8002218:	ed93 7a08 	vldr	s14, [r3, #32]
 800221c:	697b      	ldr	r3, [r7, #20]
 800221e:	edd3 7a09 	vldr	s15, [r3, #36]	@ 0x24
 8002222:	ee27 7a27 	vmul.f32	s14, s14, s15
 8002226:	697b      	ldr	r3, [r7, #20]
 8002228:	edd3 6a06 	vldr	s13, [r3, #24]
 800222c:	697b      	ldr	r3, [r7, #20]
 800222e:	edd3 7a07 	vldr	s15, [r3, #28]
 8002232:	ee66 7aa7 	vmul.f32	s15, s13, s15
 8002236:	ee77 7a27 	vadd.f32	s15, s14, s15
            const FusionVector halfGravity = {.axis = {
 800223a:	edc7 7a0a 	vstr	s15, [r7, #40]	@ 0x28
                    .z = Q.w * Q.w - 0.5f + Q.z * Q.z,
 800223e:	697b      	ldr	r3, [r7, #20]
 8002240:	ed93 7a06 	vldr	s14, [r3, #24]
 8002244:	697b      	ldr	r3, [r7, #20]
 8002246:	edd3 7a06 	vldr	s15, [r3, #24]
 800224a:	ee67 7a27 	vmul.f32	s15, s14, s15
 800224e:	eeb6 7a00 	vmov.f32	s14, #96	@ 0x3f000000  0.5
 8002252:	ee37 7ac7 	vsub.f32	s14, s15, s14
 8002256:	697b      	ldr	r3, [r7, #20]
 8002258:	edd3 6a09 	vldr	s13, [r3, #36]	@ 0x24
 800225c:	697b      	ldr	r3, [r7, #20]
 800225e:	edd3 7a09 	vldr	s15, [r3, #36]	@ 0x24
 8002262:	ee66 7aa7 	vmul.f32	s15, s13, s15
 8002266:	ee77 7a27 	vadd.f32	s15, s14, s15
            const FusionVector halfGravity = {.axis = {
 800226a:	edc7 7a0b 	vstr	s15, [r7, #44]	@ 0x2c
            }}; // third column of transposed rotation matrix scaled by 0.5
            return halfGravity;
 800226e:	f107 033c 	add.w	r3, r7, #60	@ 0x3c
 8002272:	f107 0224 	add.w	r2, r7, #36	@ 0x24
 8002276:	ca07      	ldmia	r2, {r0, r1, r2}
 8002278:	e883 0007 	stmia.w	r3, {r0, r1, r2}
 800227c:	e052      	b.n	8002324 <HalfGravity+0x152>
        }
        case FusionConventionNed: {
            const FusionVector halfGravity = {.axis = {
                    .x = Q.w * Q.y - Q.x * Q.z,
 800227e:	697b      	ldr	r3, [r7, #20]
 8002280:	ed93 7a06 	vldr	s14, [r3, #24]
 8002284:	697b      	ldr	r3, [r7, #20]
 8002286:	edd3 7a08 	vldr	s15, [r3, #32]
 800228a:	ee27 7a27 	vmul.f32	s14, s14, s15
 800228e:	697b      	ldr	r3, [r7, #20]
 8002290:	edd3 6a07 	vldr	s13, [r3, #28]
 8002294:	697b      	ldr	r3, [r7, #20]
 8002296:	edd3 7a09 	vldr	s15, [r3, #36]	@ 0x24
 800229a:	ee66 7aa7 	vmul.f32	s15, s13, s15
 800229e:	ee77 7a67 	vsub.f32	s15, s14, s15
            const FusionVector halfGravity = {.axis = {
 80022a2:	edc7 7a06 	vstr	s15, [r7, #24]
                    .y = -1.0f * (Q.y * Q.z + Q.w * Q.x),
 80022a6:	697b      	ldr	r3, [r7, #20]
 80022a8:	ed93 7a08 	vldr	s14, [r3, #32]
 80022ac:	697b      	ldr	r3, [r7, #20]
 80022ae:	edd3 7a09 	vldr	s15, [r3, #36]	@ 0x24
 80022b2:	ee27 7a27 	vmul.f32	s14, s14, s15
 80022b6:	697b      	ldr	r3, [r7, #20]
 80022b8:	edd3 6a06 	vldr	s13, [r3, #24]
 80022bc:	697b      	ldr	r3, [r7, #20]
 80022be:	edd3 7a07 	vldr	s15, [r3, #28]
 80022c2:	ee66 7aa7 	vmul.f32	s15, s13, s15
 80022c6:	ee77 7a27 	vadd.f32	s15, s14, s15
 80022ca:	eef1 7a67 	vneg.f32	s15, s15
            const FusionVector halfGravity = {.axis = {
 80022ce:	edc7 7a07 	vstr	s15, [r7, #28]
                    .z = 0.5f - Q.w * Q.w - Q.z * Q.z,
 80022d2:	697b      	ldr	r3, [r7, #20]
 80022d4:	ed93 7a06 	vldr	s14, [r3, #24]
 80022d8:	697b      	ldr	r3, [r7, #20]
 80022da:	edd3 7a06 	vldr	s15, [r3, #24]
 80022de:	ee67 7a27 	vmul.f32	s15, s14, s15
 80022e2:	eeb6 7a00 	vmov.f32	s14, #96	@ 0x3f000000  0.5
 80022e6:	ee37 7a67 	vsub.f32	s14, s14, s15
 80022ea:	697b      	ldr	r3, [r7, #20]
 80022ec:	edd3 6a09 	vldr	s13, [r3, #36]	@ 0x24
 80022f0:	697b      	ldr	r3, [r7, #20]
 80022f2:	edd3 7a09 	vldr	s15, [r3, #36]	@ 0x24
 80022f6:	ee66 7aa7 	vmul.f32	s15, s13, s15
 80022fa:	ee77 7a67 	vsub.f32	s15, s14, s15
            const FusionVector halfGravity = {.axis = {
 80022fe:	edc7 7a08 	vstr	s15, [r7, #32]
            }}; // third column of transposed rotation matrix scaled by -0.5
            return halfGravity;
 8002302:	f107 033c 	add.w	r3, r7, #60	@ 0x3c
 8002306:	f107 0218 	add.w	r2, r7, #24
 800230a:	ca07      	ldmia	r2, {r0, r1, r2}
 800230c:	e883 0007 	stmia.w	r3, {r0, r1, r2}
 8002310:	e008      	b.n	8002324 <HalfGravity+0x152>
        }
    }
    return FUSION_VECTOR_ZERO; // avoid compiler warning
 8002312:	f04f 0300 	mov.w	r3, #0
 8002316:	63fb      	str	r3, [r7, #60]	@ 0x3c
 8002318:	f04f 0300 	mov.w	r3, #0
 800231c:	643b      	str	r3, [r7, #64]	@ 0x40
 800231e:	f04f 0300 	mov.w	r3, #0
 8002322:	647b      	str	r3, [r7, #68]	@ 0x44
#undef Q
}
 8002324:	6bf9      	ldr	r1, [r7, #60]	@ 0x3c
 8002326:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
 8002328:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
 800232a:	ee06 1a90 	vmov	s13, r1
 800232e:	ee07 2a10 	vmov	s14, r2
 8002332:	ee07 3a90 	vmov	s15, r3
 8002336:	eeb0 0a66 	vmov.f32	s0, s13
 800233a:	eef0 0a47 	vmov.f32	s1, s14
 800233e:	eeb0 1a67 	vmov.f32	s2, s15
 8002342:	374c      	adds	r7, #76	@ 0x4c
 8002344:	46bd      	mov	sp, r7
 8002346:	f85d 7b04 	ldr.w	r7, [sp], #4
 800234a:	4770      	bx	lr

0800234c <HalfMagnetic>:
/**
 * @brief Returns the direction of the magnetic field scaled by 0.5.
 * @param ahrs AHRS algorithm structure.
 * @return Direction of the magnetic field scaled by 0.5.
 */
static inline FusionVector HalfMagnetic(const FusionAhrs *const ahrs) {
 800234c:	b480      	push	{r7}
 800234e:	b097      	sub	sp, #92	@ 0x5c
 8002350:	af00      	add	r7, sp, #0
 8002352:	6178      	str	r0, [r7, #20]
#define Q ahrs->quaternion.element
    switch (ahrs->settings.convention) {
 8002354:	697b      	ldr	r3, [r7, #20]
 8002356:	781b      	ldrb	r3, [r3, #0]
 8002358:	2b02      	cmp	r3, #2
 800235a:	f000 809a 	beq.w	8002492 <HalfMagnetic+0x146>
 800235e:	2b02      	cmp	r3, #2
 8002360:	f300 80e1 	bgt.w	8002526 <HalfMagnetic+0x1da>
 8002364:	2b00      	cmp	r3, #0
 8002366:	d002      	beq.n	800236e <HalfMagnetic+0x22>
 8002368:	2b01      	cmp	r3, #1
 800236a:	d048      	beq.n	80023fe <HalfMagnetic+0xb2>
 800236c:	e0db      	b.n	8002526 <HalfMagnetic+0x1da>
        case FusionConventionNwu: {
            const FusionVector halfMagnetic = {.axis = {
                    .x = Q.x * Q.y + Q.w * Q.z,
 800236e:	697b      	ldr	r3, [r7, #20]
 8002370:	ed93 7a07 	vldr	s14, [r3, #28]
 8002374:	697b      	ldr	r3, [r7, #20]
 8002376:	edd3 7a08 	vldr	s15, [r3, #32]
 800237a:	ee27 7a27 	vmul.f32	s14, s14, s15
 800237e:	697b      	ldr	r3, [r7, #20]
 8002380:	edd3 6a06 	vldr	s13, [r3, #24]
 8002384:	697b      	ldr	r3, [r7, #20]
 8002386:	edd3 7a09 	vldr	s15, [r3, #36]	@ 0x24
 800238a:	ee66 7aa7 	vmul.f32	s15, s13, s15
 800238e:	ee77 7a27 	vadd.f32	s15, s14, s15
            const FusionVector halfMagnetic = {.axis = {
 8002392:	edc7 7a0d 	vstr	s15, [r7, #52]	@ 0x34
                    .y = Q.w * Q.w - 0.5f + Q.y * Q.y,
 8002396:	697b      	ldr	r3, [r7, #20]
 8002398:	ed93 7a06 	vldr	s14, [r3, #24]
 800239c:	697b      	ldr	r3, [r7, #20]
 800239e:	edd3 7a06 	vldr	s15, [r3, #24]
 80023a2:	ee67 7a27 	vmul.f32	s15, s14, s15
 80023a6:	eeb6 7a00 	vmov.f32	s14, #96	@ 0x3f000000  0.5
 80023aa:	ee37 7ac7 	vsub.f32	s14, s15, s14
 80023ae:	697b      	ldr	r3, [r7, #20]
 80023b0:	edd3 6a08 	vldr	s13, [r3, #32]
 80023b4:	697b      	ldr	r3, [r7, #20]
 80023b6:	edd3 7a08 	vldr	s15, [r3, #32]
 80023ba:	ee66 7aa7 	vmul.f32	s15, s13, s15
 80023be:	ee77 7a27 	vadd.f32	s15, s14, s15
            const FusionVector halfMagnetic = {.axis = {
 80023c2:	edc7 7a0e 	vstr	s15, [r7, #56]	@ 0x38
                    .z = Q.y * Q.z - Q.w * Q.x,
 80023c6:	697b      	ldr	r3, [r7, #20]
 80023c8:	ed93 7a08 	vldr	s14, [r3, #32]
 80023cc:	697b      	ldr	r3, [r7, #20]
 80023ce:	edd3 7a09 	vldr	s15, [r3, #36]	@ 0x24
 80023d2:	ee27 7a27 	vmul.f32	s14, s14, s15
 80023d6:	697b      	ldr	r3, [r7, #20]
 80023d8:	edd3 6a06 	vldr	s13, [r3, #24]
 80023dc:	697b      	ldr	r3, [r7, #20]
 80023de:	edd3 7a07 	vldr	s15, [r3, #28]
 80023e2:	ee66 7aa7 	vmul.f32	s15, s13, s15
 80023e6:	ee77 7a67 	vsub.f32	s15, s14, s15
            const FusionVector halfMagnetic = {.axis = {
 80023ea:	edc7 7a0f 	vstr	s15, [r7, #60]	@ 0x3c
            }}; // second column of transposed rotation matrix scaled by 0.5
            return halfMagnetic;
 80023ee:	f107 034c 	add.w	r3, r7, #76	@ 0x4c
 80023f2:	f107 0234 	add.w	r2, r7, #52	@ 0x34
 80023f6:	ca07      	ldmia	r2, {r0, r1, r2}
 80023f8:	e883 0007 	stmia.w	r3, {r0, r1, r2}
 80023fc:	e09c      	b.n	8002538 <HalfMagnetic+0x1ec>
        }
        case FusionConventionEnu: {
            const FusionVector halfMagnetic = {.axis = {
                    .x = 0.5f - Q.w * Q.w - Q.x * Q.x,
 80023fe:	697b      	ldr	r3, [r7, #20]
 8002400:	ed93 7a06 	vldr	s14, [r3, #24]
 8002404:	697b      	ldr	r3, [r7, #20]
 8002406:	edd3 7a06 	vldr	s15, [r3, #24]
 800240a:	ee67 7a27 	vmul.f32	s15, s14, s15
 800240e:	eeb6 7a00 	vmov.f32	s14, #96	@ 0x3f000000  0.5
 8002412:	ee37 7a67 	vsub.f32	s14, s14, s15
 8002416:	697b      	ldr	r3, [r7, #20]
 8002418:	edd3 6a07 	vldr	s13, [r3, #28]
 800241c:	697b      	ldr	r3, [r7, #20]
 800241e:	edd3 7a07 	vldr	s15, [r3, #28]
 8002422:	ee66 7aa7 	vmul.f32	s15, s13, s15
 8002426:	ee77 7a67 	vsub.f32	s15, s14, s15
            const FusionVector halfMagnetic = {.axis = {
 800242a:	edc7 7a0a 	vstr	s15, [r7, #40]	@ 0x28
                    .y = Q.w * Q.z - Q.x * Q.y,
 800242e:	697b      	ldr	r3, [r7, #20]
 8002430:	ed93 7a06 	vldr	s14, [r3, #24]
 8002434:	697b      	ldr	r3, [r7, #20]
 8002436:	edd3 7a09 	vldr	s15, [r3, #36]	@ 0x24
 800243a:	ee27 7a27 	vmul.f32	s14, s14, s15
 800243e:	697b      	ldr	r3, [r7, #20]
 8002440:	edd3 6a07 	vldr	s13, [r3, #28]
 8002444:	697b      	ldr	r3, [r7, #20]
 8002446:	edd3 7a08 	vldr	s15, [r3, #32]
 800244a:	ee66 7aa7 	vmul.f32	s15, s13, s15
 800244e:	ee77 7a67 	vsub.f32	s15, s14, s15
            const FusionVector halfMagnetic = {.axis = {
 8002452:	edc7 7a0b 	vstr	s15, [r7, #44]	@ 0x2c
                    .z = -1.0f * (Q.x * Q.z + Q.w * Q.y),
 8002456:	697b      	ldr	r3, [r7, #20]
 8002458:	ed93 7a07 	vldr	s14, [r3, #28]
 800245c:	697b      	ldr	r3, [r7, #20]
 800245e:	edd3 7a09 	vldr	s15, [r3, #36]	@ 0x24
 8002462:	ee27 7a27 	vmul.f32	s14, s14, s15
 8002466:	697b      	ldr	r3, [r7, #20]
 8002468:	edd3 6a06 	vldr	s13, [r3, #24]
 800246c:	697b      	ldr	r3, [r7, #20]
 800246e:	edd3 7a08 	vldr	s15, [r3, #32]
 8002472:	ee66 7aa7 	vmul.f32	s15, s13, s15
 8002476:	ee77 7a27 	vadd.f32	s15, s14, s15
 800247a:	eef1 7a67 	vneg.f32	s15, s15
            const FusionVector halfMagnetic = {.axis = {
 800247e:	edc7 7a0c 	vstr	s15, [r7, #48]	@ 0x30
            }}; // first column of transposed rotation matrix scaled by -0.5
            return halfMagnetic;
 8002482:	f107 034c 	add.w	r3, r7, #76	@ 0x4c
 8002486:	f107 0228 	add.w	r2, r7, #40	@ 0x28
 800248a:	ca07      	ldmia	r2, {r0, r1, r2}
 800248c:	e883 0007 	stmia.w	r3, {r0, r1, r2}
 8002490:	e052      	b.n	8002538 <HalfMagnetic+0x1ec>
        }
        case FusionConventionNed: {
            const FusionVector halfMagnetic = {.axis = {
                    .x = -1.0f * (Q.x * Q.y + Q.w * Q.z),
 8002492:	697b      	ldr	r3, [r7, #20]
 8002494:	ed93 7a07 	vldr	s14, [r3, #28]
 8002498:	697b      	ldr	r3, [r7, #20]
 800249a:	edd3 7a08 	vldr	s15, [r3, #32]
 800249e:	ee27 7a27 	vmul.f32	s14, s14, s15
 80024a2:	697b      	ldr	r3, [r7, #20]
 80024a4:	edd3 6a06 	vldr	s13, [r3, #24]
 80024a8:	697b      	ldr	r3, [r7, #20]
 80024aa:	edd3 7a09 	vldr	s15, [r3, #36]	@ 0x24
 80024ae:	ee66 7aa7 	vmul.f32	s15, s13, s15
 80024b2:	ee77 7a27 	vadd.f32	s15, s14, s15
 80024b6:	eef1 7a67 	vneg.f32	s15, s15
            const FusionVector halfMagnetic = {.axis = {
 80024ba:	edc7 7a07 	vstr	s15, [r7, #28]
                    .y = 0.5f - Q.w * Q.w - Q.y * Q.y,
 80024be:	697b      	ldr	r3, [r7, #20]
 80024c0:	ed93 7a06 	vldr	s14, [r3, #24]
 80024c4:	697b      	ldr	r3, [r7, #20]
 80024c6:	edd3 7a06 	vldr	s15, [r3, #24]
 80024ca:	ee67 7a27 	vmul.f32	s15, s14, s15
 80024ce:	eeb6 7a00 	vmov.f32	s14, #96	@ 0x3f000000  0.5
 80024d2:	ee37 7a67 	vsub.f32	s14, s14, s15
 80024d6:	697b      	ldr	r3, [r7, #20]
 80024d8:	edd3 6a08 	vldr	s13, [r3, #32]
 80024dc:	697b      	ldr	r3, [r7, #20]
 80024de:	edd3 7a08 	vldr	s15, [r3, #32]
 80024e2:	ee66 7aa7 	vmul.f32	s15, s13, s15
 80024e6:	ee77 7a67 	vsub.f32	s15, s14, s15
            const FusionVector halfMagnetic = {.axis = {
 80024ea:	edc7 7a08 	vstr	s15, [r7, #32]
                    .z = Q.w * Q.x - Q.y * Q.z,
 80024ee:	697b      	ldr	r3, [r7, #20]
 80024f0:	ed93 7a06 	vldr	s14, [r3, #24]
 80024f4:	697b      	ldr	r3, [r7, #20]
 80024f6:	edd3 7a07 	vldr	s15, [r3, #28]
 80024fa:	ee27 7a27 	vmul.f32	s14, s14, s15
 80024fe:	697b      	ldr	r3, [r7, #20]
 8002500:	edd3 6a08 	vldr	s13, [r3, #32]
 8002504:	697b      	ldr	r3, [r7, #20]
 8002506:	edd3 7a09 	vldr	s15, [r3, #36]	@ 0x24
 800250a:	ee66 7aa7 	vmul.f32	s15, s13, s15
 800250e:	ee77 7a67 	vsub.f32	s15, s14, s15
            const FusionVector halfMagnetic = {.axis = {
 8002512:	edc7 7a09 	vstr	s15, [r7, #36]	@ 0x24
            }}; // second column of transposed rotation matrix scaled by -0.5
            return halfMagnetic;
 8002516:	f107 034c 	add.w	r3, r7, #76	@ 0x4c
 800251a:	f107 021c 	add.w	r2, r7, #28
 800251e:	ca07      	ldmia	r2, {r0, r1, r2}
 8002520:	e883 0007 	stmia.w	r3, {r0, r1, r2}
 8002524:	e008      	b.n	8002538 <HalfMagnetic+0x1ec>
        }
    }
    return FUSION_VECTOR_ZERO; // avoid compiler warning
 8002526:	f04f 0300 	mov.w	r3, #0
 800252a:	64fb      	str	r3, [r7, #76]	@ 0x4c
 800252c:	f04f 0300 	mov.w	r3, #0
 8002530:	653b      	str	r3, [r7, #80]	@ 0x50
 8002532:	f04f 0300 	mov.w	r3, #0
 8002536:	657b      	str	r3, [r7, #84]	@ 0x54
#undef Q
}
 8002538:	6cf9      	ldr	r1, [r7, #76]	@ 0x4c
 800253a:	6d3a      	ldr	r2, [r7, #80]	@ 0x50
 800253c:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 800253e:	ee06 1a90 	vmov	s13, r1
 8002542:	ee07 2a10 	vmov	s14, r2
 8002546:	ee07 3a90 	vmov	s15, r3
 800254a:	eeb0 0a66 	vmov.f32	s0, s13
 800254e:	eef0 0a47 	vmov.f32	s1, s14
 8002552:	eeb0 1a67 	vmov.f32	s2, s15
 8002556:	375c      	adds	r7, #92	@ 0x5c
 8002558:	46bd      	mov	sp, r7
 800255a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800255e:	4770      	bx	lr

08002560 <Feedback>:
 * @brief Returns the feedback.
 * @param sensor Sensor.
 * @param reference Reference.
 * @return Feedback.
 */
static inline FusionVector Feedback(const FusionVector sensor, const FusionVector reference) {
 8002560:	b580      	push	{r7, lr}
 8002562:	b090      	sub	sp, #64	@ 0x40
 8002564:	af00      	add	r7, sp, #0
 8002566:	eeb0 5a40 	vmov.f32	s10, s0
 800256a:	eef0 5a60 	vmov.f32	s11, s1
 800256e:	eeb0 6a41 	vmov.f32	s12, s2
 8002572:	eef0 6a61 	vmov.f32	s13, s3
 8002576:	eeb0 7a42 	vmov.f32	s14, s4
 800257a:	eef0 7a62 	vmov.f32	s15, s5
 800257e:	ed87 5a07 	vstr	s10, [r7, #28]
 8002582:	edc7 5a08 	vstr	s11, [r7, #32]
 8002586:	ed87 6a09 	vstr	s12, [r7, #36]	@ 0x24
 800258a:	edc7 6a04 	vstr	s13, [r7, #16]
 800258e:	ed87 7a05 	vstr	s14, [r7, #20]
 8002592:	edc7 7a06 	vstr	s15, [r7, #24]
    if (FusionVectorDotProduct(sensor, reference) < 0.0f) { // if error is >90 degrees
 8002596:	ed97 5a04 	vldr	s10, [r7, #16]
 800259a:	edd7 5a05 	vldr	s11, [r7, #20]
 800259e:	ed97 6a06 	vldr	s12, [r7, #24]
 80025a2:	edd7 6a07 	vldr	s13, [r7, #28]
 80025a6:	ed97 7a08 	vldr	s14, [r7, #32]
 80025aa:	edd7 7a09 	vldr	s15, [r7, #36]	@ 0x24
 80025ae:	eef0 1a45 	vmov.f32	s3, s10
 80025b2:	eeb0 2a65 	vmov.f32	s4, s11
 80025b6:	eef0 2a46 	vmov.f32	s5, s12
 80025ba:	eeb0 0a66 	vmov.f32	s0, s13
 80025be:	eef0 0a47 	vmov.f32	s1, s14
 80025c2:	eeb0 1a67 	vmov.f32	s2, s15
 80025c6:	f7fe fea7 	bl	8001318 <FusionVectorDotProduct>
 80025ca:	eef0 7a40 	vmov.f32	s15, s0
 80025ce:	eef5 7ac0 	vcmpe.f32	s15, #0.0
 80025d2:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 80025d6:	d540      	bpl.n	800265a <Feedback+0xfa>
        return FusionVectorNormalise(FusionVectorCrossProduct(sensor, reference));
 80025d8:	ed97 5a04 	vldr	s10, [r7, #16]
 80025dc:	edd7 5a05 	vldr	s11, [r7, #20]
 80025e0:	ed97 6a06 	vldr	s12, [r7, #24]
 80025e4:	edd7 6a07 	vldr	s13, [r7, #28]
 80025e8:	ed97 7a08 	vldr	s14, [r7, #32]
 80025ec:	edd7 7a09 	vldr	s15, [r7, #36]	@ 0x24
 80025f0:	eef0 1a45 	vmov.f32	s3, s10
 80025f4:	eeb0 2a65 	vmov.f32	s4, s11
 80025f8:	eef0 2a46 	vmov.f32	s5, s12
 80025fc:	eeb0 0a66 	vmov.f32	s0, s13
 8002600:	eef0 0a47 	vmov.f32	s1, s14
 8002604:	eeb0 1a67 	vmov.f32	s2, s15
 8002608:	f7fe fe20 	bl	800124c <FusionVectorCrossProduct>
 800260c:	eef0 6a40 	vmov.f32	s13, s0
 8002610:	eeb0 7a60 	vmov.f32	s14, s1
 8002614:	eef0 7a41 	vmov.f32	s15, s2
 8002618:	edc7 6a0d 	vstr	s13, [r7, #52]	@ 0x34
 800261c:	ed87 7a0e 	vstr	s14, [r7, #56]	@ 0x38
 8002620:	edc7 7a0f 	vstr	s15, [r7, #60]	@ 0x3c
 8002624:	edd7 6a0d 	vldr	s13, [r7, #52]	@ 0x34
 8002628:	ed97 7a0e 	vldr	s14, [r7, #56]	@ 0x38
 800262c:	edd7 7a0f 	vldr	s15, [r7, #60]	@ 0x3c
 8002630:	eeb0 0a66 	vmov.f32	s0, s13
 8002634:	eef0 0a47 	vmov.f32	s1, s14
 8002638:	eeb0 1a67 	vmov.f32	s2, s15
 800263c:	f7fe ff36 	bl	80014ac <FusionVectorNormalise>
 8002640:	eef0 6a40 	vmov.f32	s13, s0
 8002644:	eeb0 7a60 	vmov.f32	s14, s1
 8002648:	eef0 7a41 	vmov.f32	s15, s2
 800264c:	edc7 6a0a 	vstr	s13, [r7, #40]	@ 0x28
 8002650:	ed87 7a0b 	vstr	s14, [r7, #44]	@ 0x2c
 8002654:	edc7 7a0c 	vstr	s15, [r7, #48]	@ 0x30
 8002658:	e025      	b.n	80026a6 <Feedback+0x146>
    }
    return FusionVectorCrossProduct(sensor, reference);
 800265a:	ed97 5a04 	vldr	s10, [r7, #16]
 800265e:	edd7 5a05 	vldr	s11, [r7, #20]
 8002662:	ed97 6a06 	vldr	s12, [r7, #24]
 8002666:	edd7 6a07 	vldr	s13, [r7, #28]
 800266a:	ed97 7a08 	vldr	s14, [r7, #32]
 800266e:	edd7 7a09 	vldr	s15, [r7, #36]	@ 0x24
 8002672:	eef0 1a45 	vmov.f32	s3, s10
 8002676:	eeb0 2a65 	vmov.f32	s4, s11
 800267a:	eef0 2a46 	vmov.f32	s5, s12
 800267e:	eeb0 0a66 	vmov.f32	s0, s13
 8002682:	eef0 0a47 	vmov.f32	s1, s14
 8002686:	eeb0 1a67 	vmov.f32	s2, s15
 800268a:	f7fe fddf 	bl	800124c <FusionVectorCrossProduct>
 800268e:	eef0 6a40 	vmov.f32	s13, s0
 8002692:	eeb0 7a60 	vmov.f32	s14, s1
 8002696:	eef0 7a41 	vmov.f32	s15, s2
 800269a:	edc7 6a0a 	vstr	s13, [r7, #40]	@ 0x28
 800269e:	ed87 7a0b 	vstr	s14, [r7, #44]	@ 0x2c
 80026a2:	edc7 7a0c 	vstr	s15, [r7, #48]	@ 0x30
}
 80026a6:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
 80026a8:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 80026aa:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 80026ac:	ee06 1a90 	vmov	s13, r1
 80026b0:	ee07 2a10 	vmov	s14, r2
 80026b4:	ee07 3a90 	vmov	s15, r3
 80026b8:	eeb0 0a66 	vmov.f32	s0, s13
 80026bc:	eef0 0a47 	vmov.f32	s1, s14
 80026c0:	eeb0 1a67 	vmov.f32	s2, s15
 80026c4:	3740      	adds	r7, #64	@ 0x40
 80026c6:	46bd      	mov	sp, r7
 80026c8:	bd80      	pop	{r7, pc}

080026ca <Clamp>:
 * @param value Value.
 * @param min Minimum value.
 * @param max Maximum value.
 * @return Value limited to maximum and minimum.
 */
static inline int Clamp(const int value, const int min, const int max) {
 80026ca:	b480      	push	{r7}
 80026cc:	b085      	sub	sp, #20
 80026ce:	af00      	add	r7, sp, #0
 80026d0:	60f8      	str	r0, [r7, #12]
 80026d2:	60b9      	str	r1, [r7, #8]
 80026d4:	607a      	str	r2, [r7, #4]
    if (value < min) {
 80026d6:	68fa      	ldr	r2, [r7, #12]
 80026d8:	68bb      	ldr	r3, [r7, #8]
 80026da:	429a      	cmp	r2, r3
 80026dc:	da01      	bge.n	80026e2 <Clamp+0x18>
        return min;
 80026de:	68bb      	ldr	r3, [r7, #8]
 80026e0:	e006      	b.n	80026f0 <Clamp+0x26>
    }
    if (value > max) {
 80026e2:	68fa      	ldr	r2, [r7, #12]
 80026e4:	687b      	ldr	r3, [r7, #4]
 80026e6:	429a      	cmp	r2, r3
 80026e8:	dd01      	ble.n	80026ee <Clamp+0x24>
        return max;
 80026ea:	687b      	ldr	r3, [r7, #4]
 80026ec:	e000      	b.n	80026f0 <Clamp+0x26>
    }
    return value;
 80026ee:	68fb      	ldr	r3, [r7, #12]
}
 80026f0:	4618      	mov	r0, r3
 80026f2:	3714      	adds	r7, #20
 80026f4:	46bd      	mov	sp, r7
 80026f6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80026fa:	4770      	bx	lr

080026fc <FusionAhrsGetQuaternion>:
/**
 * @brief Returns the quaternion describing the sensor relative to the Earth.
 * @param ahrs AHRS algorithm structure.
 * @return Quaternion describing the sensor relative to the Earth.
 */
FusionQuaternion FusionAhrsGetQuaternion(const FusionAhrs *const ahrs) {
 80026fc:	b490      	push	{r4, r7}
 80026fe:	b08a      	sub	sp, #40	@ 0x28
 8002700:	af00      	add	r7, sp, #0
 8002702:	6178      	str	r0, [r7, #20]
    return ahrs->quaternion;
 8002704:	697b      	ldr	r3, [r7, #20]
 8002706:	f107 0418 	add.w	r4, r7, #24
 800270a:	3318      	adds	r3, #24
 800270c:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
 800270e:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
 8002712:	69b8      	ldr	r0, [r7, #24]
 8002714:	69f9      	ldr	r1, [r7, #28]
 8002716:	6a3a      	ldr	r2, [r7, #32]
 8002718:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800271a:	ee06 0a10 	vmov	s12, r0
 800271e:	ee06 1a90 	vmov	s13, r1
 8002722:	ee07 2a10 	vmov	s14, r2
 8002726:	ee07 3a90 	vmov	s15, r3
}
 800272a:	eeb0 0a46 	vmov.f32	s0, s12
 800272e:	eef0 0a66 	vmov.f32	s1, s13
 8002732:	eeb0 1a47 	vmov.f32	s2, s14
 8002736:	eef0 1a67 	vmov.f32	s3, s15
 800273a:	3728      	adds	r7, #40	@ 0x28
 800273c:	46bd      	mov	sp, r7
 800273e:	bc90      	pop	{r4, r7}
 8002740:	4770      	bx	lr
	...

08002744 <FusionAhrsGetInternalStates>:
/**
 * @brief Returns the AHRS algorithm internal states.
 * @param ahrs AHRS algorithm structure.
 * @return AHRS algorithm internal states.
 */
FusionAhrsInternalStates FusionAhrsGetInternalStates(const FusionAhrs *const ahrs) {
 8002744:	b5b0      	push	{r4, r5, r7, lr}
 8002746:	b088      	sub	sp, #32
 8002748:	af00      	add	r7, sp, #0
 800274a:	6078      	str	r0, [r7, #4]
 800274c:	6039      	str	r1, [r7, #0]
    const FusionAhrsInternalStates internalStates = {
            .accelerationError = FusionRadiansToDegrees(FusionAsin(2.0f * FusionVectorMagnitude(ahrs->halfAccelerometerFeedback))),
 800274e:	683b      	ldr	r3, [r7, #0]
 8002750:	edd3 6a11 	vldr	s13, [r3, #68]	@ 0x44
 8002754:	ed93 7a12 	vldr	s14, [r3, #72]	@ 0x48
 8002758:	edd3 7a13 	vldr	s15, [r3, #76]	@ 0x4c
 800275c:	eeb0 0a66 	vmov.f32	s0, s13
 8002760:	eef0 0a47 	vmov.f32	s1, s14
 8002764:	eeb0 1a67 	vmov.f32	s2, s15
 8002768:	f7fe fe76 	bl	8001458 <FusionVectorMagnitude>
 800276c:	eef0 7a40 	vmov.f32	s15, s0
 8002770:	ee77 7aa7 	vadd.f32	s15, s15, s15
 8002774:	eeb0 0a67 	vmov.f32	s0, s15
 8002778:	f7fe fbdc 	bl	8000f34 <FusionAsin>
 800277c:	eef0 7a40 	vmov.f32	s15, s0
 8002780:	eeb0 0a67 	vmov.f32	s0, s15
 8002784:	f7fe fbc2 	bl	8000f0c <FusionRadiansToDegrees>
 8002788:	eef0 7a40 	vmov.f32	s15, s0
    const FusionAhrsInternalStates internalStates = {
 800278c:	edc7 7a02 	vstr	s15, [r7, #8]
            .accelerometerIgnored = ahrs->accelerometerIgnored,
 8002790:	683b      	ldr	r3, [r7, #0]
 8002792:	f893 305c 	ldrb.w	r3, [r3, #92]	@ 0x5c
    const FusionAhrsInternalStates internalStates = {
 8002796:	733b      	strb	r3, [r7, #12]
            .accelerationRecoveryTrigger = ahrs->settings.recoveryTriggerPeriod == 0 ? 0.0f : (float) ahrs->accelerationRecoveryTrigger / (float) ahrs->settings.recoveryTriggerPeriod,
 8002798:	683b      	ldr	r3, [r7, #0]
 800279a:	695b      	ldr	r3, [r3, #20]
 800279c:	2b00      	cmp	r3, #0
 800279e:	d00e      	beq.n	80027be <FusionAhrsGetInternalStates+0x7a>
 80027a0:	683b      	ldr	r3, [r7, #0]
 80027a2:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 80027a4:	ee07 3a90 	vmov	s15, r3
 80027a8:	eef8 6ae7 	vcvt.f32.s32	s13, s15
 80027ac:	683b      	ldr	r3, [r7, #0]
 80027ae:	695b      	ldr	r3, [r3, #20]
 80027b0:	ee07 3a90 	vmov	s15, r3
 80027b4:	eeb8 7a67 	vcvt.f32.u32	s14, s15
 80027b8:	eec6 7a87 	vdiv.f32	s15, s13, s14
 80027bc:	e001      	b.n	80027c2 <FusionAhrsGetInternalStates+0x7e>
 80027be:	eddf 7a27 	vldr	s15, [pc, #156]	@ 800285c <FusionAhrsGetInternalStates+0x118>
    const FusionAhrsInternalStates internalStates = {
 80027c2:	edc7 7a04 	vstr	s15, [r7, #16]
            .magneticError = FusionRadiansToDegrees(FusionAsin(2.0f * FusionVectorMagnitude(ahrs->halfMagnetometerFeedback))),
 80027c6:	683b      	ldr	r3, [r7, #0]
 80027c8:	edd3 6a14 	vldr	s13, [r3, #80]	@ 0x50
 80027cc:	ed93 7a15 	vldr	s14, [r3, #84]	@ 0x54
 80027d0:	edd3 7a16 	vldr	s15, [r3, #88]	@ 0x58
 80027d4:	eeb0 0a66 	vmov.f32	s0, s13
 80027d8:	eef0 0a47 	vmov.f32	s1, s14
 80027dc:	eeb0 1a67 	vmov.f32	s2, s15
 80027e0:	f7fe fe3a 	bl	8001458 <FusionVectorMagnitude>
 80027e4:	eef0 7a40 	vmov.f32	s15, s0
 80027e8:	ee77 7aa7 	vadd.f32	s15, s15, s15
 80027ec:	eeb0 0a67 	vmov.f32	s0, s15
 80027f0:	f7fe fba0 	bl	8000f34 <FusionAsin>
 80027f4:	eef0 7a40 	vmov.f32	s15, s0
 80027f8:	eeb0 0a67 	vmov.f32	s0, s15
 80027fc:	f7fe fb86 	bl	8000f0c <FusionRadiansToDegrees>
 8002800:	eef0 7a40 	vmov.f32	s15, s0
    const FusionAhrsInternalStates internalStates = {
 8002804:	edc7 7a05 	vstr	s15, [r7, #20]
            .magnetometerIgnored = ahrs->magnetometerIgnored,
 8002808:	683b      	ldr	r3, [r7, #0]
 800280a:	f893 3068 	ldrb.w	r3, [r3, #104]	@ 0x68
    const FusionAhrsInternalStates internalStates = {
 800280e:	763b      	strb	r3, [r7, #24]
            .magneticRecoveryTrigger = ahrs->settings.recoveryTriggerPeriod == 0 ? 0.0f : (float) ahrs->magneticRecoveryTrigger / (float) ahrs->settings.recoveryTriggerPeriod,
 8002810:	683b      	ldr	r3, [r7, #0]
 8002812:	695b      	ldr	r3, [r3, #20]
 8002814:	2b00      	cmp	r3, #0
 8002816:	d00e      	beq.n	8002836 <FusionAhrsGetInternalStates+0xf2>
 8002818:	683b      	ldr	r3, [r7, #0]
 800281a:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
 800281c:	ee07 3a90 	vmov	s15, r3
 8002820:	eef8 6ae7 	vcvt.f32.s32	s13, s15
 8002824:	683b      	ldr	r3, [r7, #0]
 8002826:	695b      	ldr	r3, [r3, #20]
 8002828:	ee07 3a90 	vmov	s15, r3
 800282c:	eeb8 7a67 	vcvt.f32.u32	s14, s15
 8002830:	eec6 7a87 	vdiv.f32	s15, s13, s14
 8002834:	e001      	b.n	800283a <FusionAhrsGetInternalStates+0xf6>
 8002836:	eddf 7a09 	vldr	s15, [pc, #36]	@ 800285c <FusionAhrsGetInternalStates+0x118>
    const FusionAhrsInternalStates internalStates = {
 800283a:	edc7 7a07 	vstr	s15, [r7, #28]
    };
    return internalStates;
 800283e:	687b      	ldr	r3, [r7, #4]
 8002840:	461d      	mov	r5, r3
 8002842:	f107 0408 	add.w	r4, r7, #8
 8002846:	cc0f      	ldmia	r4!, {r0, r1, r2, r3}
 8002848:	c50f      	stmia	r5!, {r0, r1, r2, r3}
 800284a:	e894 0003 	ldmia.w	r4, {r0, r1}
 800284e:	e885 0003 	stmia.w	r5, {r0, r1}
}
 8002852:	6878      	ldr	r0, [r7, #4]
 8002854:	3720      	adds	r7, #32
 8002856:	46bd      	mov	sp, r7
 8002858:	bdb0      	pop	{r4, r5, r7, pc}
 800285a:	bf00      	nop
 800285c:	00000000 	.word	0x00000000

08002860 <FusionAhrsGetFlags>:
/**
 * @brief Returns the AHRS algorithm flags.
 * @param ahrs AHRS algorithm structure.
 * @return AHRS algorithm flags.
 */
FusionAhrsFlags FusionAhrsGetFlags(const FusionAhrs *const ahrs) {
 8002860:	b480      	push	{r7}
 8002862:	b085      	sub	sp, #20
 8002864:	af00      	add	r7, sp, #0
 8002866:	6078      	str	r0, [r7, #4]
    const FusionAhrsFlags flags = {
            .initialising = ahrs->initialising,
 8002868:	687b      	ldr	r3, [r7, #4]
 800286a:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
    const FusionAhrsFlags flags = {
 800286e:	723b      	strb	r3, [r7, #8]
            .angularRateRecovery = ahrs->angularRateRecovery,
 8002870:	687b      	ldr	r3, [r7, #4]
 8002872:	f893 3040 	ldrb.w	r3, [r3, #64]	@ 0x40
    const FusionAhrsFlags flags = {
 8002876:	727b      	strb	r3, [r7, #9]
            .accelerationRecovery = ahrs->accelerationRecoveryTrigger > ahrs->accelerationRecoveryTimeout,
 8002878:	687b      	ldr	r3, [r7, #4]
 800287a:	6e1a      	ldr	r2, [r3, #96]	@ 0x60
 800287c:	687b      	ldr	r3, [r7, #4]
 800287e:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 8002880:	429a      	cmp	r2, r3
 8002882:	bfcc      	ite	gt
 8002884:	2301      	movgt	r3, #1
 8002886:	2300      	movle	r3, #0
 8002888:	b2db      	uxtb	r3, r3
    const FusionAhrsFlags flags = {
 800288a:	72bb      	strb	r3, [r7, #10]
            .magneticRecovery= ahrs->magneticRecoveryTrigger > ahrs->magneticRecoveryTimeout,
 800288c:	687b      	ldr	r3, [r7, #4]
 800288e:	6eda      	ldr	r2, [r3, #108]	@ 0x6c
 8002890:	687b      	ldr	r3, [r7, #4]
 8002892:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
 8002894:	429a      	cmp	r2, r3
 8002896:	bfcc      	ite	gt
 8002898:	2301      	movgt	r3, #1
 800289a:	2300      	movle	r3, #0
 800289c:	b2db      	uxtb	r3, r3
    const FusionAhrsFlags flags = {
 800289e:	72fb      	strb	r3, [r7, #11]
    };
    return flags;
 80028a0:	68bb      	ldr	r3, [r7, #8]
 80028a2:	60fb      	str	r3, [r7, #12]
 80028a4:	2300      	movs	r3, #0
 80028a6:	7b3a      	ldrb	r2, [r7, #12]
 80028a8:	f362 0307 	bfi	r3, r2, #0, #8
 80028ac:	7b7a      	ldrb	r2, [r7, #13]
 80028ae:	f362 230f 	bfi	r3, r2, #8, #8
 80028b2:	7bba      	ldrb	r2, [r7, #14]
 80028b4:	f362 4317 	bfi	r3, r2, #16, #8
 80028b8:	7bfa      	ldrb	r2, [r7, #15]
 80028ba:	f362 631f 	bfi	r3, r2, #24, #8
}
 80028be:	4618      	mov	r0, r3
 80028c0:	3714      	adds	r7, #20
 80028c2:	46bd      	mov	sp, r7
 80028c4:	f85d 7b04 	ldr.w	r7, [sp], #4
 80028c8:	4770      	bx	lr
	...

080028cc <write_register>:
    uint8_t val;
    HAL_I2C_Mem_Read(&hi2c1, ICM20948_ADDR, reg, 1, &val, 1, HAL_MAX_DELAY);
    return val;
}

void write_register(uint8_t reg, uint8_t val) {
 80028cc:	b580      	push	{r7, lr}
 80028ce:	b086      	sub	sp, #24
 80028d0:	af04      	add	r7, sp, #16
 80028d2:	4603      	mov	r3, r0
 80028d4:	460a      	mov	r2, r1
 80028d6:	71fb      	strb	r3, [r7, #7]
 80028d8:	4613      	mov	r3, r2
 80028da:	71bb      	strb	r3, [r7, #6]
    HAL_I2C_Mem_Write(&hi2c1, ICM20948_ADDR, reg, 1, &val, 1, HAL_MAX_DELAY);
 80028dc:	79fb      	ldrb	r3, [r7, #7]
 80028de:	b29a      	uxth	r2, r3
 80028e0:	f04f 33ff 	mov.w	r3, #4294967295
 80028e4:	9302      	str	r3, [sp, #8]
 80028e6:	2301      	movs	r3, #1
 80028e8:	9301      	str	r3, [sp, #4]
 80028ea:	1dbb      	adds	r3, r7, #6
 80028ec:	9300      	str	r3, [sp, #0]
 80028ee:	2301      	movs	r3, #1
 80028f0:	21d2      	movs	r1, #210	@ 0xd2
 80028f2:	4803      	ldr	r0, [pc, #12]	@ (8002900 <write_register+0x34>)
 80028f4:	f002 f86e 	bl	80049d4 <HAL_I2C_Mem_Write>
}
 80028f8:	bf00      	nop
 80028fa:	3708      	adds	r7, #8
 80028fc:	46bd      	mov	sp, r7
 80028fe:	bd80      	pop	{r7, pc}
 8002900:	200001f0 	.word	0x200001f0

08002904 <icm20948_select_bank>:

void icm20948_select_bank(uint8_t bank) {
 8002904:	b580      	push	{r7, lr}
 8002906:	b082      	sub	sp, #8
 8002908:	af00      	add	r7, sp, #0
 800290a:	4603      	mov	r3, r0
 800290c:	71fb      	strb	r3, [r7, #7]
    write_register(0x7F, bank << 4);  // REG_BANK_SEL (0x7F)
 800290e:	79fb      	ldrb	r3, [r7, #7]
 8002910:	011b      	lsls	r3, r3, #4
 8002912:	b2db      	uxtb	r3, r3
 8002914:	4619      	mov	r1, r3
 8002916:	207f      	movs	r0, #127	@ 0x7f
 8002918:	f7ff ffd8 	bl	80028cc <write_register>
}
 800291c:	bf00      	nop
 800291e:	3708      	adds	r7, #8
 8002920:	46bd      	mov	sp, r7
 8002922:	bd80      	pop	{r7, pc}

08002924 <icm20948_init>:

void icm20948_init(void) {
 8002924:	b580      	push	{r7, lr}
 8002926:	af00      	add	r7, sp, #0
    icm20948_select_bank(0);           // BANK 0
 8002928:	2000      	movs	r0, #0
 800292a:	f7ff ffeb 	bl	8002904 <icm20948_select_bank>
    write_register(0x06, 0x01);        // PWR_MGMT_1: reset
 800292e:	2101      	movs	r1, #1
 8002930:	2006      	movs	r0, #6
 8002932:	f7ff ffcb 	bl	80028cc <write_register>
    HAL_Delay(10);
 8002936:	200a      	movs	r0, #10
 8002938:	f001 fbfc 	bl	8004134 <HAL_Delay>
    write_register(0x06, 0x01);        // Clock source auto
 800293c:	2101      	movs	r1, #1
 800293e:	2006      	movs	r0, #6
 8002940:	f7ff ffc4 	bl	80028cc <write_register>

    icm20948_select_bank(2);           // BANK 2
 8002944:	2002      	movs	r0, #2
 8002946:	f7ff ffdd 	bl	8002904 <icm20948_select_bank>
   // write_register(0x14, 0x00);        // ACCEL_CONFIG: ±2g
    write_register(0x14, 0x04);  // ACCEL_CONFIG : ±8g (bits 2:1 = 10)
 800294a:	2104      	movs	r1, #4
 800294c:	2014      	movs	r0, #20
 800294e:	f7ff ffbd 	bl	80028cc <write_register>

    icm20948_select_bank(0);           // Revenir en BANK 0 pour lecture
 8002952:	2000      	movs	r0, #0
 8002954:	f7ff ffd6 	bl	8002904 <icm20948_select_bank>
}
 8002958:	bf00      	nop
 800295a:	bd80      	pop	{r7, pc}

0800295c <icm20948_read_accel>:

void icm20948_read_accel(float *ax, float *ay, float *az) {
 800295c:	b580      	push	{r7, lr}
 800295e:	b08c      	sub	sp, #48	@ 0x30
 8002960:	af04      	add	r7, sp, #16
 8002962:	60f8      	str	r0, [r7, #12]
 8002964:	60b9      	str	r1, [r7, #8]
 8002966:	607a      	str	r2, [r7, #4]
    uint8_t data[6];
    HAL_I2C_Mem_Read(&hi2c1, ICM20948_ADDR, 0x2D, 1, data, 6, HAL_MAX_DELAY);
 8002968:	f04f 33ff 	mov.w	r3, #4294967295
 800296c:	9302      	str	r3, [sp, #8]
 800296e:	2306      	movs	r3, #6
 8002970:	9301      	str	r3, [sp, #4]
 8002972:	f107 0314 	add.w	r3, r7, #20
 8002976:	9300      	str	r3, [sp, #0]
 8002978:	2301      	movs	r3, #1
 800297a:	222d      	movs	r2, #45	@ 0x2d
 800297c:	21d2      	movs	r1, #210	@ 0xd2
 800297e:	4823      	ldr	r0, [pc, #140]	@ (8002a0c <icm20948_read_accel+0xb0>)
 8002980:	f002 f93c 	bl	8004bfc <HAL_I2C_Mem_Read>
    int16_t x = (data[0] << 8) | data[1];
 8002984:	7d3b      	ldrb	r3, [r7, #20]
 8002986:	b21b      	sxth	r3, r3
 8002988:	021b      	lsls	r3, r3, #8
 800298a:	b21a      	sxth	r2, r3
 800298c:	7d7b      	ldrb	r3, [r7, #21]
 800298e:	b21b      	sxth	r3, r3
 8002990:	4313      	orrs	r3, r2
 8002992:	83fb      	strh	r3, [r7, #30]
    int16_t y = (data[2] << 8) | data[3];
 8002994:	7dbb      	ldrb	r3, [r7, #22]
 8002996:	b21b      	sxth	r3, r3
 8002998:	021b      	lsls	r3, r3, #8
 800299a:	b21a      	sxth	r2, r3
 800299c:	7dfb      	ldrb	r3, [r7, #23]
 800299e:	b21b      	sxth	r3, r3
 80029a0:	4313      	orrs	r3, r2
 80029a2:	83bb      	strh	r3, [r7, #28]
    int16_t z = (data[4] << 8) | data[5];
 80029a4:	7e3b      	ldrb	r3, [r7, #24]
 80029a6:	b21b      	sxth	r3, r3
 80029a8:	021b      	lsls	r3, r3, #8
 80029aa:	b21a      	sxth	r2, r3
 80029ac:	7e7b      	ldrb	r3, [r7, #25]
 80029ae:	b21b      	sxth	r3, r3
 80029b0:	4313      	orrs	r3, r2
 80029b2:	837b      	strh	r3, [r7, #26]
    //*ax = (float)x / 16384.0f;
    //*ay = (float)y / 16384.0f;
    //*az = (float)z / 16384.0f;
    *ax = (float)x / 4096.0f;
 80029b4:	f9b7 301e 	ldrsh.w	r3, [r7, #30]
 80029b8:	ee07 3a90 	vmov	s15, r3
 80029bc:	eeb8 7ae7 	vcvt.f32.s32	s14, s15
 80029c0:	eddf 6a13 	vldr	s13, [pc, #76]	@ 8002a10 <icm20948_read_accel+0xb4>
 80029c4:	eec7 7a26 	vdiv.f32	s15, s14, s13
 80029c8:	68fb      	ldr	r3, [r7, #12]
 80029ca:	edc3 7a00 	vstr	s15, [r3]
    *ay = (float)y / 4096.0f;
 80029ce:	f9b7 301c 	ldrsh.w	r3, [r7, #28]
 80029d2:	ee07 3a90 	vmov	s15, r3
 80029d6:	eeb8 7ae7 	vcvt.f32.s32	s14, s15
 80029da:	eddf 6a0d 	vldr	s13, [pc, #52]	@ 8002a10 <icm20948_read_accel+0xb4>
 80029de:	eec7 7a26 	vdiv.f32	s15, s14, s13
 80029e2:	68bb      	ldr	r3, [r7, #8]
 80029e4:	edc3 7a00 	vstr	s15, [r3]
    *az = (float)z / 4096.0f;
 80029e8:	f9b7 301a 	ldrsh.w	r3, [r7, #26]
 80029ec:	ee07 3a90 	vmov	s15, r3
 80029f0:	eeb8 7ae7 	vcvt.f32.s32	s14, s15
 80029f4:	eddf 6a06 	vldr	s13, [pc, #24]	@ 8002a10 <icm20948_read_accel+0xb4>
 80029f8:	eec7 7a26 	vdiv.f32	s15, s14, s13
 80029fc:	687b      	ldr	r3, [r7, #4]
 80029fe:	edc3 7a00 	vstr	s15, [r3]

}
 8002a02:	bf00      	nop
 8002a04:	3720      	adds	r7, #32
 8002a06:	46bd      	mov	sp, r7
 8002a08:	bd80      	pop	{r7, pc}
 8002a0a:	bf00      	nop
 8002a0c:	200001f0 	.word	0x200001f0
 8002a10:	45800000 	.word	0x45800000

08002a14 <icm20948_read_gyro>:

void icm20948_read_gyro(float *gx, float *gy, float *gz) {
 8002a14:	b580      	push	{r7, lr}
 8002a16:	b08c      	sub	sp, #48	@ 0x30
 8002a18:	af04      	add	r7, sp, #16
 8002a1a:	60f8      	str	r0, [r7, #12]
 8002a1c:	60b9      	str	r1, [r7, #8]
 8002a1e:	607a      	str	r2, [r7, #4]
    uint8_t data[6];
    icm20948_select_bank(0);
 8002a20:	2000      	movs	r0, #0
 8002a22:	f7ff ff6f 	bl	8002904 <icm20948_select_bank>
    HAL_I2C_Mem_Read(&hi2c1, ICM20948_ADDR, 0x33, 1, data, 6, HAL_MAX_DELAY);
 8002a26:	f04f 33ff 	mov.w	r3, #4294967295
 8002a2a:	9302      	str	r3, [sp, #8]
 8002a2c:	2306      	movs	r3, #6
 8002a2e:	9301      	str	r3, [sp, #4]
 8002a30:	f107 0314 	add.w	r3, r7, #20
 8002a34:	9300      	str	r3, [sp, #0]
 8002a36:	2301      	movs	r3, #1
 8002a38:	2233      	movs	r2, #51	@ 0x33
 8002a3a:	21d2      	movs	r1, #210	@ 0xd2
 8002a3c:	4822      	ldr	r0, [pc, #136]	@ (8002ac8 <icm20948_read_gyro+0xb4>)
 8002a3e:	f002 f8dd 	bl	8004bfc <HAL_I2C_Mem_Read>
    int16_t x = (data[0] << 8) | data[1];
 8002a42:	7d3b      	ldrb	r3, [r7, #20]
 8002a44:	b21b      	sxth	r3, r3
 8002a46:	021b      	lsls	r3, r3, #8
 8002a48:	b21a      	sxth	r2, r3
 8002a4a:	7d7b      	ldrb	r3, [r7, #21]
 8002a4c:	b21b      	sxth	r3, r3
 8002a4e:	4313      	orrs	r3, r2
 8002a50:	83fb      	strh	r3, [r7, #30]
    int16_t y = (data[2] << 8) | data[3];
 8002a52:	7dbb      	ldrb	r3, [r7, #22]
 8002a54:	b21b      	sxth	r3, r3
 8002a56:	021b      	lsls	r3, r3, #8
 8002a58:	b21a      	sxth	r2, r3
 8002a5a:	7dfb      	ldrb	r3, [r7, #23]
 8002a5c:	b21b      	sxth	r3, r3
 8002a5e:	4313      	orrs	r3, r2
 8002a60:	83bb      	strh	r3, [r7, #28]
    int16_t z = (data[4] << 8) | data[5];
 8002a62:	7e3b      	ldrb	r3, [r7, #24]
 8002a64:	b21b      	sxth	r3, r3
 8002a66:	021b      	lsls	r3, r3, #8
 8002a68:	b21a      	sxth	r2, r3
 8002a6a:	7e7b      	ldrb	r3, [r7, #25]
 8002a6c:	b21b      	sxth	r3, r3
 8002a6e:	4313      	orrs	r3, r2
 8002a70:	837b      	strh	r3, [r7, #26]
    *gx = (float)x / 131.0f; // sensibilité typique ±250 dps
 8002a72:	f9b7 301e 	ldrsh.w	r3, [r7, #30]
 8002a76:	ee07 3a90 	vmov	s15, r3
 8002a7a:	eeb8 7ae7 	vcvt.f32.s32	s14, s15
 8002a7e:	eddf 6a13 	vldr	s13, [pc, #76]	@ 8002acc <icm20948_read_gyro+0xb8>
 8002a82:	eec7 7a26 	vdiv.f32	s15, s14, s13
 8002a86:	68fb      	ldr	r3, [r7, #12]
 8002a88:	edc3 7a00 	vstr	s15, [r3]
    *gy = (float)y / 131.0f;
 8002a8c:	f9b7 301c 	ldrsh.w	r3, [r7, #28]
 8002a90:	ee07 3a90 	vmov	s15, r3
 8002a94:	eeb8 7ae7 	vcvt.f32.s32	s14, s15
 8002a98:	eddf 6a0c 	vldr	s13, [pc, #48]	@ 8002acc <icm20948_read_gyro+0xb8>
 8002a9c:	eec7 7a26 	vdiv.f32	s15, s14, s13
 8002aa0:	68bb      	ldr	r3, [r7, #8]
 8002aa2:	edc3 7a00 	vstr	s15, [r3]
    *gz = (float)z / 131.0f;
 8002aa6:	f9b7 301a 	ldrsh.w	r3, [r7, #26]
 8002aaa:	ee07 3a90 	vmov	s15, r3
 8002aae:	eeb8 7ae7 	vcvt.f32.s32	s14, s15
 8002ab2:	eddf 6a06 	vldr	s13, [pc, #24]	@ 8002acc <icm20948_read_gyro+0xb8>
 8002ab6:	eec7 7a26 	vdiv.f32	s15, s14, s13
 8002aba:	687b      	ldr	r3, [r7, #4]
 8002abc:	edc3 7a00 	vstr	s15, [r3]
}
 8002ac0:	bf00      	nop
 8002ac2:	3720      	adds	r7, #32
 8002ac4:	46bd      	mov	sp, r7
 8002ac6:	bd80      	pop	{r7, pc}
 8002ac8:	200001f0 	.word	0x200001f0
 8002acc:	43030000 	.word	0x43030000

08002ad0 <icm20948_read_mag>:
    // Exemples de setup (registres slave 0, adresse, etc.)
    // ...
    icm20948_select_bank(0);
}

void icm20948_read_mag(float *mx, float *my, float *mz) {
 8002ad0:	b580      	push	{r7, lr}
 8002ad2:	b08c      	sub	sp, #48	@ 0x30
 8002ad4:	af04      	add	r7, sp, #16
 8002ad6:	60f8      	str	r0, [r7, #12]
 8002ad8:	60b9      	str	r1, [r7, #8]
 8002ada:	607a      	str	r2, [r7, #4]
    uint8_t data[6];
    // Lecture des registres magnéto via I2C Master
    // Par défaut les données du magnétomètre sont relayées en registres USER_MAG_DATA_X/Y/Z
    // ou on doit lire via I2C Master
    // Exemple simplifié :
    HAL_I2C_Mem_Read(&hi2c1, ICM20948_ADDR, 0x31, 1, data, 6, HAL_MAX_DELAY);
 8002adc:	f04f 33ff 	mov.w	r3, #4294967295
 8002ae0:	9302      	str	r3, [sp, #8]
 8002ae2:	2306      	movs	r3, #6
 8002ae4:	9301      	str	r3, [sp, #4]
 8002ae6:	f107 0314 	add.w	r3, r7, #20
 8002aea:	9300      	str	r3, [sp, #0]
 8002aec:	2301      	movs	r3, #1
 8002aee:	2231      	movs	r2, #49	@ 0x31
 8002af0:	21d2      	movs	r1, #210	@ 0xd2
 8002af2:	4823      	ldr	r0, [pc, #140]	@ (8002b80 <icm20948_read_mag+0xb0>)
 8002af4:	f002 f882 	bl	8004bfc <HAL_I2C_Mem_Read>
    int16_t x = (data[1] << 8) | data[0]; // Attention à l’ordre des octets pour AK09916
 8002af8:	7d7b      	ldrb	r3, [r7, #21]
 8002afa:	b21b      	sxth	r3, r3
 8002afc:	021b      	lsls	r3, r3, #8
 8002afe:	b21a      	sxth	r2, r3
 8002b00:	7d3b      	ldrb	r3, [r7, #20]
 8002b02:	b21b      	sxth	r3, r3
 8002b04:	4313      	orrs	r3, r2
 8002b06:	83fb      	strh	r3, [r7, #30]
    int16_t y = (data[3] << 8) | data[2];
 8002b08:	7dfb      	ldrb	r3, [r7, #23]
 8002b0a:	b21b      	sxth	r3, r3
 8002b0c:	021b      	lsls	r3, r3, #8
 8002b0e:	b21a      	sxth	r2, r3
 8002b10:	7dbb      	ldrb	r3, [r7, #22]
 8002b12:	b21b      	sxth	r3, r3
 8002b14:	4313      	orrs	r3, r2
 8002b16:	83bb      	strh	r3, [r7, #28]
    int16_t z = (data[5] << 8) | data[4];
 8002b18:	7e7b      	ldrb	r3, [r7, #25]
 8002b1a:	b21b      	sxth	r3, r3
 8002b1c:	021b      	lsls	r3, r3, #8
 8002b1e:	b21a      	sxth	r2, r3
 8002b20:	7e3b      	ldrb	r3, [r7, #24]
 8002b22:	b21b      	sxth	r3, r3
 8002b24:	4313      	orrs	r3, r2
 8002b26:	837b      	strh	r3, [r7, #26]
    *mx = (float)x * 0.15f; // conversion en µT (selon datasheet)
 8002b28:	f9b7 301e 	ldrsh.w	r3, [r7, #30]
 8002b2c:	ee07 3a90 	vmov	s15, r3
 8002b30:	eef8 7ae7 	vcvt.f32.s32	s15, s15
 8002b34:	ed9f 7a13 	vldr	s14, [pc, #76]	@ 8002b84 <icm20948_read_mag+0xb4>
 8002b38:	ee67 7a87 	vmul.f32	s15, s15, s14
 8002b3c:	68fb      	ldr	r3, [r7, #12]
 8002b3e:	edc3 7a00 	vstr	s15, [r3]
    *my = (float)y * 0.15f;
 8002b42:	f9b7 301c 	ldrsh.w	r3, [r7, #28]
 8002b46:	ee07 3a90 	vmov	s15, r3
 8002b4a:	eef8 7ae7 	vcvt.f32.s32	s15, s15
 8002b4e:	ed9f 7a0d 	vldr	s14, [pc, #52]	@ 8002b84 <icm20948_read_mag+0xb4>
 8002b52:	ee67 7a87 	vmul.f32	s15, s15, s14
 8002b56:	68bb      	ldr	r3, [r7, #8]
 8002b58:	edc3 7a00 	vstr	s15, [r3]
    *mz = (float)z * 0.15f;
 8002b5c:	f9b7 301a 	ldrsh.w	r3, [r7, #26]
 8002b60:	ee07 3a90 	vmov	s15, r3
 8002b64:	eef8 7ae7 	vcvt.f32.s32	s15, s15
 8002b68:	ed9f 7a06 	vldr	s14, [pc, #24]	@ 8002b84 <icm20948_read_mag+0xb4>
 8002b6c:	ee67 7a87 	vmul.f32	s15, s15, s14
 8002b70:	687b      	ldr	r3, [r7, #4]
 8002b72:	edc3 7a00 	vstr	s15, [r3]
}
 8002b76:	bf00      	nop
 8002b78:	3720      	adds	r7, #32
 8002b7a:	46bd      	mov	sp, r7
 8002b7c:	bd80      	pop	{r7, pc}
 8002b7e:	bf00      	nop
 8002b80:	200001f0 	.word	0x200001f0
 8002b84:	3e19999a 	.word	0x3e19999a

08002b88 <lcd_init>:

void lcd_send_cmd(uint8_t cmd);
void lcd_send_data(uint8_t data);
void lcd_send(uint8_t data, uint8_t mode);

void lcd_init(void) {
 8002b88:	b580      	push	{r7, lr}
 8002b8a:	af00      	add	r7, sp, #0
    HAL_Delay(50);
 8002b8c:	2032      	movs	r0, #50	@ 0x32
 8002b8e:	f001 fad1 	bl	8004134 <HAL_Delay>
    lcd_send_cmd(0x33);
 8002b92:	2033      	movs	r0, #51	@ 0x33
 8002b94:	f000 f853 	bl	8002c3e <lcd_send_cmd>
    lcd_send_cmd(0x32);
 8002b98:	2032      	movs	r0, #50	@ 0x32
 8002b9a:	f000 f850 	bl	8002c3e <lcd_send_cmd>
    lcd_send_cmd(0x28);
 8002b9e:	2028      	movs	r0, #40	@ 0x28
 8002ba0:	f000 f84d 	bl	8002c3e <lcd_send_cmd>
    lcd_send_cmd(0x0C);
 8002ba4:	200c      	movs	r0, #12
 8002ba6:	f000 f84a 	bl	8002c3e <lcd_send_cmd>
    lcd_send_cmd(0x06);
 8002baa:	2006      	movs	r0, #6
 8002bac:	f000 f847 	bl	8002c3e <lcd_send_cmd>
    lcd_send_cmd(0x01);
 8002bb0:	2001      	movs	r0, #1
 8002bb2:	f000 f844 	bl	8002c3e <lcd_send_cmd>
    HAL_Delay(5);
 8002bb6:	2005      	movs	r0, #5
 8002bb8:	f001 fabc 	bl	8004134 <HAL_Delay>
}
 8002bbc:	bf00      	nop
 8002bbe:	bd80      	pop	{r7, pc}

08002bc0 <lcd_clear>:

void lcd_clear(void) {
 8002bc0:	b580      	push	{r7, lr}
 8002bc2:	af00      	add	r7, sp, #0
    lcd_send_cmd(0x01);
 8002bc4:	2001      	movs	r0, #1
 8002bc6:	f000 f83a 	bl	8002c3e <lcd_send_cmd>
    HAL_Delay(2);
 8002bca:	2002      	movs	r0, #2
 8002bcc:	f001 fab2 	bl	8004134 <HAL_Delay>
}
 8002bd0:	bf00      	nop
 8002bd2:	bd80      	pop	{r7, pc}

08002bd4 <lcd_set_cursor>:

void lcd_set_cursor(uint8_t row, uint8_t col) {
 8002bd4:	b580      	push	{r7, lr}
 8002bd6:	b084      	sub	sp, #16
 8002bd8:	af00      	add	r7, sp, #0
 8002bda:	4603      	mov	r3, r0
 8002bdc:	460a      	mov	r2, r1
 8002bde:	71fb      	strb	r3, [r7, #7]
 8002be0:	4613      	mov	r3, r2
 8002be2:	71bb      	strb	r3, [r7, #6]
    const uint8_t row_offsets[] = {0x00, 0x40, 0x14, 0x54};
 8002be4:	4b0a      	ldr	r3, [pc, #40]	@ (8002c10 <lcd_set_cursor+0x3c>)
 8002be6:	60fb      	str	r3, [r7, #12]
    lcd_send_cmd(0x80 | (col + row_offsets[row]));
 8002be8:	79fb      	ldrb	r3, [r7, #7]
 8002bea:	3310      	adds	r3, #16
 8002bec:	443b      	add	r3, r7
 8002bee:	f813 2c04 	ldrb.w	r2, [r3, #-4]
 8002bf2:	79bb      	ldrb	r3, [r7, #6]
 8002bf4:	4413      	add	r3, r2
 8002bf6:	b2db      	uxtb	r3, r3
 8002bf8:	b25b      	sxtb	r3, r3
 8002bfa:	f063 037f 	orn	r3, r3, #127	@ 0x7f
 8002bfe:	b25b      	sxtb	r3, r3
 8002c00:	b2db      	uxtb	r3, r3
 8002c02:	4618      	mov	r0, r3
 8002c04:	f000 f81b 	bl	8002c3e <lcd_send_cmd>
}
 8002c08:	bf00      	nop
 8002c0a:	3710      	adds	r7, #16
 8002c0c:	46bd      	mov	sp, r7
 8002c0e:	bd80      	pop	{r7, pc}
 8002c10:	54144000 	.word	0x54144000

08002c14 <lcd_print>:

void lcd_print(const char *str) {
 8002c14:	b580      	push	{r7, lr}
 8002c16:	b082      	sub	sp, #8
 8002c18:	af00      	add	r7, sp, #0
 8002c1a:	6078      	str	r0, [r7, #4]
    while (*str) {
 8002c1c:	e006      	b.n	8002c2c <lcd_print+0x18>
        lcd_send_data((uint8_t)(*str++));
 8002c1e:	687b      	ldr	r3, [r7, #4]
 8002c20:	1c5a      	adds	r2, r3, #1
 8002c22:	607a      	str	r2, [r7, #4]
 8002c24:	781b      	ldrb	r3, [r3, #0]
 8002c26:	4618      	mov	r0, r3
 8002c28:	f000 f817 	bl	8002c5a <lcd_send_data>
    while (*str) {
 8002c2c:	687b      	ldr	r3, [r7, #4]
 8002c2e:	781b      	ldrb	r3, [r3, #0]
 8002c30:	2b00      	cmp	r3, #0
 8002c32:	d1f4      	bne.n	8002c1e <lcd_print+0xa>
    }
}
 8002c34:	bf00      	nop
 8002c36:	bf00      	nop
 8002c38:	3708      	adds	r7, #8
 8002c3a:	46bd      	mov	sp, r7
 8002c3c:	bd80      	pop	{r7, pc}

08002c3e <lcd_send_cmd>:

void lcd_send_cmd(uint8_t cmd) {
 8002c3e:	b580      	push	{r7, lr}
 8002c40:	b082      	sub	sp, #8
 8002c42:	af00      	add	r7, sp, #0
 8002c44:	4603      	mov	r3, r0
 8002c46:	71fb      	strb	r3, [r7, #7]
    lcd_send(cmd, 0);
 8002c48:	79fb      	ldrb	r3, [r7, #7]
 8002c4a:	2100      	movs	r1, #0
 8002c4c:	4618      	mov	r0, r3
 8002c4e:	f000 f813 	bl	8002c78 <lcd_send>
}
 8002c52:	bf00      	nop
 8002c54:	3708      	adds	r7, #8
 8002c56:	46bd      	mov	sp, r7
 8002c58:	bd80      	pop	{r7, pc}

08002c5a <lcd_send_data>:

void lcd_send_data(uint8_t data) {
 8002c5a:	b580      	push	{r7, lr}
 8002c5c:	b082      	sub	sp, #8
 8002c5e:	af00      	add	r7, sp, #0
 8002c60:	4603      	mov	r3, r0
 8002c62:	71fb      	strb	r3, [r7, #7]
    lcd_send(data, 1);
 8002c64:	79fb      	ldrb	r3, [r7, #7]
 8002c66:	2101      	movs	r1, #1
 8002c68:	4618      	mov	r0, r3
 8002c6a:	f000 f805 	bl	8002c78 <lcd_send>
}
 8002c6e:	bf00      	nop
 8002c70:	3708      	adds	r7, #8
 8002c72:	46bd      	mov	sp, r7
 8002c74:	bd80      	pop	{r7, pc}
	...

08002c78 <lcd_send>:

void lcd_send(uint8_t data, uint8_t mode) {
 8002c78:	b580      	push	{r7, lr}
 8002c7a:	b086      	sub	sp, #24
 8002c7c:	af02      	add	r7, sp, #8
 8002c7e:	4603      	mov	r3, r0
 8002c80:	460a      	mov	r2, r1
 8002c82:	71fb      	strb	r3, [r7, #7]
 8002c84:	4613      	mov	r3, r2
 8002c86:	71bb      	strb	r3, [r7, #6]
    uint8_t high = (data & 0xF0) | LCD_BACKLIGHT | (mode ? 0x01 : 0);
 8002c88:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8002c8c:	f023 030f 	bic.w	r3, r3, #15
 8002c90:	b25b      	sxtb	r3, r3
 8002c92:	f043 0308 	orr.w	r3, r3, #8
 8002c96:	b25a      	sxtb	r2, r3
 8002c98:	79bb      	ldrb	r3, [r7, #6]
 8002c9a:	2b00      	cmp	r3, #0
 8002c9c:	bf14      	ite	ne
 8002c9e:	2301      	movne	r3, #1
 8002ca0:	2300      	moveq	r3, #0
 8002ca2:	b2db      	uxtb	r3, r3
 8002ca4:	b25b      	sxtb	r3, r3
 8002ca6:	4313      	orrs	r3, r2
 8002ca8:	b25b      	sxtb	r3, r3
 8002caa:	73fb      	strb	r3, [r7, #15]
    uint8_t low = ((data << 4) & 0xF0) | LCD_BACKLIGHT | (mode ? 0x01 : 0);
 8002cac:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8002cb0:	011b      	lsls	r3, r3, #4
 8002cb2:	b25b      	sxtb	r3, r3
 8002cb4:	f043 0308 	orr.w	r3, r3, #8
 8002cb8:	b25a      	sxtb	r2, r3
 8002cba:	79bb      	ldrb	r3, [r7, #6]
 8002cbc:	2b00      	cmp	r3, #0
 8002cbe:	bf14      	ite	ne
 8002cc0:	2301      	movne	r3, #1
 8002cc2:	2300      	moveq	r3, #0
 8002cc4:	b2db      	uxtb	r3, r3
 8002cc6:	b25b      	sxtb	r3, r3
 8002cc8:	4313      	orrs	r3, r2
 8002cca:	b25b      	sxtb	r3, r3
 8002ccc:	73bb      	strb	r3, [r7, #14]

    uint8_t data_arr[4] = {
 8002cce:	7bfb      	ldrb	r3, [r7, #15]
 8002cd0:	f043 0304 	orr.w	r3, r3, #4
 8002cd4:	b2db      	uxtb	r3, r3
 8002cd6:	723b      	strb	r3, [r7, #8]
 8002cd8:	7bfb      	ldrb	r3, [r7, #15]
 8002cda:	727b      	strb	r3, [r7, #9]
 8002cdc:	7bbb      	ldrb	r3, [r7, #14]
 8002cde:	f043 0304 	orr.w	r3, r3, #4
 8002ce2:	b2db      	uxtb	r3, r3
 8002ce4:	72bb      	strb	r3, [r7, #10]
 8002ce6:	7bbb      	ldrb	r3, [r7, #14]
 8002ce8:	72fb      	strb	r3, [r7, #11]
        high | LCD_ENABLE, high,
        low | LCD_ENABLE, low
    };
    HAL_I2C_Master_Transmit(&hi2c1, LCD_ADDR, data_arr, 4, HAL_MAX_DELAY);
 8002cea:	f107 0208 	add.w	r2, r7, #8
 8002cee:	f04f 33ff 	mov.w	r3, #4294967295
 8002cf2:	9300      	str	r3, [sp, #0]
 8002cf4:	2304      	movs	r3, #4
 8002cf6:	214e      	movs	r1, #78	@ 0x4e
 8002cf8:	4803      	ldr	r0, [pc, #12]	@ (8002d08 <lcd_send+0x90>)
 8002cfa:	f001 fd53 	bl	80047a4 <HAL_I2C_Master_Transmit>
 8002cfe:	bf00      	nop
 8002d00:	3710      	adds	r7, #16
 8002d02:	46bd      	mov	sp, r7
 8002d04:	bd80      	pop	{r7, pc}
 8002d06:	bf00      	nop
 8002d08:	200001f0 	.word	0x200001f0

08002d0c <FusionRadiansToDegrees>:
static inline float FusionRadiansToDegrees(const float radians) {
 8002d0c:	b480      	push	{r7}
 8002d0e:	b083      	sub	sp, #12
 8002d10:	af00      	add	r7, sp, #0
 8002d12:	ed87 0a01 	vstr	s0, [r7, #4]
    return radians * (180.0f / (float) M_PI);
 8002d16:	edd7 7a01 	vldr	s15, [r7, #4]
 8002d1a:	ed9f 7a05 	vldr	s14, [pc, #20]	@ 8002d30 <FusionRadiansToDegrees+0x24>
 8002d1e:	ee67 7a87 	vmul.f32	s15, s15, s14
}
 8002d22:	eeb0 0a67 	vmov.f32	s0, s15
 8002d26:	370c      	adds	r7, #12
 8002d28:	46bd      	mov	sp, r7
 8002d2a:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002d2e:	4770      	bx	lr
 8002d30:	42652ee0 	.word	0x42652ee0

08002d34 <FusionAsin>:
static inline float FusionAsin(const float value) {
 8002d34:	b580      	push	{r7, lr}
 8002d36:	b082      	sub	sp, #8
 8002d38:	af00      	add	r7, sp, #0
 8002d3a:	ed87 0a01 	vstr	s0, [r7, #4]
    if (value <= -1.0f) {
 8002d3e:	edd7 7a01 	vldr	s15, [r7, #4]
 8002d42:	eebf 7a00 	vmov.f32	s14, #240	@ 0xbf800000 -1.0
 8002d46:	eef4 7ac7 	vcmpe.f32	s15, s14
 8002d4a:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8002d4e:	d802      	bhi.n	8002d56 <FusionAsin+0x22>
        return (float) M_PI / -2.0f;
 8002d50:	eddf 7a0c 	vldr	s15, [pc, #48]	@ 8002d84 <FusionAsin+0x50>
 8002d54:	e011      	b.n	8002d7a <FusionAsin+0x46>
    if (value >= 1.0f) {
 8002d56:	edd7 7a01 	vldr	s15, [r7, #4]
 8002d5a:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 8002d5e:	eef4 7ac7 	vcmpe.f32	s15, s14
 8002d62:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8002d66:	db02      	blt.n	8002d6e <FusionAsin+0x3a>
        return (float) M_PI / 2.0f;
 8002d68:	eddf 7a07 	vldr	s15, [pc, #28]	@ 8002d88 <FusionAsin+0x54>
 8002d6c:	e005      	b.n	8002d7a <FusionAsin+0x46>
    return asinf(value);
 8002d6e:	ed97 0a01 	vldr	s0, [r7, #4]
 8002d72:	f007 f99b 	bl	800a0ac <asinf>
 8002d76:	eef0 7a40 	vmov.f32	s15, s0
}
 8002d7a:	eeb0 0a67 	vmov.f32	s0, s15
 8002d7e:	3708      	adds	r7, #8
 8002d80:	46bd      	mov	sp, r7
 8002d82:	bd80      	pop	{r7, pc}
 8002d84:	bfc90fdb 	.word	0xbfc90fdb
 8002d88:	3fc90fdb 	.word	0x3fc90fdb

08002d8c <FusionQuaternionToEuler>:
/**
 * @brief Converts a quaternion to ZYX Euler angles in degrees.
 * @param quaternion Quaternion.
 * @return Euler angles in degrees.
 */
static inline FusionEuler FusionQuaternionToEuler(const FusionQuaternion quaternion) {
 8002d8c:	b580      	push	{r7, lr}
 8002d8e:	b090      	sub	sp, #64	@ 0x40
 8002d90:	af00      	add	r7, sp, #0
 8002d92:	eeb0 6a40 	vmov.f32	s12, s0
 8002d96:	eef0 6a60 	vmov.f32	s13, s1
 8002d9a:	eeb0 7a41 	vmov.f32	s14, s2
 8002d9e:	eef0 7a61 	vmov.f32	s15, s3
 8002da2:	ed87 6a04 	vstr	s12, [r7, #16]
 8002da6:	edc7 6a05 	vstr	s13, [r7, #20]
 8002daa:	ed87 7a06 	vstr	s14, [r7, #24]
 8002dae:	edc7 7a07 	vstr	s15, [r7, #28]
#define Q quaternion.element
    const float halfMinusQySquared = 0.5f - Q.y * Q.y; // calculate common terms to avoid repeated operations
 8002db2:	ed97 7a06 	vldr	s14, [r7, #24]
 8002db6:	edd7 7a06 	vldr	s15, [r7, #24]
 8002dba:	ee67 7a27 	vmul.f32	s15, s14, s15
 8002dbe:	eeb6 7a00 	vmov.f32	s14, #96	@ 0x3f000000  0.5
 8002dc2:	ee77 7a67 	vsub.f32	s15, s14, s15
 8002dc6:	edc7 7a0f 	vstr	s15, [r7, #60]	@ 0x3c
    const FusionEuler euler = {.angle = {
            .roll = FusionRadiansToDegrees(atan2f(Q.w * Q.x + Q.y * Q.z, halfMinusQySquared - Q.x * Q.x)),
 8002dca:	ed97 7a04 	vldr	s14, [r7, #16]
 8002dce:	edd7 7a05 	vldr	s15, [r7, #20]
 8002dd2:	ee27 7a27 	vmul.f32	s14, s14, s15
 8002dd6:	edd7 6a06 	vldr	s13, [r7, #24]
 8002dda:	edd7 7a07 	vldr	s15, [r7, #28]
 8002dde:	ee66 7aa7 	vmul.f32	s15, s13, s15
 8002de2:	ee77 6a27 	vadd.f32	s13, s14, s15
 8002de6:	ed97 7a05 	vldr	s14, [r7, #20]
 8002dea:	edd7 7a05 	vldr	s15, [r7, #20]
 8002dee:	ee67 7a27 	vmul.f32	s15, s14, s15
 8002df2:	ed97 7a0f 	vldr	s14, [r7, #60]	@ 0x3c
 8002df6:	ee77 7a67 	vsub.f32	s15, s14, s15
 8002dfa:	eef0 0a67 	vmov.f32	s1, s15
 8002dfe:	eeb0 0a66 	vmov.f32	s0, s13
 8002e02:	f007 f97f 	bl	800a104 <atan2f>
 8002e06:	eef0 7a40 	vmov.f32	s15, s0
 8002e0a:	eeb0 0a67 	vmov.f32	s0, s15
 8002e0e:	f7ff ff7d 	bl	8002d0c <FusionRadiansToDegrees>
 8002e12:	eef0 7a40 	vmov.f32	s15, s0
    const FusionEuler euler = {.angle = {
 8002e16:	edc7 7a09 	vstr	s15, [r7, #36]	@ 0x24
            .pitch = FusionRadiansToDegrees(FusionAsin(2.0f * (Q.w * Q.y - Q.z * Q.x))),
 8002e1a:	ed97 7a04 	vldr	s14, [r7, #16]
 8002e1e:	edd7 7a06 	vldr	s15, [r7, #24]
 8002e22:	ee27 7a27 	vmul.f32	s14, s14, s15
 8002e26:	edd7 6a07 	vldr	s13, [r7, #28]
 8002e2a:	edd7 7a05 	vldr	s15, [r7, #20]
 8002e2e:	ee66 7aa7 	vmul.f32	s15, s13, s15
 8002e32:	ee77 7a67 	vsub.f32	s15, s14, s15
 8002e36:	ee77 7aa7 	vadd.f32	s15, s15, s15
 8002e3a:	eeb0 0a67 	vmov.f32	s0, s15
 8002e3e:	f7ff ff79 	bl	8002d34 <FusionAsin>
 8002e42:	eef0 7a40 	vmov.f32	s15, s0
 8002e46:	eeb0 0a67 	vmov.f32	s0, s15
 8002e4a:	f7ff ff5f 	bl	8002d0c <FusionRadiansToDegrees>
 8002e4e:	eef0 7a40 	vmov.f32	s15, s0
    const FusionEuler euler = {.angle = {
 8002e52:	edc7 7a0a 	vstr	s15, [r7, #40]	@ 0x28
            .yaw = FusionRadiansToDegrees(atan2f(Q.w * Q.z + Q.x * Q.y, halfMinusQySquared - Q.z * Q.z)),
 8002e56:	ed97 7a04 	vldr	s14, [r7, #16]
 8002e5a:	edd7 7a07 	vldr	s15, [r7, #28]
 8002e5e:	ee27 7a27 	vmul.f32	s14, s14, s15
 8002e62:	edd7 6a05 	vldr	s13, [r7, #20]
 8002e66:	edd7 7a06 	vldr	s15, [r7, #24]
 8002e6a:	ee66 7aa7 	vmul.f32	s15, s13, s15
 8002e6e:	ee77 6a27 	vadd.f32	s13, s14, s15
 8002e72:	ed97 7a07 	vldr	s14, [r7, #28]
 8002e76:	edd7 7a07 	vldr	s15, [r7, #28]
 8002e7a:	ee67 7a27 	vmul.f32	s15, s14, s15
 8002e7e:	ed97 7a0f 	vldr	s14, [r7, #60]	@ 0x3c
 8002e82:	ee77 7a67 	vsub.f32	s15, s14, s15
 8002e86:	eef0 0a67 	vmov.f32	s1, s15
 8002e8a:	eeb0 0a66 	vmov.f32	s0, s13
 8002e8e:	f007 f939 	bl	800a104 <atan2f>
 8002e92:	eef0 7a40 	vmov.f32	s15, s0
 8002e96:	eeb0 0a67 	vmov.f32	s0, s15
 8002e9a:	f7ff ff37 	bl	8002d0c <FusionRadiansToDegrees>
 8002e9e:	eef0 7a40 	vmov.f32	s15, s0
    const FusionEuler euler = {.angle = {
 8002ea2:	edc7 7a0b 	vstr	s15, [r7, #44]	@ 0x2c
    }};
    return euler;
 8002ea6:	f107 0330 	add.w	r3, r7, #48	@ 0x30
 8002eaa:	f107 0224 	add.w	r2, r7, #36	@ 0x24
 8002eae:	ca07      	ldmia	r2, {r0, r1, r2}
 8002eb0:	e883 0007 	stmia.w	r3, {r0, r1, r2}
 8002eb4:	6b39      	ldr	r1, [r7, #48]	@ 0x30
 8002eb6:	6b7a      	ldr	r2, [r7, #52]	@ 0x34
 8002eb8:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8002eba:	ee06 1a90 	vmov	s13, r1
 8002ebe:	ee07 2a10 	vmov	s14, r2
 8002ec2:	ee07 3a90 	vmov	s15, r3
#undef Q
}
 8002ec6:	eeb0 0a66 	vmov.f32	s0, s13
 8002eca:	eef0 0a47 	vmov.f32	s1, s14
 8002ece:	eeb0 1a67 	vmov.f32	s2, s15
 8002ed2:	3740      	adds	r7, #64	@ 0x40
 8002ed4:	46bd      	mov	sp, r7
 8002ed6:	bd80      	pop	{r7, pc}

08002ed8 <__io_putchar>:
void SystemClock_Config(void);
static void MX_GPIO_Init(void);
static void MX_I2C1_Init(void);
static void MX_USART2_UART_Init(void);

int __io_putchar(int ch) {
 8002ed8:	b580      	push	{r7, lr}
 8002eda:	b082      	sub	sp, #8
 8002edc:	af00      	add	r7, sp, #0
 8002ede:	6078      	str	r0, [r7, #4]
    HAL_UART_Transmit(&huart2, (uint8_t *)&ch, 1, HAL_MAX_DELAY);
 8002ee0:	1d39      	adds	r1, r7, #4
 8002ee2:	f04f 33ff 	mov.w	r3, #4294967295
 8002ee6:	2201      	movs	r2, #1
 8002ee8:	4803      	ldr	r0, [pc, #12]	@ (8002ef8 <__io_putchar+0x20>)
 8002eea:	f003 fd43 	bl	8006974 <HAL_UART_Transmit>
    return ch;
 8002eee:	687b      	ldr	r3, [r7, #4]
}
 8002ef0:	4618      	mov	r0, r3
 8002ef2:	3708      	adds	r7, #8
 8002ef4:	46bd      	mov	sp, r7
 8002ef6:	bd80      	pop	{r7, pc}
 8002ef8:	20000244 	.word	0x20000244

08002efc <main>:

// Variables pour le filtrage du magnétomètre
float mx_filtered = 0.0f, my_filtered = 0.0f, mz_filtered = 0.0f;

int main(void) {
 8002efc:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8002f00:	b0c9      	sub	sp, #292	@ 0x124
 8002f02:	af0e      	add	r7, sp, #56	@ 0x38
    HAL_Init();
 8002f04:	f001 f89a 	bl	800403c <HAL_Init>
    SystemClock_Config();
 8002f08:	f000 fa5c 	bl	80033c4 <SystemClock_Config>
    MX_GPIO_Init();
 8002f0c:	f000 fb1c 	bl	8003548 <MX_GPIO_Init>
    MX_I2C1_Init();
 8002f10:	f000 faaa 	bl	8003468 <MX_I2C1_Init>
    MX_USART2_UART_Init();
 8002f14:	f000 fae8 	bl	80034e8 <MX_USART2_UART_Init>

    // Initialisation de l'écran
    lcd_init();
 8002f18:	f7ff fe36 	bl	8002b88 <lcd_init>
    lcd_clear();
 8002f1c:	f7ff fe50 	bl	8002bc0 <lcd_clear>
    lcd_set_cursor(0, 0);
 8002f20:	2100      	movs	r1, #0
 8002f22:	2000      	movs	r0, #0
 8002f24:	f7ff fe56 	bl	8002bd4 <lcd_set_cursor>
    lcd_print("MOTO IMU SYSTEM");
 8002f28:	48d5      	ldr	r0, [pc, #852]	@ (8003280 <main+0x384>)
 8002f2a:	f7ff fe73 	bl	8002c14 <lcd_print>
    HAL_Delay(1000);
 8002f2e:	f44f 707a 	mov.w	r0, #1000	@ 0x3e8
 8002f32:	f001 f8ff 	bl	8004134 <HAL_Delay>

    // Initialisation de l'IMU
	icm20948_init();
 8002f36:	f7ff fcf5 	bl	8002924 <icm20948_init>

    // Initialisation de la fusion AHRS
    FusionAhrsInitialise(&ahrs);
 8002f3a:	48d2      	ldr	r0, [pc, #840]	@ (8003284 <main+0x388>)
 8002f3c:	f7fe fc80 	bl	8001840 <FusionAhrsInitialise>

    FusionAhrsSettings settings = {
 8002f40:	4bd1      	ldr	r3, [pc, #836]	@ (8003288 <main+0x38c>)
 8002f42:	f107 049c 	add.w	r4, r7, #156	@ 0x9c
 8002f46:	461d      	mov	r5, r3
 8002f48:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
 8002f4a:	c40f      	stmia	r4!, {r0, r1, r2, r3}
 8002f4c:	e895 0003 	ldmia.w	r5, {r0, r1}
 8002f50:	e884 0003 	stmia.w	r4, {r0, r1}
        .gyroscopeRange = 2000.0f, // Range du gyroscope en dps
        .accelerationRejection = 15.0f, // Rejet modéré (vibrations moto)
        .magneticRejection = 30.0f, // Rejet élevé (interférences métalliques)
        .recoveryTriggerPeriod = (int)(2.0f / MOTO_SAMPLE_PERIOD) // 2 secondes
    };
    FusionAhrsSetSettings(&ahrs, &settings);
 8002f54:	f107 039c 	add.w	r3, r7, #156	@ 0x9c
 8002f58:	4619      	mov	r1, r3
 8002f5a:	48ca      	ldr	r0, [pc, #808]	@ (8003284 <main+0x388>)
 8002f5c:	f7fe fcf2 	bl	8001944 <FusionAhrsSetSettings>

    // Initialisation des données moto
    Moto_InitData(&moto_data);
 8002f60:	48ca      	ldr	r0, [pc, #808]	@ (800328c <main+0x390>)
 8002f62:	f000 fb81 	bl	8003668 <Moto_InitData>



    uint32_t last_time = HAL_GetTick();
 8002f66:	f001 f8d9 	bl	800411c <HAL_GetTick>
 8002f6a:	f8c7 00e4 	str.w	r0, [r7, #228]	@ 0xe4
    uint32_t init_start_time = last_time;
 8002f6e:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8002f72:	f8c7 30d8 	str.w	r3, [r7, #216]	@ 0xd8
    uint32_t display_update_counter = 0;
 8002f76:	2300      	movs	r3, #0
 8002f78:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0

    while (1) {
        uint32_t current_time = HAL_GetTick();
 8002f7c:	f001 f8ce 	bl	800411c <HAL_GetTick>
 8002f80:	f8c7 00d4 	str.w	r0, [r7, #212]	@ 0xd4
        float dt = (current_time - last_time) / 1000.0f;
 8002f84:	f8d7 20d4 	ldr.w	r2, [r7, #212]	@ 0xd4
 8002f88:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
 8002f8c:	1ad3      	subs	r3, r2, r3
 8002f8e:	ee07 3a90 	vmov	s15, r3
 8002f92:	eeb8 7a67 	vcvt.f32.u32	s14, s15
 8002f96:	eddf 6abe 	vldr	s13, [pc, #760]	@ 8003290 <main+0x394>
 8002f9a:	eec7 7a26 	vdiv.f32	s15, s14, s13
 8002f9e:	edc7 7a34 	vstr	s15, [r7, #208]	@ 0xd0

        if (dt >= MOTO_SAMPLE_PERIOD) {
 8002fa2:	edd7 7a34 	vldr	s15, [r7, #208]	@ 0xd0
 8002fa6:	ed9f 7abb 	vldr	s14, [pc, #748]	@ 8003294 <main+0x398>
 8002faa:	eef4 7ac7 	vcmpe.f32	s15, s14
 8002fae:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8002fb2:	f2c0 81f5 	blt.w	80033a0 <main+0x4a4>
            float ax, ay, az;    // Accéléromètre
            float gx, gy, gz;    // Gyroscope
            float mx, my, mz;    // Magnétomètre

            // Lecture des capteurs
            icm20948_read_accel(&ax, &ay, &az);
 8002fb6:	f107 0290 	add.w	r2, r7, #144	@ 0x90
 8002fba:	f107 0194 	add.w	r1, r7, #148	@ 0x94
 8002fbe:	f107 0398 	add.w	r3, r7, #152	@ 0x98
 8002fc2:	4618      	mov	r0, r3
 8002fc4:	f7ff fcca 	bl	800295c <icm20948_read_accel>
            icm20948_read_gyro(&gx, &gy, &gz);
 8002fc8:	f107 0284 	add.w	r2, r7, #132	@ 0x84
 8002fcc:	f107 0188 	add.w	r1, r7, #136	@ 0x88
 8002fd0:	f107 038c 	add.w	r3, r7, #140	@ 0x8c
 8002fd4:	4618      	mov	r0, r3
 8002fd6:	f7ff fd1d 	bl	8002a14 <icm20948_read_gyro>
            icm20948_read_mag(&mx, &my, &mz);
 8002fda:	f107 0278 	add.w	r2, r7, #120	@ 0x78
 8002fde:	f107 017c 	add.w	r1, r7, #124	@ 0x7c
 8002fe2:	f107 0380 	add.w	r3, r7, #128	@ 0x80
 8002fe6:	4618      	mov	r0, r3
 8002fe8:	f7ff fd72 	bl	8002ad0 <icm20948_read_mag>

            // Calibration et filtrage du magnétomètre
            Moto_CalibrateMagnetometer(&mx, &my, &mz);
 8002fec:	f107 0278 	add.w	r2, r7, #120	@ 0x78
 8002ff0:	f107 017c 	add.w	r1, r7, #124	@ 0x7c
 8002ff4:	f107 0380 	add.w	r3, r7, #128	@ 0x80
 8002ff8:	4618      	mov	r0, r3
 8002ffa:	f000 fd04 	bl	8003a06 <Moto_CalibrateMagnetometer>
            mx_filtered = MOTO_MAG_FILTER_ALPHA * mx + (1.0f - MOTO_MAG_FILTER_ALPHA) * mx_filtered;
 8002ffe:	edd7 7a20 	vldr	s15, [r7, #128]	@ 0x80
 8003002:	ed9f 7aa5 	vldr	s14, [pc, #660]	@ 8003298 <main+0x39c>
 8003006:	ee27 7a87 	vmul.f32	s14, s15, s14
 800300a:	4ba4      	ldr	r3, [pc, #656]	@ (800329c <main+0x3a0>)
 800300c:	edd3 7a00 	vldr	s15, [r3]
 8003010:	eddf 6aa3 	vldr	s13, [pc, #652]	@ 80032a0 <main+0x3a4>
 8003014:	ee67 7aa6 	vmul.f32	s15, s15, s13
 8003018:	ee77 7a27 	vadd.f32	s15, s14, s15
 800301c:	4b9f      	ldr	r3, [pc, #636]	@ (800329c <main+0x3a0>)
 800301e:	edc3 7a00 	vstr	s15, [r3]
            my_filtered = MOTO_MAG_FILTER_ALPHA * my + (1.0f - MOTO_MAG_FILTER_ALPHA) * my_filtered;
 8003022:	edd7 7a1f 	vldr	s15, [r7, #124]	@ 0x7c
 8003026:	ed9f 7a9c 	vldr	s14, [pc, #624]	@ 8003298 <main+0x39c>
 800302a:	ee27 7a87 	vmul.f32	s14, s15, s14
 800302e:	4b9d      	ldr	r3, [pc, #628]	@ (80032a4 <main+0x3a8>)
 8003030:	edd3 7a00 	vldr	s15, [r3]
 8003034:	eddf 6a9a 	vldr	s13, [pc, #616]	@ 80032a0 <main+0x3a4>
 8003038:	ee67 7aa6 	vmul.f32	s15, s15, s13
 800303c:	ee77 7a27 	vadd.f32	s15, s14, s15
 8003040:	4b98      	ldr	r3, [pc, #608]	@ (80032a4 <main+0x3a8>)
 8003042:	edc3 7a00 	vstr	s15, [r3]
            mz_filtered = MOTO_MAG_FILTER_ALPHA * mz + (1.0f - MOTO_MAG_FILTER_ALPHA) * mz_filtered;
 8003046:	edd7 7a1e 	vldr	s15, [r7, #120]	@ 0x78
 800304a:	ed9f 7a93 	vldr	s14, [pc, #588]	@ 8003298 <main+0x39c>
 800304e:	ee27 7a87 	vmul.f32	s14, s15, s14
 8003052:	4b95      	ldr	r3, [pc, #596]	@ (80032a8 <main+0x3ac>)
 8003054:	edd3 7a00 	vldr	s15, [r3]
 8003058:	eddf 6a91 	vldr	s13, [pc, #580]	@ 80032a0 <main+0x3a4>
 800305c:	ee67 7aa6 	vmul.f32	s15, s15, s13
 8003060:	ee77 7a27 	vadd.f32	s15, s14, s15
 8003064:	4b90      	ldr	r3, [pc, #576]	@ (80032a8 <main+0x3ac>)
 8003066:	edc3 7a00 	vstr	s15, [r3]

            // Préparation des données pour Fusion
            FusionVector gyroscope = {gx, gy, gz};
 800306a:	f8d7 308c 	ldr.w	r3, [r7, #140]	@ 0x8c
 800306e:	66fb      	str	r3, [r7, #108]	@ 0x6c
 8003070:	f8d7 3088 	ldr.w	r3, [r7, #136]	@ 0x88
 8003074:	673b      	str	r3, [r7, #112]	@ 0x70
 8003076:	f8d7 3084 	ldr.w	r3, [r7, #132]	@ 0x84
 800307a:	677b      	str	r3, [r7, #116]	@ 0x74
            FusionVector accelerometer = {ax, ay, az};
 800307c:	f8d7 3098 	ldr.w	r3, [r7, #152]	@ 0x98
 8003080:	663b      	str	r3, [r7, #96]	@ 0x60
 8003082:	f8d7 3094 	ldr.w	r3, [r7, #148]	@ 0x94
 8003086:	667b      	str	r3, [r7, #100]	@ 0x64
 8003088:	f8d7 3090 	ldr.w	r3, [r7, #144]	@ 0x90
 800308c:	66bb      	str	r3, [r7, #104]	@ 0x68
            FusionVector magnetometer = {mx_filtered, my_filtered, mz_filtered};
 800308e:	4b83      	ldr	r3, [pc, #524]	@ (800329c <main+0x3a0>)
 8003090:	681b      	ldr	r3, [r3, #0]
 8003092:	657b      	str	r3, [r7, #84]	@ 0x54
 8003094:	4b83      	ldr	r3, [pc, #524]	@ (80032a4 <main+0x3a8>)
 8003096:	681b      	ldr	r3, [r3, #0]
 8003098:	65bb      	str	r3, [r7, #88]	@ 0x58
 800309a:	4b83      	ldr	r3, [pc, #524]	@ (80032a8 <main+0x3ac>)
 800309c:	681b      	ldr	r3, [r3, #0]
 800309e:	65fb      	str	r3, [r7, #92]	@ 0x5c

            // Mise à jour AHRS
            FusionAhrsUpdate(&ahrs, gyroscope, accelerometer, magnetometer, dt);
 80030a0:	ed97 3a15 	vldr	s6, [r7, #84]	@ 0x54
 80030a4:	edd7 3a16 	vldr	s7, [r7, #88]	@ 0x58
 80030a8:	ed97 4a17 	vldr	s8, [r7, #92]	@ 0x5c
 80030ac:	ed97 5a18 	vldr	s10, [r7, #96]	@ 0x60
 80030b0:	edd7 5a19 	vldr	s11, [r7, #100]	@ 0x64
 80030b4:	ed97 6a1a 	vldr	s12, [r7, #104]	@ 0x68
 80030b8:	edd7 6a1b 	vldr	s13, [r7, #108]	@ 0x6c
 80030bc:	ed97 7a1c 	vldr	s14, [r7, #112]	@ 0x70
 80030c0:	edd7 7a1d 	vldr	s15, [r7, #116]	@ 0x74
 80030c4:	edd7 4a34 	vldr	s9, [r7, #208]	@ 0xd0
 80030c8:	eef0 1a45 	vmov.f32	s3, s10
 80030cc:	eeb0 2a65 	vmov.f32	s4, s11
 80030d0:	eef0 2a46 	vmov.f32	s5, s12
 80030d4:	eeb0 0a66 	vmov.f32	s0, s13
 80030d8:	eef0 0a47 	vmov.f32	s1, s14
 80030dc:	eeb0 1a67 	vmov.f32	s2, s15
 80030e0:	4868      	ldr	r0, [pc, #416]	@ (8003284 <main+0x388>)
 80030e2:	f7fe fce7 	bl	8001ab4 <FusionAhrsUpdate>

            // Récupération des angles d'Euler
            FusionEuler euler = FusionQuaternionToEuler(FusionAhrsGetQuaternion(&ahrs));
 80030e6:	4867      	ldr	r0, [pc, #412]	@ (8003284 <main+0x388>)
 80030e8:	f7ff fb08 	bl	80026fc <FusionAhrsGetQuaternion>
 80030ec:	eeb0 6a40 	vmov.f32	s12, s0
 80030f0:	eef0 6a60 	vmov.f32	s13, s1
 80030f4:	eeb0 7a41 	vmov.f32	s14, s2
 80030f8:	eef0 7a61 	vmov.f32	s15, s3
 80030fc:	ed87 6a2d 	vstr	s12, [r7, #180]	@ 0xb4
 8003100:	edc7 6a2e 	vstr	s13, [r7, #184]	@ 0xb8
 8003104:	ed87 7a2f 	vstr	s14, [r7, #188]	@ 0xbc
 8003108:	edc7 7a30 	vstr	s15, [r7, #192]	@ 0xc0
 800310c:	ed97 6a2d 	vldr	s12, [r7, #180]	@ 0xb4
 8003110:	edd7 6a2e 	vldr	s13, [r7, #184]	@ 0xb8
 8003114:	ed97 7a2f 	vldr	s14, [r7, #188]	@ 0xbc
 8003118:	edd7 7a30 	vldr	s15, [r7, #192]	@ 0xc0
 800311c:	eeb0 0a46 	vmov.f32	s0, s12
 8003120:	eef0 0a66 	vmov.f32	s1, s13
 8003124:	eeb0 1a47 	vmov.f32	s2, s14
 8003128:	eef0 1a67 	vmov.f32	s3, s15
 800312c:	f7ff fe2e 	bl	8002d8c <FusionQuaternionToEuler>
 8003130:	eef0 6a40 	vmov.f32	s13, s0
 8003134:	eeb0 7a60 	vmov.f32	s14, s1
 8003138:	eef0 7a41 	vmov.f32	s15, s2
 800313c:	edc7 6a12 	vstr	s13, [r7, #72]	@ 0x48
 8003140:	ed87 7a13 	vstr	s14, [r7, #76]	@ 0x4c
 8003144:	edc7 7a14 	vstr	s15, [r7, #80]	@ 0x50
            float roll = euler.angle.roll;
 8003148:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
 800314a:	f8c7 30cc 	str.w	r3, [r7, #204]	@ 0xcc
            float pitch = euler.angle.pitch;
 800314e:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 8003150:	f8c7 30c8 	str.w	r3, [r7, #200]	@ 0xc8
            float yaw = euler.angle.yaw;
 8003154:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 8003156:	f8c7 30c4 	str.w	r3, [r7, #196]	@ 0xc4

            // Vérification de la phase d'initialisation
            FusionAhrsFlags flags = FusionAhrsGetFlags(&ahrs);
 800315a:	484a      	ldr	r0, [pc, #296]	@ (8003284 <main+0x388>)
 800315c:	f7ff fb80 	bl	8002860 <FusionAhrsGetFlags>
 8003160:	4603      	mov	r3, r0
 8003162:	647b      	str	r3, [r7, #68]	@ 0x44
            moto_data.is_initializing = flags.initialising;
 8003164:	f897 2044 	ldrb.w	r2, [r7, #68]	@ 0x44
 8003168:	4b48      	ldr	r3, [pc, #288]	@ (800328c <main+0x390>)
 800316a:	765a      	strb	r2, [r3, #25]

            // Mise à jour de l'état de la moto
            Moto_UpdateState(&moto_data, roll, pitch, yaw, gx, gy, gz);
 800316c:	edd7 7a23 	vldr	s15, [r7, #140]	@ 0x8c
 8003170:	ed97 7a22 	vldr	s14, [r7, #136]	@ 0x88
 8003174:	edd7 6a21 	vldr	s13, [r7, #132]	@ 0x84
 8003178:	eef0 2a66 	vmov.f32	s5, s13
 800317c:	eeb0 2a47 	vmov.f32	s4, s14
 8003180:	eef0 1a67 	vmov.f32	s3, s15
 8003184:	ed97 1a31 	vldr	s2, [r7, #196]	@ 0xc4
 8003188:	edd7 0a32 	vldr	s1, [r7, #200]	@ 0xc8
 800318c:	ed97 0a33 	vldr	s0, [r7, #204]	@ 0xcc
 8003190:	483e      	ldr	r0, [pc, #248]	@ (800328c <main+0x390>)
 8003192:	f000 fa7f 	bl	8003694 <Moto_UpdateState>
            Moto_FilterAngles(&moto_data);
 8003196:	483d      	ldr	r0, [pc, #244]	@ (800328c <main+0x390>)
 8003198:	f000 fb0c 	bl	80037b4 <Moto_FilterAngles>
            Moto_UpdateStats(&moto_stats, &moto_data, gx, gy, gz);
 800319c:	edd7 7a23 	vldr	s15, [r7, #140]	@ 0x8c
 80031a0:	ed97 7a22 	vldr	s14, [r7, #136]	@ 0x88
 80031a4:	edd7 6a21 	vldr	s13, [r7, #132]	@ 0x84
 80031a8:	eeb0 1a66 	vmov.f32	s2, s13
 80031ac:	eef0 0a47 	vmov.f32	s1, s14
 80031b0:	eeb0 0a67 	vmov.f32	s0, s15
 80031b4:	4935      	ldr	r1, [pc, #212]	@ (800328c <main+0x390>)
 80031b6:	483d      	ldr	r0, [pc, #244]	@ (80032ac <main+0x3b0>)
 80031b8:	f000 fb84 	bl	80038c4 <Moto_UpdateStats>

            // Mise à jour de l'affichage (toutes les 5 itérations = ~50ms)
            display_update_counter++;
 80031bc:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 80031c0:	3301      	adds	r3, #1
 80031c2:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
            if (display_update_counter >= 5) {
 80031c6:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
 80031ca:	2b04      	cmp	r3, #4
 80031cc:	d923      	bls.n	8003216 <main+0x31a>
                char buffer[21];

                for (int line = 0; line < 4; line++) {
 80031ce:	2300      	movs	r3, #0
 80031d0:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
 80031d4:	e018      	b.n	8003208 <main+0x30c>
                    Moto_FormatDisplay(&moto_data, line, buffer);
 80031d6:	f107 032c 	add.w	r3, r7, #44	@ 0x2c
 80031da:	461a      	mov	r2, r3
 80031dc:	f8d7 10dc 	ldr.w	r1, [r7, #220]	@ 0xdc
 80031e0:	482a      	ldr	r0, [pc, #168]	@ (800328c <main+0x390>)
 80031e2:	f000 fc55 	bl	8003a90 <Moto_FormatDisplay>
                    lcd_set_cursor(line, 0);
 80031e6:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 80031ea:	b2db      	uxtb	r3, r3
 80031ec:	2100      	movs	r1, #0
 80031ee:	4618      	mov	r0, r3
 80031f0:	f7ff fcf0 	bl	8002bd4 <lcd_set_cursor>
                    lcd_print(buffer);
 80031f4:	f107 032c 	add.w	r3, r7, #44	@ 0x2c
 80031f8:	4618      	mov	r0, r3
 80031fa:	f7ff fd0b 	bl	8002c14 <lcd_print>
                for (int line = 0; line < 4; line++) {
 80031fe:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 8003202:	3301      	adds	r3, #1
 8003204:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
 8003208:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
 800320c:	2b03      	cmp	r3, #3
 800320e:	dde2      	ble.n	80031d6 <main+0x2da>
                }

                display_update_counter = 0;
 8003210:	2300      	movs	r3, #0
 8003212:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
            }

            // LED d'état
            switch (moto_data.state) {
 8003216:	4b1d      	ldr	r3, [pc, #116]	@ (800328c <main+0x390>)
 8003218:	7e1b      	ldrb	r3, [r3, #24]
 800321a:	2b06      	cmp	r3, #6
 800321c:	d864      	bhi.n	80032e8 <main+0x3ec>
 800321e:	a201      	add	r2, pc, #4	@ (adr r2, 8003224 <main+0x328>)
 8003220:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8003224:	08003241 	.word	0x08003241
 8003228:	0800324f 	.word	0x0800324f
 800322c:	080032b9 	.word	0x080032b9
 8003230:	080032e9 	.word	0x080032e9
 8003234:	080032e9 	.word	0x080032e9
 8003238:	0800324f 	.word	0x0800324f
 800323c:	080032b9 	.word	0x080032b9
                case MOTO_STATE_NORMAL:
                    HAL_GPIO_WritePin(LD4_GPIO_Port, LD4_Pin, GPIO_PIN_RESET);
 8003240:	2200      	movs	r2, #0
 8003242:	f44f 5100 	mov.w	r1, #8192	@ 0x2000
 8003246:	481a      	ldr	r0, [pc, #104]	@ (80032b0 <main+0x3b4>)
 8003248:	f001 f9f8 	bl	800463c <HAL_GPIO_WritePin>
                    break;
 800324c:	e053      	b.n	80032f6 <main+0x3fa>
                case MOTO_STATE_WARNING:
                case MOTO_STATE_RAPID_TURN:
                    // Clignotement lent
                    if ((current_time / 500) % 2) {
 800324e:	f8d7 30d4 	ldr.w	r3, [r7, #212]	@ 0xd4
 8003252:	4a18      	ldr	r2, [pc, #96]	@ (80032b4 <main+0x3b8>)
 8003254:	fba2 2303 	umull	r2, r3, r2, r3
 8003258:	095b      	lsrs	r3, r3, #5
 800325a:	f003 0301 	and.w	r3, r3, #1
 800325e:	2b00      	cmp	r3, #0
 8003260:	d006      	beq.n	8003270 <main+0x374>
                        HAL_GPIO_WritePin(LD4_GPIO_Port, LD4_Pin, GPIO_PIN_SET);
 8003262:	2201      	movs	r2, #1
 8003264:	f44f 5100 	mov.w	r1, #8192	@ 0x2000
 8003268:	4811      	ldr	r0, [pc, #68]	@ (80032b0 <main+0x3b4>)
 800326a:	f001 f9e7 	bl	800463c <HAL_GPIO_WritePin>
                    } else {
                        HAL_GPIO_WritePin(LD4_GPIO_Port, LD4_Pin, GPIO_PIN_RESET);
                    }
                    break;
 800326e:	e042      	b.n	80032f6 <main+0x3fa>
                        HAL_GPIO_WritePin(LD4_GPIO_Port, LD4_Pin, GPIO_PIN_RESET);
 8003270:	2200      	movs	r2, #0
 8003272:	f44f 5100 	mov.w	r1, #8192	@ 0x2000
 8003276:	480e      	ldr	r0, [pc, #56]	@ (80032b0 <main+0x3b4>)
 8003278:	f001 f9e0 	bl	800463c <HAL_GPIO_WritePin>
                    break;
 800327c:	e03b      	b.n	80032f6 <main+0x3fa>
 800327e:	bf00      	nop
 8003280:	0800b748 	.word	0x0800b748
 8003284:	200002cc 	.word	0x200002cc
 8003288:	0800b7a4 	.word	0x0800b7a4
 800328c:	20000340 	.word	0x20000340
 8003290:	447a0000 	.word	0x447a0000
 8003294:	3c23d70a 	.word	0x3c23d70a
 8003298:	3dcccccd 	.word	0x3dcccccd
 800329c:	2000038c 	.word	0x2000038c
 80032a0:	3f666666 	.word	0x3f666666
 80032a4:	20000390 	.word	0x20000390
 80032a8:	20000394 	.word	0x20000394
 80032ac:	20000364 	.word	0x20000364
 80032b0:	48000400 	.word	0x48000400
 80032b4:	10624dd3 	.word	0x10624dd3
                case MOTO_STATE_DANGER:
                case MOTO_STATE_POSSIBLE_CRASH:
                    // Clignotement rapide
                    if ((current_time / 100) % 2) {
 80032b8:	f8d7 30d4 	ldr.w	r3, [r7, #212]	@ 0xd4
 80032bc:	4a3a      	ldr	r2, [pc, #232]	@ (80033a8 <main+0x4ac>)
 80032be:	fba2 2303 	umull	r2, r3, r2, r3
 80032c2:	095b      	lsrs	r3, r3, #5
 80032c4:	f003 0301 	and.w	r3, r3, #1
 80032c8:	2b00      	cmp	r3, #0
 80032ca:	d006      	beq.n	80032da <main+0x3de>
                        HAL_GPIO_WritePin(LD4_GPIO_Port, LD4_Pin, GPIO_PIN_SET);
 80032cc:	2201      	movs	r2, #1
 80032ce:	f44f 5100 	mov.w	r1, #8192	@ 0x2000
 80032d2:	4836      	ldr	r0, [pc, #216]	@ (80033ac <main+0x4b0>)
 80032d4:	f001 f9b2 	bl	800463c <HAL_GPIO_WritePin>
                    } else {
                        HAL_GPIO_WritePin(LD4_GPIO_Port, LD4_Pin, GPIO_PIN_RESET);
                    }
                    break;
 80032d8:	e00d      	b.n	80032f6 <main+0x3fa>
                        HAL_GPIO_WritePin(LD4_GPIO_Port, LD4_Pin, GPIO_PIN_RESET);
 80032da:	2200      	movs	r2, #0
 80032dc:	f44f 5100 	mov.w	r1, #8192	@ 0x2000
 80032e0:	4832      	ldr	r0, [pc, #200]	@ (80033ac <main+0x4b0>)
 80032e2:	f001 f9ab 	bl	800463c <HAL_GPIO_WritePin>
                    break;
 80032e6:	e006      	b.n	80032f6 <main+0x3fa>
                default:
                    HAL_GPIO_WritePin(LD4_GPIO_Port, LD4_Pin, GPIO_PIN_SET);
 80032e8:	2201      	movs	r2, #1
 80032ea:	f44f 5100 	mov.w	r1, #8192	@ 0x2000
 80032ee:	482f      	ldr	r0, [pc, #188]	@ (80033ac <main+0x4b0>)
 80032f0:	f001 f9a4 	bl	800463c <HAL_GPIO_WritePin>
                    break;
 80032f4:	bf00      	nop
            }

            // Debug UART (toutes les 50 itérations = ~500ms)
            static uint32_t uart_counter = 0;
            uart_counter++;
 80032f6:	4b2e      	ldr	r3, [pc, #184]	@ (80033b0 <main+0x4b4>)
 80032f8:	681b      	ldr	r3, [r3, #0]
 80032fa:	3301      	adds	r3, #1
 80032fc:	4a2c      	ldr	r2, [pc, #176]	@ (80033b0 <main+0x4b4>)
 80032fe:	6013      	str	r3, [r2, #0]
            if (uart_counter >= 50) {
 8003300:	4b2b      	ldr	r3, [pc, #172]	@ (80033b0 <main+0x4b4>)
 8003302:	681b      	ldr	r3, [r3, #0]
 8003304:	2b31      	cmp	r3, #49	@ 0x31
 8003306:	d943      	bls.n	8003390 <main+0x494>
                FusionAhrsInternalStates states = FusionAhrsGetInternalStates(&ahrs);
 8003308:	f107 0314 	add.w	r3, r7, #20
 800330c:	4929      	ldr	r1, [pc, #164]	@ (80033b4 <main+0x4b8>)
 800330e:	4618      	mov	r0, r3
 8003310:	f7ff fa18 	bl	8002744 <FusionAhrsGetInternalStates>

                printf("R:%.1f P:%.1f Y:%.1f | St:%s | AE:%.1f ME:%.1f | AI:%d MI:%d | Smp:%lu\r\n",
 8003314:	f8d7 00cc 	ldr.w	r0, [r7, #204]	@ 0xcc
 8003318:	f7fd f91e 	bl	8000558 <__aeabi_f2d>
 800331c:	e9c7 0102 	strd	r0, r1, [r7, #8]
 8003320:	f8d7 00c8 	ldr.w	r0, [r7, #200]	@ 0xc8
 8003324:	f7fd f918 	bl	8000558 <__aeabi_f2d>
 8003328:	4604      	mov	r4, r0
 800332a:	460d      	mov	r5, r1
 800332c:	f8d7 00c4 	ldr.w	r0, [r7, #196]	@ 0xc4
 8003330:	f7fd f912 	bl	8000558 <__aeabi_f2d>
 8003334:	4680      	mov	r8, r0
 8003336:	4689      	mov	r9, r1
 8003338:	4b1f      	ldr	r3, [pc, #124]	@ (80033b8 <main+0x4bc>)
 800333a:	7e1b      	ldrb	r3, [r3, #24]
 800333c:	4618      	mov	r0, r3
 800333e:	f000 fa81 	bl	8003844 <Moto_GetStateString>
 8003342:	4606      	mov	r6, r0
                       roll, pitch, yaw,
                       Moto_GetStateString(moto_data.state),
                       states.accelerationError, states.magneticError,
 8003344:	697b      	ldr	r3, [r7, #20]
                printf("R:%.1f P:%.1f Y:%.1f | St:%s | AE:%.1f ME:%.1f | AI:%d MI:%d | Smp:%lu\r\n",
 8003346:	4618      	mov	r0, r3
 8003348:	f7fd f906 	bl	8000558 <__aeabi_f2d>
 800334c:	4682      	mov	sl, r0
 800334e:	468b      	mov	fp, r1
                       states.accelerationError, states.magneticError,
 8003350:	6a3b      	ldr	r3, [r7, #32]
                printf("R:%.1f P:%.1f Y:%.1f | St:%s | AE:%.1f ME:%.1f | AI:%d MI:%d | Smp:%lu\r\n",
 8003352:	4618      	mov	r0, r3
 8003354:	f7fd f900 	bl	8000558 <__aeabi_f2d>
                       states.accelerometerIgnored, states.magnetometerIgnored,
 8003358:	7e3b      	ldrb	r3, [r7, #24]
                printf("R:%.1f P:%.1f Y:%.1f | St:%s | AE:%.1f ME:%.1f | AI:%d MI:%d | Smp:%lu\r\n",
 800335a:	461a      	mov	r2, r3
                       states.accelerometerIgnored, states.magnetometerIgnored,
 800335c:	f897 3024 	ldrb.w	r3, [r7, #36]	@ 0x24
                printf("R:%.1f P:%.1f Y:%.1f | St:%s | AE:%.1f ME:%.1f | AI:%d MI:%d | Smp:%lu\r\n",
 8003360:	607b      	str	r3, [r7, #4]
 8003362:	4b16      	ldr	r3, [pc, #88]	@ (80033bc <main+0x4c0>)
 8003364:	69db      	ldr	r3, [r3, #28]
 8003366:	930c      	str	r3, [sp, #48]	@ 0x30
 8003368:	687b      	ldr	r3, [r7, #4]
 800336a:	930b      	str	r3, [sp, #44]	@ 0x2c
 800336c:	920a      	str	r2, [sp, #40]	@ 0x28
 800336e:	e9cd 0108 	strd	r0, r1, [sp, #32]
 8003372:	e9cd ab06 	strd	sl, fp, [sp, #24]
 8003376:	9604      	str	r6, [sp, #16]
 8003378:	e9cd 8902 	strd	r8, r9, [sp, #8]
 800337c:	e9cd 4500 	strd	r4, r5, [sp]
 8003380:	e9d7 2302 	ldrd	r2, r3, [r7, #8]
 8003384:	480e      	ldr	r0, [pc, #56]	@ (80033c0 <main+0x4c4>)
 8003386:	f004 fd37 	bl	8007df8 <iprintf>
                       moto_stats.total_samples);

                uart_counter = 0;
 800338a:	4b09      	ldr	r3, [pc, #36]	@ (80033b0 <main+0x4b4>)
 800338c:	2200      	movs	r2, #0
 800338e:	601a      	str	r2, [r3, #0]
            }

            // Mise à jour du timestamp
            moto_data.last_update_time = current_time;
 8003390:	4a09      	ldr	r2, [pc, #36]	@ (80033b8 <main+0x4bc>)
 8003392:	f8d7 30d4 	ldr.w	r3, [r7, #212]	@ 0xd4
 8003396:	6213      	str	r3, [r2, #32]
            last_time = current_time;
 8003398:	f8d7 30d4 	ldr.w	r3, [r7, #212]	@ 0xd4
 800339c:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
        }

        // Petite pause pour éviter la surcharge du processeur
        HAL_Delay(20);
 80033a0:	2014      	movs	r0, #20
 80033a2:	f000 fec7 	bl	8004134 <HAL_Delay>
    while (1) {
 80033a6:	e5e9      	b.n	8002f7c <main+0x80>
 80033a8:	51eb851f 	.word	0x51eb851f
 80033ac:	48000400 	.word	0x48000400
 80033b0:	20000398 	.word	0x20000398
 80033b4:	200002cc 	.word	0x200002cc
 80033b8:	20000340 	.word	0x20000340
 80033bc:	20000364 	.word	0x20000364
 80033c0:	0800b758 	.word	0x0800b758

080033c4 <SystemClock_Config>:
    }
}

void SystemClock_Config(void)
{
 80033c4:	b580      	push	{r7, lr}
 80033c6:	b096      	sub	sp, #88	@ 0x58
 80033c8:	af00      	add	r7, sp, #0
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 80033ca:	f107 0314 	add.w	r3, r7, #20
 80033ce:	2244      	movs	r2, #68	@ 0x44
 80033d0:	2100      	movs	r1, #0
 80033d2:	4618      	mov	r0, r3
 80033d4:	f004 fd9b 	bl	8007f0e <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 80033d8:	463b      	mov	r3, r7
 80033da:	2200      	movs	r2, #0
 80033dc:	601a      	str	r2, [r3, #0]
 80033de:	605a      	str	r2, [r3, #4]
 80033e0:	609a      	str	r2, [r3, #8]
 80033e2:	60da      	str	r2, [r3, #12]
 80033e4:	611a      	str	r2, [r3, #16]

  /** Configure the main internal regulator output voltage
  */
  if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
 80033e6:	f44f 7000 	mov.w	r0, #512	@ 0x200
 80033ea:	f002 f889 	bl	8005500 <HAL_PWREx_ControlVoltageScaling>
 80033ee:	4603      	mov	r3, r0
 80033f0:	2b00      	cmp	r3, #0
 80033f2:	d001      	beq.n	80033f8 <SystemClock_Config+0x34>
  {
    Error_Handler();
 80033f4:	f000 f932 	bl	800365c <Error_Handler>
  }

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 80033f8:	2302      	movs	r3, #2
 80033fa:	617b      	str	r3, [r7, #20]
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 80033fc:	f44f 7380 	mov.w	r3, #256	@ 0x100
 8003400:	623b      	str	r3, [r7, #32]
  RCC_OscInitStruct.HSICalibrationValue = 64;
 8003402:	2340      	movs	r3, #64	@ 0x40
 8003404:	627b      	str	r3, [r7, #36]	@ 0x24
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 8003406:	2302      	movs	r3, #2
 8003408:	63fb      	str	r3, [r7, #60]	@ 0x3c
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
 800340a:	2302      	movs	r3, #2
 800340c:	643b      	str	r3, [r7, #64]	@ 0x40
  RCC_OscInitStruct.PLL.PLLM = 1;
 800340e:	2301      	movs	r3, #1
 8003410:	647b      	str	r3, [r7, #68]	@ 0x44
  RCC_OscInitStruct.PLL.PLLN = 10;
 8003412:	230a      	movs	r3, #10
 8003414:	64bb      	str	r3, [r7, #72]	@ 0x48
  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
 8003416:	2307      	movs	r3, #7
 8003418:	64fb      	str	r3, [r7, #76]	@ 0x4c
  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
 800341a:	2302      	movs	r3, #2
 800341c:	653b      	str	r3, [r7, #80]	@ 0x50
  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
 800341e:	2302      	movs	r3, #2
 8003420:	657b      	str	r3, [r7, #84]	@ 0x54
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 8003422:	f107 0314 	add.w	r3, r7, #20
 8003426:	4618      	mov	r0, r3
 8003428:	f002 f8c0 	bl	80055ac <HAL_RCC_OscConfig>
 800342c:	4603      	mov	r3, r0
 800342e:	2b00      	cmp	r3, #0
 8003430:	d001      	beq.n	8003436 <SystemClock_Config+0x72>
  {
    Error_Handler();
 8003432:	f000 f913 	bl	800365c <Error_Handler>
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8003436:	230f      	movs	r3, #15
 8003438:	603b      	str	r3, [r7, #0]
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 800343a:	2303      	movs	r3, #3
 800343c:	607b      	str	r3, [r7, #4]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 800343e:	2300      	movs	r3, #0
 8003440:	60bb      	str	r3, [r7, #8]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 8003442:	2300      	movs	r3, #0
 8003444:	60fb      	str	r3, [r7, #12]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 8003446:	2300      	movs	r3, #0
 8003448:	613b      	str	r3, [r7, #16]

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
 800344a:	463b      	mov	r3, r7
 800344c:	2104      	movs	r1, #4
 800344e:	4618      	mov	r0, r3
 8003450:	f002 fcc0 	bl	8005dd4 <HAL_RCC_ClockConfig>
 8003454:	4603      	mov	r3, r0
 8003456:	2b00      	cmp	r3, #0
 8003458:	d001      	beq.n	800345e <SystemClock_Config+0x9a>
  {
    Error_Handler();
 800345a:	f000 f8ff 	bl	800365c <Error_Handler>
  }
}
 800345e:	bf00      	nop
 8003460:	3758      	adds	r7, #88	@ 0x58
 8003462:	46bd      	mov	sp, r7
 8003464:	bd80      	pop	{r7, pc}
	...

08003468 <MX_I2C1_Init>:

static void MX_I2C1_Init(void)
{
 8003468:	b580      	push	{r7, lr}
 800346a:	af00      	add	r7, sp, #0
  hi2c1.Instance = I2C1;
 800346c:	4b1b      	ldr	r3, [pc, #108]	@ (80034dc <MX_I2C1_Init+0x74>)
 800346e:	4a1c      	ldr	r2, [pc, #112]	@ (80034e0 <MX_I2C1_Init+0x78>)
 8003470:	601a      	str	r2, [r3, #0]
  hi2c1.Init.Timing = 0x10D19CE4;
 8003472:	4b1a      	ldr	r3, [pc, #104]	@ (80034dc <MX_I2C1_Init+0x74>)
 8003474:	4a1b      	ldr	r2, [pc, #108]	@ (80034e4 <MX_I2C1_Init+0x7c>)
 8003476:	605a      	str	r2, [r3, #4]
  hi2c1.Init.OwnAddress1 = 0;
 8003478:	4b18      	ldr	r3, [pc, #96]	@ (80034dc <MX_I2C1_Init+0x74>)
 800347a:	2200      	movs	r2, #0
 800347c:	609a      	str	r2, [r3, #8]
  hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
 800347e:	4b17      	ldr	r3, [pc, #92]	@ (80034dc <MX_I2C1_Init+0x74>)
 8003480:	2201      	movs	r2, #1
 8003482:	60da      	str	r2, [r3, #12]
  hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
 8003484:	4b15      	ldr	r3, [pc, #84]	@ (80034dc <MX_I2C1_Init+0x74>)
 8003486:	2200      	movs	r2, #0
 8003488:	611a      	str	r2, [r3, #16]
  hi2c1.Init.OwnAddress2 = 0;
 800348a:	4b14      	ldr	r3, [pc, #80]	@ (80034dc <MX_I2C1_Init+0x74>)
 800348c:	2200      	movs	r2, #0
 800348e:	615a      	str	r2, [r3, #20]
  hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
 8003490:	4b12      	ldr	r3, [pc, #72]	@ (80034dc <MX_I2C1_Init+0x74>)
 8003492:	2200      	movs	r2, #0
 8003494:	619a      	str	r2, [r3, #24]
  hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
 8003496:	4b11      	ldr	r3, [pc, #68]	@ (80034dc <MX_I2C1_Init+0x74>)
 8003498:	2200      	movs	r2, #0
 800349a:	61da      	str	r2, [r3, #28]
  hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
 800349c:	4b0f      	ldr	r3, [pc, #60]	@ (80034dc <MX_I2C1_Init+0x74>)
 800349e:	2200      	movs	r2, #0
 80034a0:	621a      	str	r2, [r3, #32]
  if (HAL_I2C_Init(&hi2c1) != HAL_OK)
 80034a2:	480e      	ldr	r0, [pc, #56]	@ (80034dc <MX_I2C1_Init+0x74>)
 80034a4:	f001 f8e2 	bl	800466c <HAL_I2C_Init>
 80034a8:	4603      	mov	r3, r0
 80034aa:	2b00      	cmp	r3, #0
 80034ac:	d001      	beq.n	80034b2 <MX_I2C1_Init+0x4a>
  {
    Error_Handler();
 80034ae:	f000 f8d5 	bl	800365c <Error_Handler>
  }

  if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
 80034b2:	2100      	movs	r1, #0
 80034b4:	4809      	ldr	r0, [pc, #36]	@ (80034dc <MX_I2C1_Init+0x74>)
 80034b6:	f001 ff7d 	bl	80053b4 <HAL_I2CEx_ConfigAnalogFilter>
 80034ba:	4603      	mov	r3, r0
 80034bc:	2b00      	cmp	r3, #0
 80034be:	d001      	beq.n	80034c4 <MX_I2C1_Init+0x5c>
  {
    Error_Handler();
 80034c0:	f000 f8cc 	bl	800365c <Error_Handler>
  }

  if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
 80034c4:	2100      	movs	r1, #0
 80034c6:	4805      	ldr	r0, [pc, #20]	@ (80034dc <MX_I2C1_Init+0x74>)
 80034c8:	f001 ffbf 	bl	800544a <HAL_I2CEx_ConfigDigitalFilter>
 80034cc:	4603      	mov	r3, r0
 80034ce:	2b00      	cmp	r3, #0
 80034d0:	d001      	beq.n	80034d6 <MX_I2C1_Init+0x6e>
  {
    Error_Handler();
 80034d2:	f000 f8c3 	bl	800365c <Error_Handler>
  }
}
 80034d6:	bf00      	nop
 80034d8:	bd80      	pop	{r7, pc}
 80034da:	bf00      	nop
 80034dc:	200001f0 	.word	0x200001f0
 80034e0:	40005400 	.word	0x40005400
 80034e4:	10d19ce4 	.word	0x10d19ce4

080034e8 <MX_USART2_UART_Init>:

static void MX_USART2_UART_Init(void)
{
 80034e8:	b580      	push	{r7, lr}
 80034ea:	af00      	add	r7, sp, #0
  huart2.Instance = USART2;
 80034ec:	4b14      	ldr	r3, [pc, #80]	@ (8003540 <MX_USART2_UART_Init+0x58>)
 80034ee:	4a15      	ldr	r2, [pc, #84]	@ (8003544 <MX_USART2_UART_Init+0x5c>)
 80034f0:	601a      	str	r2, [r3, #0]
  huart2.Init.BaudRate = 115200;
 80034f2:	4b13      	ldr	r3, [pc, #76]	@ (8003540 <MX_USART2_UART_Init+0x58>)
 80034f4:	f44f 32e1 	mov.w	r2, #115200	@ 0x1c200
 80034f8:	605a      	str	r2, [r3, #4]
  huart2.Init.WordLength = UART_WORDLENGTH_8B;
 80034fa:	4b11      	ldr	r3, [pc, #68]	@ (8003540 <MX_USART2_UART_Init+0x58>)
 80034fc:	2200      	movs	r2, #0
 80034fe:	609a      	str	r2, [r3, #8]
  huart2.Init.StopBits = UART_STOPBITS_1;
 8003500:	4b0f      	ldr	r3, [pc, #60]	@ (8003540 <MX_USART2_UART_Init+0x58>)
 8003502:	2200      	movs	r2, #0
 8003504:	60da      	str	r2, [r3, #12]
  huart2.Init.Parity = UART_PARITY_NONE;
 8003506:	4b0e      	ldr	r3, [pc, #56]	@ (8003540 <MX_USART2_UART_Init+0x58>)
 8003508:	2200      	movs	r2, #0
 800350a:	611a      	str	r2, [r3, #16]
  huart2.Init.Mode = UART_MODE_TX_RX;
 800350c:	4b0c      	ldr	r3, [pc, #48]	@ (8003540 <MX_USART2_UART_Init+0x58>)
 800350e:	220c      	movs	r2, #12
 8003510:	615a      	str	r2, [r3, #20]
  huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 8003512:	4b0b      	ldr	r3, [pc, #44]	@ (8003540 <MX_USART2_UART_Init+0x58>)
 8003514:	2200      	movs	r2, #0
 8003516:	619a      	str	r2, [r3, #24]
  huart2.Init.OverSampling = UART_OVERSAMPLING_16;
 8003518:	4b09      	ldr	r3, [pc, #36]	@ (8003540 <MX_USART2_UART_Init+0x58>)
 800351a:	2200      	movs	r2, #0
 800351c:	61da      	str	r2, [r3, #28]
  huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
 800351e:	4b08      	ldr	r3, [pc, #32]	@ (8003540 <MX_USART2_UART_Init+0x58>)
 8003520:	2200      	movs	r2, #0
 8003522:	621a      	str	r2, [r3, #32]
  huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
 8003524:	4b06      	ldr	r3, [pc, #24]	@ (8003540 <MX_USART2_UART_Init+0x58>)
 8003526:	2200      	movs	r2, #0
 8003528:	625a      	str	r2, [r3, #36]	@ 0x24
  if (HAL_UART_Init(&huart2) != HAL_OK)
 800352a:	4805      	ldr	r0, [pc, #20]	@ (8003540 <MX_USART2_UART_Init+0x58>)
 800352c:	f003 f9d4 	bl	80068d8 <HAL_UART_Init>
 8003530:	4603      	mov	r3, r0
 8003532:	2b00      	cmp	r3, #0
 8003534:	d001      	beq.n	800353a <MX_USART2_UART_Init+0x52>
  {
    Error_Handler();
 8003536:	f000 f891 	bl	800365c <Error_Handler>
  }
}
 800353a:	bf00      	nop
 800353c:	bd80      	pop	{r7, pc}
 800353e:	bf00      	nop
 8003540:	20000244 	.word	0x20000244
 8003544:	40004400 	.word	0x40004400

08003548 <MX_GPIO_Init>:

static void MX_GPIO_Init(void)
{
 8003548:	b580      	push	{r7, lr}
 800354a:	b08a      	sub	sp, #40	@ 0x28
 800354c:	af00      	add	r7, sp, #0
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 800354e:	f107 0314 	add.w	r3, r7, #20
 8003552:	2200      	movs	r2, #0
 8003554:	601a      	str	r2, [r3, #0]
 8003556:	605a      	str	r2, [r3, #4]
 8003558:	609a      	str	r2, [r3, #8]
 800355a:	60da      	str	r2, [r3, #12]
 800355c:	611a      	str	r2, [r3, #16]

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOC_CLK_ENABLE();
 800355e:	4b3c      	ldr	r3, [pc, #240]	@ (8003650 <MX_GPIO_Init+0x108>)
 8003560:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8003562:	4a3b      	ldr	r2, [pc, #236]	@ (8003650 <MX_GPIO_Init+0x108>)
 8003564:	f043 0304 	orr.w	r3, r3, #4
 8003568:	64d3      	str	r3, [r2, #76]	@ 0x4c
 800356a:	4b39      	ldr	r3, [pc, #228]	@ (8003650 <MX_GPIO_Init+0x108>)
 800356c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800356e:	f003 0304 	and.w	r3, r3, #4
 8003572:	613b      	str	r3, [r7, #16]
 8003574:	693b      	ldr	r3, [r7, #16]
  __HAL_RCC_GPIOH_CLK_ENABLE();
 8003576:	4b36      	ldr	r3, [pc, #216]	@ (8003650 <MX_GPIO_Init+0x108>)
 8003578:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800357a:	4a35      	ldr	r2, [pc, #212]	@ (8003650 <MX_GPIO_Init+0x108>)
 800357c:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
 8003580:	64d3      	str	r3, [r2, #76]	@ 0x4c
 8003582:	4b33      	ldr	r3, [pc, #204]	@ (8003650 <MX_GPIO_Init+0x108>)
 8003584:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8003586:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 800358a:	60fb      	str	r3, [r7, #12]
 800358c:	68fb      	ldr	r3, [r7, #12]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 800358e:	4b30      	ldr	r3, [pc, #192]	@ (8003650 <MX_GPIO_Init+0x108>)
 8003590:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8003592:	4a2f      	ldr	r2, [pc, #188]	@ (8003650 <MX_GPIO_Init+0x108>)
 8003594:	f043 0301 	orr.w	r3, r3, #1
 8003598:	64d3      	str	r3, [r2, #76]	@ 0x4c
 800359a:	4b2d      	ldr	r3, [pc, #180]	@ (8003650 <MX_GPIO_Init+0x108>)
 800359c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800359e:	f003 0301 	and.w	r3, r3, #1
 80035a2:	60bb      	str	r3, [r7, #8]
 80035a4:	68bb      	ldr	r3, [r7, #8]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 80035a6:	4b2a      	ldr	r3, [pc, #168]	@ (8003650 <MX_GPIO_Init+0x108>)
 80035a8:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 80035aa:	4a29      	ldr	r2, [pc, #164]	@ (8003650 <MX_GPIO_Init+0x108>)
 80035ac:	f043 0302 	orr.w	r3, r3, #2
 80035b0:	64d3      	str	r3, [r2, #76]	@ 0x4c
 80035b2:	4b27      	ldr	r3, [pc, #156]	@ (8003650 <MX_GPIO_Init+0x108>)
 80035b4:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 80035b6:	f003 0302 	and.w	r3, r3, #2
 80035ba:	607b      	str	r3, [r7, #4]
 80035bc:	687b      	ldr	r3, [r7, #4]

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOA, SMPS_EN_Pin|SMPS_V1_Pin|SMPS_SW_Pin, GPIO_PIN_RESET);
 80035be:	2200      	movs	r2, #0
 80035c0:	21b0      	movs	r1, #176	@ 0xb0
 80035c2:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 80035c6:	f001 f839 	bl	800463c <HAL_GPIO_WritePin>

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(LD4_GPIO_Port, LD4_Pin, GPIO_PIN_RESET);
 80035ca:	2200      	movs	r2, #0
 80035cc:	f44f 5100 	mov.w	r1, #8192	@ 0x2000
 80035d0:	4820      	ldr	r0, [pc, #128]	@ (8003654 <MX_GPIO_Init+0x10c>)
 80035d2:	f001 f833 	bl	800463c <HAL_GPIO_WritePin>

  /*Configure GPIO pin : B1_Pin */
  GPIO_InitStruct.Pin = B1_Pin;
 80035d6:	f44f 5300 	mov.w	r3, #8192	@ 0x2000
 80035da:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
 80035dc:	f44f 1304 	mov.w	r3, #2162688	@ 0x210000
 80035e0:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 80035e2:	2300      	movs	r3, #0
 80035e4:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
 80035e6:	f107 0314 	add.w	r3, r7, #20
 80035ea:	4619      	mov	r1, r3
 80035ec:	481a      	ldr	r0, [pc, #104]	@ (8003658 <MX_GPIO_Init+0x110>)
 80035ee:	f000 feab 	bl	8004348 <HAL_GPIO_Init>

  /*Configure GPIO pins : SMPS_EN_Pin SMPS_V1_Pin SMPS_SW_Pin */
  GPIO_InitStruct.Pin = SMPS_EN_Pin|SMPS_V1_Pin|SMPS_SW_Pin;
 80035f2:	23b0      	movs	r3, #176	@ 0xb0
 80035f4:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 80035f6:	2301      	movs	r3, #1
 80035f8:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 80035fa:	2300      	movs	r3, #0
 80035fc:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 80035fe:	2300      	movs	r3, #0
 8003600:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8003602:	f107 0314 	add.w	r3, r7, #20
 8003606:	4619      	mov	r1, r3
 8003608:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 800360c:	f000 fe9c 	bl	8004348 <HAL_GPIO_Init>

  /*Configure GPIO pin : SMPS_PG_Pin */
  GPIO_InitStruct.Pin = SMPS_PG_Pin;
 8003610:	2340      	movs	r3, #64	@ 0x40
 8003612:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8003614:	2300      	movs	r3, #0
 8003616:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_PULLUP;
 8003618:	2301      	movs	r3, #1
 800361a:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(SMPS_PG_GPIO_Port, &GPIO_InitStruct);
 800361c:	f107 0314 	add.w	r3, r7, #20
 8003620:	4619      	mov	r1, r3
 8003622:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 8003626:	f000 fe8f 	bl	8004348 <HAL_GPIO_Init>

  /*Configure GPIO pin : LD4_Pin */
  GPIO_InitStruct.Pin = LD4_Pin;
 800362a:	f44f 5300 	mov.w	r3, #8192	@ 0x2000
 800362e:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8003630:	2301      	movs	r3, #1
 8003632:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8003634:	2300      	movs	r3, #0
 8003636:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8003638:	2300      	movs	r3, #0
 800363a:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(LD4_GPIO_Port, &GPIO_InitStruct);
 800363c:	f107 0314 	add.w	r3, r7, #20
 8003640:	4619      	mov	r1, r3
 8003642:	4804      	ldr	r0, [pc, #16]	@ (8003654 <MX_GPIO_Init+0x10c>)
 8003644:	f000 fe80 	bl	8004348 <HAL_GPIO_Init>
}
 8003648:	bf00      	nop
 800364a:	3728      	adds	r7, #40	@ 0x28
 800364c:	46bd      	mov	sp, r7
 800364e:	bd80      	pop	{r7, pc}
 8003650:	40021000 	.word	0x40021000
 8003654:	48000400 	.word	0x48000400
 8003658:	48000800 	.word	0x48000800

0800365c <Error_Handler>:

void Error_Handler(void)
{
 800365c:	b480      	push	{r7}
 800365e:	af00      	add	r7, sp, #0
  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __disable_irq(void)
{
  __ASM volatile ("cpsid i" : : : "memory");
 8003660:	b672      	cpsid	i
}
 8003662:	bf00      	nop
  __disable_irq();
  while (1)
 8003664:	bf00      	nop
 8003666:	e7fd      	b.n	8003664 <Error_Handler+0x8>

08003668 <Moto_InitData>:

//------------------------------------------------------------------------------
// Fonctions publiques
//------------------------------------------------------------------------------

void Moto_InitData(MotoData_t *data) {
 8003668:	b580      	push	{r7, lr}
 800366a:	b082      	sub	sp, #8
 800366c:	af00      	add	r7, sp, #0
 800366e:	6078      	str	r0, [r7, #4]
    memset(data, 0, sizeof(MotoData_t));
 8003670:	2224      	movs	r2, #36	@ 0x24
 8003672:	2100      	movs	r1, #0
 8003674:	6878      	ldr	r0, [r7, #4]
 8003676:	f004 fc4a 	bl	8007f0e <memset>
    data->state = MOTO_STATE_NORMAL;
 800367a:	687b      	ldr	r3, [r7, #4]
 800367c:	2200      	movs	r2, #0
 800367e:	761a      	strb	r2, [r3, #24]
    data->is_initializing = true;
 8003680:	687b      	ldr	r3, [r7, #4]
 8003682:	2201      	movs	r2, #1
 8003684:	765a      	strb	r2, [r3, #25]
    data->last_update_time = 0;
 8003686:	687b      	ldr	r3, [r7, #4]
 8003688:	2200      	movs	r2, #0
 800368a:	621a      	str	r2, [r3, #32]
}
 800368c:	bf00      	nop
 800368e:	3708      	adds	r7, #8
 8003690:	46bd      	mov	sp, r7
 8003692:	bd80      	pop	{r7, pc}

08003694 <Moto_UpdateState>:

void Moto_UpdateState(MotoData_t *data, float roll, float pitch, float yaw,
                      float gyro_x, float gyro_y, float gyro_z) {
 8003694:	b580      	push	{r7, lr}
 8003696:	b08a      	sub	sp, #40	@ 0x28
 8003698:	af00      	add	r7, sp, #0
 800369a:	61f8      	str	r0, [r7, #28]
 800369c:	ed87 0a06 	vstr	s0, [r7, #24]
 80036a0:	edc7 0a05 	vstr	s1, [r7, #20]
 80036a4:	ed87 1a04 	vstr	s2, [r7, #16]
 80036a8:	edc7 1a03 	vstr	s3, [r7, #12]
 80036ac:	ed87 2a02 	vstr	s4, [r7, #8]
 80036b0:	edc7 2a01 	vstr	s5, [r7, #4]

    // Mise à jour des angles bruts
    data->roll = roll;
 80036b4:	69fb      	ldr	r3, [r7, #28]
 80036b6:	69ba      	ldr	r2, [r7, #24]
 80036b8:	601a      	str	r2, [r3, #0]
    data->pitch = pitch;
 80036ba:	69fb      	ldr	r3, [r7, #28]
 80036bc:	697a      	ldr	r2, [r7, #20]
 80036be:	605a      	str	r2, [r3, #4]
    data->yaw = yaw;
 80036c0:	69fb      	ldr	r3, [r7, #28]
 80036c2:	693a      	ldr	r2, [r7, #16]
 80036c4:	609a      	str	r2, [r3, #8]

    // Calcul de la magnitude de la vitesse angulaire
    float gyro_magnitude = sqrtf(gyro_x*gyro_x + gyro_y*gyro_y + gyro_z*gyro_z);
 80036c6:	edd7 7a03 	vldr	s15, [r7, #12]
 80036ca:	ee27 7aa7 	vmul.f32	s14, s15, s15
 80036ce:	edd7 7a02 	vldr	s15, [r7, #8]
 80036d2:	ee67 7aa7 	vmul.f32	s15, s15, s15
 80036d6:	ee37 7a27 	vadd.f32	s14, s14, s15
 80036da:	edd7 7a01 	vldr	s15, [r7, #4]
 80036de:	ee67 7aa7 	vmul.f32	s15, s15, s15
 80036e2:	ee77 7a27 	vadd.f32	s15, s14, s15
 80036e6:	eeb0 0a67 	vmov.f32	s0, s15
 80036ea:	f006 fd65 	bl	800a1b8 <sqrtf>
 80036ee:	ed87 0a09 	vstr	s0, [r7, #36]	@ 0x24

    // Détection d'état prioritaire : crash possible
    if (Moto_DetectCrash(data, gyro_magnitude)) {
 80036f2:	ed97 0a09 	vldr	s0, [r7, #36]	@ 0x24
 80036f6:	69f8      	ldr	r0, [r7, #28]
 80036f8:	f000 f99e 	bl	8003a38 <Moto_DetectCrash>
 80036fc:	4603      	mov	r3, r0
 80036fe:	2b00      	cmp	r3, #0
 8003700:	d003      	beq.n	800370a <Moto_UpdateState+0x76>
        data->state = MOTO_STATE_POSSIBLE_CRASH;
 8003702:	69fb      	ldr	r3, [r7, #28]
 8003704:	2206      	movs	r2, #6
 8003706:	761a      	strb	r2, [r3, #24]
        return;
 8003708:	e04c      	b.n	80037a4 <Moto_UpdateState+0x110>
    }

    // Détection de wheelie/stoppie
    if (pitch > MOTO_PITCH_WHEELIE_THRESHOLD) {
 800370a:	edd7 7a05 	vldr	s15, [r7, #20]
 800370e:	eeb3 7a09 	vmov.f32	s14, #57	@ 0x41c80000  25.0
 8003712:	eef4 7ac7 	vcmpe.f32	s15, s14
 8003716:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800371a:	dd03      	ble.n	8003724 <Moto_UpdateState+0x90>
        data->state = MOTO_STATE_WHEELIE;
 800371c:	69fb      	ldr	r3, [r7, #28]
 800371e:	2203      	movs	r2, #3
 8003720:	761a      	strb	r2, [r3, #24]
 8003722:	e03f      	b.n	80037a4 <Moto_UpdateState+0x110>
    } else if (pitch < MOTO_PITCH_STOPPIE_THRESHOLD) {
 8003724:	edd7 7a05 	vldr	s15, [r7, #20]
 8003728:	eebb 7a09 	vmov.f32	s14, #185	@ 0xc1c80000 -25.0
 800372c:	eef4 7ac7 	vcmpe.f32	s15, s14
 8003730:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8003734:	d503      	bpl.n	800373e <Moto_UpdateState+0xaa>
        data->state = MOTO_STATE_STOPPIE;
 8003736:	69fb      	ldr	r3, [r7, #28]
 8003738:	2204      	movs	r2, #4
 800373a:	761a      	strb	r2, [r3, #24]
 800373c:	e032      	b.n	80037a4 <Moto_UpdateState+0x110>
    }
    // Détection de virage rapide
    else if (fabsf(gyro_z) > MOTO_GYRO_RAPID_TURN_THRESHOLD) {
 800373e:	edd7 7a01 	vldr	s15, [r7, #4]
 8003742:	eef0 7ae7 	vabs.f32	s15, s15
 8003746:	ed9f 7a19 	vldr	s14, [pc, #100]	@ 80037ac <Moto_UpdateState+0x118>
 800374a:	eef4 7ac7 	vcmpe.f32	s15, s14
 800374e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8003752:	dd03      	ble.n	800375c <Moto_UpdateState+0xc8>
        data->state = MOTO_STATE_RAPID_TURN;
 8003754:	69fb      	ldr	r3, [r7, #28]
 8003756:	2205      	movs	r2, #5
 8003758:	761a      	strb	r2, [r3, #24]
 800375a:	e023      	b.n	80037a4 <Moto_UpdateState+0x110>
    }
    // Détection d'inclinaison dangereuse
    else if (fabsf(roll) > MOTO_ROLL_DANGER_THRESHOLD) {
 800375c:	edd7 7a06 	vldr	s15, [r7, #24]
 8003760:	eef0 7ae7 	vabs.f32	s15, s15
 8003764:	ed9f 7a12 	vldr	s14, [pc, #72]	@ 80037b0 <Moto_UpdateState+0x11c>
 8003768:	eef4 7ac7 	vcmpe.f32	s15, s14
 800376c:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8003770:	dd03      	ble.n	800377a <Moto_UpdateState+0xe6>
        data->state = MOTO_STATE_DANGER;
 8003772:	69fb      	ldr	r3, [r7, #28]
 8003774:	2202      	movs	r2, #2
 8003776:	761a      	strb	r2, [r3, #24]
 8003778:	e014      	b.n	80037a4 <Moto_UpdateState+0x110>
    }
    // Détection d'inclinaison d'avertissement
    else if (fabsf(roll) > MOTO_ROLL_WARNING_THRESHOLD) {
 800377a:	edd7 7a06 	vldr	s15, [r7, #24]
 800377e:	eef0 7ae7 	vabs.f32	s15, s15
 8003782:	eeb3 7a04 	vmov.f32	s14, #52	@ 0x41a00000  20.0
 8003786:	eef4 7ac7 	vcmpe.f32	s15, s14
 800378a:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800378e:	dd03      	ble.n	8003798 <Moto_UpdateState+0x104>
        data->state = MOTO_STATE_WARNING;
 8003790:	69fb      	ldr	r3, [r7, #28]
 8003792:	2201      	movs	r2, #1
 8003794:	761a      	strb	r2, [r3, #24]
 8003796:	e005      	b.n	80037a4 <Moto_UpdateState+0x110>
    }
    // État normal
    else {
        data->state = MOTO_STATE_NORMAL;
 8003798:	69fb      	ldr	r3, [r7, #28]
 800379a:	2200      	movs	r2, #0
 800379c:	761a      	strb	r2, [r3, #24]
        data->crash_detect_counter = 0; // Reset compteur crash
 800379e:	69fb      	ldr	r3, [r7, #28]
 80037a0:	2200      	movs	r2, #0
 80037a2:	61da      	str	r2, [r3, #28]
    }
}
 80037a4:	3728      	adds	r7, #40	@ 0x28
 80037a6:	46bd      	mov	sp, r7
 80037a8:	bd80      	pop	{r7, pc}
 80037aa:	bf00      	nop
 80037ac:	42c80000 	.word	0x42c80000
 80037b0:	420c0000 	.word	0x420c0000

080037b4 <Moto_FilterAngles>:

void Moto_FilterAngles(MotoData_t *data) {
 80037b4:	b480      	push	{r7}
 80037b6:	b083      	sub	sp, #12
 80037b8:	af00      	add	r7, sp, #0
 80037ba:	6078      	str	r0, [r7, #4]
    // Filtre passe-bas simple pour lisser l'affichage
    data->roll_filtered = MOTO_ANGLE_FILTER_ALPHA * data->roll +
 80037bc:	687b      	ldr	r3, [r7, #4]
 80037be:	edd3 7a00 	vldr	s15, [r3]
 80037c2:	ed9f 7a1e 	vldr	s14, [pc, #120]	@ 800383c <Moto_FilterAngles+0x88>
 80037c6:	ee27 7a87 	vmul.f32	s14, s15, s14
                         (1.0f - MOTO_ANGLE_FILTER_ALPHA) * data->roll_filtered;
 80037ca:	687b      	ldr	r3, [r7, #4]
 80037cc:	edd3 7a03 	vldr	s15, [r3, #12]
 80037d0:	eddf 6a1b 	vldr	s13, [pc, #108]	@ 8003840 <Moto_FilterAngles+0x8c>
 80037d4:	ee67 7aa6 	vmul.f32	s15, s15, s13
    data->roll_filtered = MOTO_ANGLE_FILTER_ALPHA * data->roll +
 80037d8:	ee77 7a27 	vadd.f32	s15, s14, s15
 80037dc:	687b      	ldr	r3, [r7, #4]
 80037de:	edc3 7a03 	vstr	s15, [r3, #12]

    data->pitch_filtered = MOTO_ANGLE_FILTER_ALPHA * data->pitch +
 80037e2:	687b      	ldr	r3, [r7, #4]
 80037e4:	edd3 7a01 	vldr	s15, [r3, #4]
 80037e8:	ed9f 7a14 	vldr	s14, [pc, #80]	@ 800383c <Moto_FilterAngles+0x88>
 80037ec:	ee27 7a87 	vmul.f32	s14, s15, s14
                          (1.0f - MOTO_ANGLE_FILTER_ALPHA) * data->pitch_filtered;
 80037f0:	687b      	ldr	r3, [r7, #4]
 80037f2:	edd3 7a04 	vldr	s15, [r3, #16]
 80037f6:	eddf 6a12 	vldr	s13, [pc, #72]	@ 8003840 <Moto_FilterAngles+0x8c>
 80037fa:	ee67 7aa6 	vmul.f32	s15, s15, s13
    data->pitch_filtered = MOTO_ANGLE_FILTER_ALPHA * data->pitch +
 80037fe:	ee77 7a27 	vadd.f32	s15, s14, s15
 8003802:	687b      	ldr	r3, [r7, #4]
 8003804:	edc3 7a04 	vstr	s15, [r3, #16]

    data->yaw_filtered = MOTO_ANGLE_FILTER_ALPHA * data->yaw +
 8003808:	687b      	ldr	r3, [r7, #4]
 800380a:	edd3 7a02 	vldr	s15, [r3, #8]
 800380e:	ed9f 7a0b 	vldr	s14, [pc, #44]	@ 800383c <Moto_FilterAngles+0x88>
 8003812:	ee27 7a87 	vmul.f32	s14, s15, s14
                        (1.0f - MOTO_ANGLE_FILTER_ALPHA) * data->yaw_filtered;
 8003816:	687b      	ldr	r3, [r7, #4]
 8003818:	edd3 7a05 	vldr	s15, [r3, #20]
 800381c:	eddf 6a08 	vldr	s13, [pc, #32]	@ 8003840 <Moto_FilterAngles+0x8c>
 8003820:	ee67 7aa6 	vmul.f32	s15, s15, s13
    data->yaw_filtered = MOTO_ANGLE_FILTER_ALPHA * data->yaw +
 8003824:	ee77 7a27 	vadd.f32	s15, s14, s15
 8003828:	687b      	ldr	r3, [r7, #4]
 800382a:	edc3 7a05 	vstr	s15, [r3, #20]
}
 800382e:	bf00      	nop
 8003830:	370c      	adds	r7, #12
 8003832:	46bd      	mov	sp, r7
 8003834:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003838:	4770      	bx	lr
 800383a:	bf00      	nop
 800383c:	3e4ccccd 	.word	0x3e4ccccd
 8003840:	3f4ccccd 	.word	0x3f4ccccd

08003844 <Moto_GetStateString>:

const char* Moto_GetStateString(MotoState_t state) {
 8003844:	b480      	push	{r7}
 8003846:	b083      	sub	sp, #12
 8003848:	af00      	add	r7, sp, #0
 800384a:	4603      	mov	r3, r0
 800384c:	71fb      	strb	r3, [r7, #7]
    switch (state) {
 800384e:	79fb      	ldrb	r3, [r7, #7]
 8003850:	2b06      	cmp	r3, #6
 8003852:	d81f      	bhi.n	8003894 <Moto_GetStateString+0x50>
 8003854:	a201      	add	r2, pc, #4	@ (adr r2, 800385c <Moto_GetStateString+0x18>)
 8003856:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800385a:	bf00      	nop
 800385c:	08003879 	.word	0x08003879
 8003860:	0800387d 	.word	0x0800387d
 8003864:	08003881 	.word	0x08003881
 8003868:	08003885 	.word	0x08003885
 800386c:	08003889 	.word	0x08003889
 8003870:	0800388d 	.word	0x0800388d
 8003874:	08003891 	.word	0x08003891
        case MOTO_STATE_NORMAL:         return "NORMAL";
 8003878:	4b0a      	ldr	r3, [pc, #40]	@ (80038a4 <Moto_GetStateString+0x60>)
 800387a:	e00c      	b.n	8003896 <Moto_GetStateString+0x52>
        case MOTO_STATE_WARNING:        return "ATTENTION";
 800387c:	4b0a      	ldr	r3, [pc, #40]	@ (80038a8 <Moto_GetStateString+0x64>)
 800387e:	e00a      	b.n	8003896 <Moto_GetStateString+0x52>
        case MOTO_STATE_DANGER:         return "DANGER";
 8003880:	4b0a      	ldr	r3, [pc, #40]	@ (80038ac <Moto_GetStateString+0x68>)
 8003882:	e008      	b.n	8003896 <Moto_GetStateString+0x52>
        case MOTO_STATE_WHEELIE:        return "WHEELIE";
 8003884:	4b0a      	ldr	r3, [pc, #40]	@ (80038b0 <Moto_GetStateString+0x6c>)
 8003886:	e006      	b.n	8003896 <Moto_GetStateString+0x52>
        case MOTO_STATE_STOPPIE:        return "STOPPIE";
 8003888:	4b0a      	ldr	r3, [pc, #40]	@ (80038b4 <Moto_GetStateString+0x70>)
 800388a:	e004      	b.n	8003896 <Moto_GetStateString+0x52>
        case MOTO_STATE_RAPID_TURN:     return "VIRAGE RAPIDE";
 800388c:	4b0a      	ldr	r3, [pc, #40]	@ (80038b8 <Moto_GetStateString+0x74>)
 800388e:	e002      	b.n	8003896 <Moto_GetStateString+0x52>
        case MOTO_STATE_POSSIBLE_CRASH: return "CHUTE POSSIBLE";
 8003890:	4b0a      	ldr	r3, [pc, #40]	@ (80038bc <Moto_GetStateString+0x78>)
 8003892:	e000      	b.n	8003896 <Moto_GetStateString+0x52>
        default:                        return "INCONNU";
 8003894:	4b0a      	ldr	r3, [pc, #40]	@ (80038c0 <Moto_GetStateString+0x7c>)
    }
}
 8003896:	4618      	mov	r0, r3
 8003898:	370c      	adds	r7, #12
 800389a:	46bd      	mov	sp, r7
 800389c:	f85d 7b04 	ldr.w	r7, [sp], #4
 80038a0:	4770      	bx	lr
 80038a2:	bf00      	nop
 80038a4:	0800b7bc 	.word	0x0800b7bc
 80038a8:	0800b7c4 	.word	0x0800b7c4
 80038ac:	0800b7d0 	.word	0x0800b7d0
 80038b0:	0800b7d8 	.word	0x0800b7d8
 80038b4:	0800b7e0 	.word	0x0800b7e0
 80038b8:	0800b7e8 	.word	0x0800b7e8
 80038bc:	0800b7f8 	.word	0x0800b7f8
 80038c0:	0800b808 	.word	0x0800b808

080038c4 <Moto_UpdateStats>:

void Moto_UpdateStats(MotoStats_t *stats, const MotoData_t *data,
                      float gyro_x, float gyro_y, float gyro_z) {
 80038c4:	b480      	push	{r7}
 80038c6:	b087      	sub	sp, #28
 80038c8:	af00      	add	r7, sp, #0
 80038ca:	6178      	str	r0, [r7, #20]
 80038cc:	6139      	str	r1, [r7, #16]
 80038ce:	ed87 0a03 	vstr	s0, [r7, #12]
 80038d2:	edc7 0a02 	vstr	s1, [r7, #8]
 80038d6:	ed87 1a01 	vstr	s2, [r7, #4]

    stats->total_samples++;
 80038da:	697b      	ldr	r3, [r7, #20]
 80038dc:	69db      	ldr	r3, [r3, #28]
 80038de:	1c5a      	adds	r2, r3, #1
 80038e0:	697b      	ldr	r3, [r7, #20]
 80038e2:	61da      	str	r2, [r3, #28]

    // Mise à jour des extremums d'angles
    if (data->roll > stats->max_roll) stats->max_roll = data->roll;
 80038e4:	693b      	ldr	r3, [r7, #16]
 80038e6:	ed93 7a00 	vldr	s14, [r3]
 80038ea:	697b      	ldr	r3, [r7, #20]
 80038ec:	edd3 7a00 	vldr	s15, [r3]
 80038f0:	eeb4 7ae7 	vcmpe.f32	s14, s15
 80038f4:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 80038f8:	dd03      	ble.n	8003902 <Moto_UpdateStats+0x3e>
 80038fa:	693b      	ldr	r3, [r7, #16]
 80038fc:	681a      	ldr	r2, [r3, #0]
 80038fe:	697b      	ldr	r3, [r7, #20]
 8003900:	601a      	str	r2, [r3, #0]
    if (data->roll < stats->min_roll) stats->min_roll = data->roll;
 8003902:	693b      	ldr	r3, [r7, #16]
 8003904:	ed93 7a00 	vldr	s14, [r3]
 8003908:	697b      	ldr	r3, [r7, #20]
 800390a:	edd3 7a01 	vldr	s15, [r3, #4]
 800390e:	eeb4 7ae7 	vcmpe.f32	s14, s15
 8003912:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8003916:	d503      	bpl.n	8003920 <Moto_UpdateStats+0x5c>
 8003918:	693b      	ldr	r3, [r7, #16]
 800391a:	681a      	ldr	r2, [r3, #0]
 800391c:	697b      	ldr	r3, [r7, #20]
 800391e:	605a      	str	r2, [r3, #4]
    if (data->pitch > stats->max_pitch) stats->max_pitch = data->pitch;
 8003920:	693b      	ldr	r3, [r7, #16]
 8003922:	ed93 7a01 	vldr	s14, [r3, #4]
 8003926:	697b      	ldr	r3, [r7, #20]
 8003928:	edd3 7a02 	vldr	s15, [r3, #8]
 800392c:	eeb4 7ae7 	vcmpe.f32	s14, s15
 8003930:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8003934:	dd03      	ble.n	800393e <Moto_UpdateStats+0x7a>
 8003936:	693b      	ldr	r3, [r7, #16]
 8003938:	685a      	ldr	r2, [r3, #4]
 800393a:	697b      	ldr	r3, [r7, #20]
 800393c:	609a      	str	r2, [r3, #8]
    if (data->pitch < stats->min_pitch) stats->min_pitch = data->pitch;
 800393e:	693b      	ldr	r3, [r7, #16]
 8003940:	ed93 7a01 	vldr	s14, [r3, #4]
 8003944:	697b      	ldr	r3, [r7, #20]
 8003946:	edd3 7a03 	vldr	s15, [r3, #12]
 800394a:	eeb4 7ae7 	vcmpe.f32	s14, s15
 800394e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8003952:	d503      	bpl.n	800395c <Moto_UpdateStats+0x98>
 8003954:	693b      	ldr	r3, [r7, #16]
 8003956:	685a      	ldr	r2, [r3, #4]
 8003958:	697b      	ldr	r3, [r7, #20]
 800395a:	60da      	str	r2, [r3, #12]

    // Mise à jour des extremums de vitesse angulaire
    if (fabsf(gyro_x) > stats->max_gyro_x) stats->max_gyro_x = fabsf(gyro_x);
 800395c:	edd7 7a03 	vldr	s15, [r7, #12]
 8003960:	eeb0 7ae7 	vabs.f32	s14, s15
 8003964:	697b      	ldr	r3, [r7, #20]
 8003966:	edd3 7a04 	vldr	s15, [r3, #16]
 800396a:	eeb4 7ae7 	vcmpe.f32	s14, s15
 800396e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8003972:	dd06      	ble.n	8003982 <Moto_UpdateStats+0xbe>
 8003974:	edd7 7a03 	vldr	s15, [r7, #12]
 8003978:	eef0 7ae7 	vabs.f32	s15, s15
 800397c:	697b      	ldr	r3, [r7, #20]
 800397e:	edc3 7a04 	vstr	s15, [r3, #16]
    if (fabsf(gyro_y) > stats->max_gyro_y) stats->max_gyro_y = fabsf(gyro_y);
 8003982:	edd7 7a02 	vldr	s15, [r7, #8]
 8003986:	eeb0 7ae7 	vabs.f32	s14, s15
 800398a:	697b      	ldr	r3, [r7, #20]
 800398c:	edd3 7a05 	vldr	s15, [r3, #20]
 8003990:	eeb4 7ae7 	vcmpe.f32	s14, s15
 8003994:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8003998:	dd06      	ble.n	80039a8 <Moto_UpdateStats+0xe4>
 800399a:	edd7 7a02 	vldr	s15, [r7, #8]
 800399e:	eef0 7ae7 	vabs.f32	s15, s15
 80039a2:	697b      	ldr	r3, [r7, #20]
 80039a4:	edc3 7a05 	vstr	s15, [r3, #20]
    if (fabsf(gyro_z) > stats->max_gyro_z) stats->max_gyro_z = fabsf(gyro_z);
 80039a8:	edd7 7a01 	vldr	s15, [r7, #4]
 80039ac:	eeb0 7ae7 	vabs.f32	s14, s15
 80039b0:	697b      	ldr	r3, [r7, #20]
 80039b2:	edd3 7a06 	vldr	s15, [r3, #24]
 80039b6:	eeb4 7ae7 	vcmpe.f32	s14, s15
 80039ba:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 80039be:	dd06      	ble.n	80039ce <Moto_UpdateStats+0x10a>
 80039c0:	edd7 7a01 	vldr	s15, [r7, #4]
 80039c4:	eef0 7ae7 	vabs.f32	s15, s15
 80039c8:	697b      	ldr	r3, [r7, #20]
 80039ca:	edc3 7a06 	vstr	s15, [r3, #24]

    // Comptage des états d'alerte
    if (data->state == MOTO_STATE_WARNING) stats->warning_count++;
 80039ce:	693b      	ldr	r3, [r7, #16]
 80039d0:	7e1b      	ldrb	r3, [r3, #24]
 80039d2:	2b01      	cmp	r3, #1
 80039d4:	d104      	bne.n	80039e0 <Moto_UpdateStats+0x11c>
 80039d6:	697b      	ldr	r3, [r7, #20]
 80039d8:	6a1b      	ldr	r3, [r3, #32]
 80039da:	1c5a      	adds	r2, r3, #1
 80039dc:	697b      	ldr	r3, [r7, #20]
 80039de:	621a      	str	r2, [r3, #32]
    if (data->state == MOTO_STATE_DANGER ||
 80039e0:	693b      	ldr	r3, [r7, #16]
 80039e2:	7e1b      	ldrb	r3, [r3, #24]
 80039e4:	2b02      	cmp	r3, #2
 80039e6:	d003      	beq.n	80039f0 <Moto_UpdateStats+0x12c>
        data->state == MOTO_STATE_POSSIBLE_CRASH) stats->danger_count++;
 80039e8:	693b      	ldr	r3, [r7, #16]
 80039ea:	7e1b      	ldrb	r3, [r3, #24]
    if (data->state == MOTO_STATE_DANGER ||
 80039ec:	2b06      	cmp	r3, #6
 80039ee:	d104      	bne.n	80039fa <Moto_UpdateStats+0x136>
        data->state == MOTO_STATE_POSSIBLE_CRASH) stats->danger_count++;
 80039f0:	697b      	ldr	r3, [r7, #20]
 80039f2:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80039f4:	1c5a      	adds	r2, r3, #1
 80039f6:	697b      	ldr	r3, [r7, #20]
 80039f8:	625a      	str	r2, [r3, #36]	@ 0x24
}
 80039fa:	bf00      	nop
 80039fc:	371c      	adds	r7, #28
 80039fe:	46bd      	mov	sp, r7
 8003a00:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003a04:	4770      	bx	lr

08003a06 <Moto_CalibrateMagnetometer>:

void Moto_CalibrateMagnetometer(float *mx, float *my, float *mz) {
 8003a06:	b480      	push	{r7}
 8003a08:	b085      	sub	sp, #20
 8003a0a:	af00      	add	r7, sp, #0
 8003a0c:	60f8      	str	r0, [r7, #12]
 8003a0e:	60b9      	str	r1, [r7, #8]
 8003a10:	607a      	str	r2, [r7, #4]
    // Application des offsets et facteurs d'échelle
    *mx = (*mx - MOTO_MAG_OFFSET_X) * MOTO_MAG_SCALE_X;
 8003a12:	68fb      	ldr	r3, [r7, #12]
 8003a14:	681a      	ldr	r2, [r3, #0]
 8003a16:	68fb      	ldr	r3, [r7, #12]
 8003a18:	601a      	str	r2, [r3, #0]
    *my = (*my - MOTO_MAG_OFFSET_Y) * MOTO_MAG_SCALE_Y;
 8003a1a:	68bb      	ldr	r3, [r7, #8]
 8003a1c:	681a      	ldr	r2, [r3, #0]
 8003a1e:	68bb      	ldr	r3, [r7, #8]
 8003a20:	601a      	str	r2, [r3, #0]
    *mz = (*mz - MOTO_MAG_OFFSET_Z) * MOTO_MAG_SCALE_Z;
 8003a22:	687b      	ldr	r3, [r7, #4]
 8003a24:	681a      	ldr	r2, [r3, #0]
 8003a26:	687b      	ldr	r3, [r7, #4]
 8003a28:	601a      	str	r2, [r3, #0]
}
 8003a2a:	bf00      	nop
 8003a2c:	3714      	adds	r7, #20
 8003a2e:	46bd      	mov	sp, r7
 8003a30:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003a34:	4770      	bx	lr
	...

08003a38 <Moto_DetectCrash>:

bool Moto_DetectCrash(MotoData_t *data, float gyro_magnitude) {
 8003a38:	b480      	push	{r7}
 8003a3a:	b083      	sub	sp, #12
 8003a3c:	af00      	add	r7, sp, #0
 8003a3e:	6078      	str	r0, [r7, #4]
 8003a40:	ed87 0a00 	vstr	s0, [r7]
    if (gyro_magnitude > MOTO_GYRO_CRASH_THRESHOLD) {
 8003a44:	edd7 7a00 	vldr	s15, [r7]
 8003a48:	ed9f 7a10 	vldr	s14, [pc, #64]	@ 8003a8c <Moto_DetectCrash+0x54>
 8003a4c:	eef4 7ac7 	vcmpe.f32	s15, s14
 8003a50:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8003a54:	dd0a      	ble.n	8003a6c <Moto_DetectCrash+0x34>
        data->crash_detect_counter++;
 8003a56:	687b      	ldr	r3, [r7, #4]
 8003a58:	69db      	ldr	r3, [r3, #28]
 8003a5a:	1c5a      	adds	r2, r3, #1
 8003a5c:	687b      	ldr	r3, [r7, #4]
 8003a5e:	61da      	str	r2, [r3, #28]

        // Confirme la chute si seuil dépassé pendant plusieurs échantillons
        if (data->crash_detect_counter > 5) { // ~50ms à 100Hz
 8003a60:	687b      	ldr	r3, [r7, #4]
 8003a62:	69db      	ldr	r3, [r3, #28]
 8003a64:	2b05      	cmp	r3, #5
 8003a66:	d90a      	bls.n	8003a7e <Moto_DetectCrash+0x46>
            return true;
 8003a68:	2301      	movs	r3, #1
 8003a6a:	e009      	b.n	8003a80 <Moto_DetectCrash+0x48>
        }
    } else {
        // Décrémente progressivement le compteur
        if (data->crash_detect_counter > 0) {
 8003a6c:	687b      	ldr	r3, [r7, #4]
 8003a6e:	69db      	ldr	r3, [r3, #28]
 8003a70:	2b00      	cmp	r3, #0
 8003a72:	d004      	beq.n	8003a7e <Moto_DetectCrash+0x46>
            data->crash_detect_counter--;
 8003a74:	687b      	ldr	r3, [r7, #4]
 8003a76:	69db      	ldr	r3, [r3, #28]
 8003a78:	1e5a      	subs	r2, r3, #1
 8003a7a:	687b      	ldr	r3, [r7, #4]
 8003a7c:	61da      	str	r2, [r3, #28]
        }
    }

    return false;
 8003a7e:	2300      	movs	r3, #0
}
 8003a80:	4618      	mov	r0, r3
 8003a82:	370c      	adds	r7, #12
 8003a84:	46bd      	mov	sp, r7
 8003a86:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003a8a:	4770      	bx	lr
 8003a8c:	43960000 	.word	0x43960000

08003a90 <Moto_FormatDisplay>:

void Moto_FormatDisplay(const MotoData_t *data, int line, char *buffer) {
 8003a90:	b5b0      	push	{r4, r5, r7, lr}
 8003a92:	b088      	sub	sp, #32
 8003a94:	af04      	add	r7, sp, #16
 8003a96:	60f8      	str	r0, [r7, #12]
 8003a98:	60b9      	str	r1, [r7, #8]
 8003a9a:	607a      	str	r2, [r7, #4]
    switch (line) {
 8003a9c:	68bb      	ldr	r3, [r7, #8]
 8003a9e:	2b03      	cmp	r3, #3
 8003aa0:	f200 8097 	bhi.w	8003bd2 <Moto_FormatDisplay+0x142>
 8003aa4:	a201      	add	r2, pc, #4	@ (adr r2, 8003aac <Moto_FormatDisplay+0x1c>)
 8003aa6:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8003aaa:	bf00      	nop
 8003aac:	08003abd 	.word	0x08003abd
 8003ab0:	08003aed 	.word	0x08003aed
 8003ab4:	08003b0b 	.word	0x08003b0b
 8003ab8:	08003b23 	.word	0x08003b23
        case 0:
            snprintf(buffer, 21, "R:%5.1f P:%5.1f",
                    data->roll_filtered, data->pitch_filtered);
 8003abc:	68fb      	ldr	r3, [r7, #12]
 8003abe:	68db      	ldr	r3, [r3, #12]
            snprintf(buffer, 21, "R:%5.1f P:%5.1f",
 8003ac0:	4618      	mov	r0, r3
 8003ac2:	f7fc fd49 	bl	8000558 <__aeabi_f2d>
 8003ac6:	4604      	mov	r4, r0
 8003ac8:	460d      	mov	r5, r1
                    data->roll_filtered, data->pitch_filtered);
 8003aca:	68fb      	ldr	r3, [r7, #12]
 8003acc:	691b      	ldr	r3, [r3, #16]
            snprintf(buffer, 21, "R:%5.1f P:%5.1f",
 8003ace:	4618      	mov	r0, r3
 8003ad0:	f7fc fd42 	bl	8000558 <__aeabi_f2d>
 8003ad4:	4602      	mov	r2, r0
 8003ad6:	460b      	mov	r3, r1
 8003ad8:	e9cd 2302 	strd	r2, r3, [sp, #8]
 8003adc:	e9cd 4500 	strd	r4, r5, [sp]
 8003ae0:	4a41      	ldr	r2, [pc, #260]	@ (8003be8 <Moto_FormatDisplay+0x158>)
 8003ae2:	2115      	movs	r1, #21
 8003ae4:	6878      	ldr	r0, [r7, #4]
 8003ae6:	f004 f999 	bl	8007e1c <sniprintf>
            break;
 8003aea:	e078      	b.n	8003bde <Moto_FormatDisplay+0x14e>

        case 1:
            snprintf(buffer, 21, "Yaw: %6.1f deg", data->yaw_filtered);
 8003aec:	68fb      	ldr	r3, [r7, #12]
 8003aee:	695b      	ldr	r3, [r3, #20]
 8003af0:	4618      	mov	r0, r3
 8003af2:	f7fc fd31 	bl	8000558 <__aeabi_f2d>
 8003af6:	4602      	mov	r2, r0
 8003af8:	460b      	mov	r3, r1
 8003afa:	e9cd 2300 	strd	r2, r3, [sp]
 8003afe:	4a3b      	ldr	r2, [pc, #236]	@ (8003bec <Moto_FormatDisplay+0x15c>)
 8003b00:	2115      	movs	r1, #21
 8003b02:	6878      	ldr	r0, [r7, #4]
 8003b04:	f004 f98a 	bl	8007e1c <sniprintf>
            break;
 8003b08:	e069      	b.n	8003bde <Moto_FormatDisplay+0x14e>

        case 2:
            snprintf(buffer, 21, "Etat: %s", Moto_GetStateString(data->state));
 8003b0a:	68fb      	ldr	r3, [r7, #12]
 8003b0c:	7e1b      	ldrb	r3, [r3, #24]
 8003b0e:	4618      	mov	r0, r3
 8003b10:	f7ff fe98 	bl	8003844 <Moto_GetStateString>
 8003b14:	4603      	mov	r3, r0
 8003b16:	4a36      	ldr	r2, [pc, #216]	@ (8003bf0 <Moto_FormatDisplay+0x160>)
 8003b18:	2115      	movs	r1, #21
 8003b1a:	6878      	ldr	r0, [r7, #4]
 8003b1c:	f004 f97e 	bl	8007e1c <sniprintf>
            break;
 8003b20:	e05d      	b.n	8003bde <Moto_FormatDisplay+0x14e>

        case 3:
            if (data->is_initializing) {
 8003b22:	68fb      	ldr	r3, [r7, #12]
 8003b24:	7e5b      	ldrb	r3, [r3, #25]
 8003b26:	2b00      	cmp	r3, #0
 8003b28:	d005      	beq.n	8003b36 <Moto_FormatDisplay+0xa6>
                snprintf(buffer, 21, "--- INIT EN COURS ---");
 8003b2a:	4a32      	ldr	r2, [pc, #200]	@ (8003bf4 <Moto_FormatDisplay+0x164>)
 8003b2c:	2115      	movs	r1, #21
 8003b2e:	6878      	ldr	r0, [r7, #4]
 8003b30:	f004 f974 	bl	8007e1c <sniprintf>
                    default:
                        snprintf(buffer, 21, "--- INCONNU ---");
                        break;
                }
            }
            break;
 8003b34:	e053      	b.n	8003bde <Moto_FormatDisplay+0x14e>
                switch (data->state) {
 8003b36:	68fb      	ldr	r3, [r7, #12]
 8003b38:	7e1b      	ldrb	r3, [r3, #24]
 8003b3a:	2b06      	cmp	r3, #6
 8003b3c:	d842      	bhi.n	8003bc4 <Moto_FormatDisplay+0x134>
 8003b3e:	a201      	add	r2, pc, #4	@ (adr r2, 8003b44 <Moto_FormatDisplay+0xb4>)
 8003b40:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8003b44:	08003b61 	.word	0x08003b61
 8003b48:	08003b6d 	.word	0x08003b6d
 8003b4c:	08003b95 	.word	0x08003b95
 8003b50:	08003ba1 	.word	0x08003ba1
 8003b54:	08003bad 	.word	0x08003bad
 8003b58:	08003bb9 	.word	0x08003bb9
 8003b5c:	08003b95 	.word	0x08003b95
                        snprintf(buffer, 21, "--- EQUILIBRE ---");
 8003b60:	4a25      	ldr	r2, [pc, #148]	@ (8003bf8 <Moto_FormatDisplay+0x168>)
 8003b62:	2115      	movs	r1, #21
 8003b64:	6878      	ldr	r0, [r7, #4]
 8003b66:	f004 f959 	bl	8007e1c <sniprintf>
                        break;
 8003b6a:	e031      	b.n	8003bd0 <Moto_FormatDisplay+0x140>
                        if (data->roll > 0) {
 8003b6c:	68fb      	ldr	r3, [r7, #12]
 8003b6e:	edd3 7a00 	vldr	s15, [r3]
 8003b72:	eef5 7ac0 	vcmpe.f32	s15, #0.0
 8003b76:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 8003b7a:	dd05      	ble.n	8003b88 <Moto_FormatDisplay+0xf8>
                            snprintf(buffer, 21, "INCLIN. DROITE  >>>");
 8003b7c:	4a1f      	ldr	r2, [pc, #124]	@ (8003bfc <Moto_FormatDisplay+0x16c>)
 8003b7e:	2115      	movs	r1, #21
 8003b80:	6878      	ldr	r0, [r7, #4]
 8003b82:	f004 f94b 	bl	8007e1c <sniprintf>
                        break;
 8003b86:	e023      	b.n	8003bd0 <Moto_FormatDisplay+0x140>
                            snprintf(buffer, 21, "<<<  INCLIN. GAUCHE");
 8003b88:	4a1d      	ldr	r2, [pc, #116]	@ (8003c00 <Moto_FormatDisplay+0x170>)
 8003b8a:	2115      	movs	r1, #21
 8003b8c:	6878      	ldr	r0, [r7, #4]
 8003b8e:	f004 f945 	bl	8007e1c <sniprintf>
                        break;
 8003b92:	e01d      	b.n	8003bd0 <Moto_FormatDisplay+0x140>
                        snprintf(buffer, 21, "!!! ATTENTION !!!");
 8003b94:	4a1b      	ldr	r2, [pc, #108]	@ (8003c04 <Moto_FormatDisplay+0x174>)
 8003b96:	2115      	movs	r1, #21
 8003b98:	6878      	ldr	r0, [r7, #4]
 8003b9a:	f004 f93f 	bl	8007e1c <sniprintf>
                        break;
 8003b9e:	e017      	b.n	8003bd0 <Moto_FormatDisplay+0x140>
                        snprintf(buffer, 21, "^^^ WHEELIE ^^^");
 8003ba0:	4a19      	ldr	r2, [pc, #100]	@ (8003c08 <Moto_FormatDisplay+0x178>)
 8003ba2:	2115      	movs	r1, #21
 8003ba4:	6878      	ldr	r0, [r7, #4]
 8003ba6:	f004 f939 	bl	8007e1c <sniprintf>
                        break;
 8003baa:	e011      	b.n	8003bd0 <Moto_FormatDisplay+0x140>
                        snprintf(buffer, 21, "vvv STOPPIE vvv");
 8003bac:	4a17      	ldr	r2, [pc, #92]	@ (8003c0c <Moto_FormatDisplay+0x17c>)
 8003bae:	2115      	movs	r1, #21
 8003bb0:	6878      	ldr	r0, [r7, #4]
 8003bb2:	f004 f933 	bl	8007e1c <sniprintf>
                        break;
 8003bb6:	e00b      	b.n	8003bd0 <Moto_FormatDisplay+0x140>
                        snprintf(buffer, 21, ">>> VIRAGE <<<");
 8003bb8:	4a15      	ldr	r2, [pc, #84]	@ (8003c10 <Moto_FormatDisplay+0x180>)
 8003bba:	2115      	movs	r1, #21
 8003bbc:	6878      	ldr	r0, [r7, #4]
 8003bbe:	f004 f92d 	bl	8007e1c <sniprintf>
                        break;
 8003bc2:	e005      	b.n	8003bd0 <Moto_FormatDisplay+0x140>
                        snprintf(buffer, 21, "--- INCONNU ---");
 8003bc4:	4a13      	ldr	r2, [pc, #76]	@ (8003c14 <Moto_FormatDisplay+0x184>)
 8003bc6:	2115      	movs	r1, #21
 8003bc8:	6878      	ldr	r0, [r7, #4]
 8003bca:	f004 f927 	bl	8007e1c <sniprintf>
                        break;
 8003bce:	bf00      	nop
            break;
 8003bd0:	e005      	b.n	8003bde <Moto_FormatDisplay+0x14e>

        default:
            snprintf(buffer, 21, "Ligne invalide");
 8003bd2:	4a11      	ldr	r2, [pc, #68]	@ (8003c18 <Moto_FormatDisplay+0x188>)
 8003bd4:	2115      	movs	r1, #21
 8003bd6:	6878      	ldr	r0, [r7, #4]
 8003bd8:	f004 f920 	bl	8007e1c <sniprintf>
            break;
 8003bdc:	bf00      	nop
    }
}
 8003bde:	bf00      	nop
 8003be0:	3710      	adds	r7, #16
 8003be2:	46bd      	mov	sp, r7
 8003be4:	bdb0      	pop	{r4, r5, r7, pc}
 8003be6:	bf00      	nop
 8003be8:	0800b810 	.word	0x0800b810
 8003bec:	0800b820 	.word	0x0800b820
 8003bf0:	0800b830 	.word	0x0800b830
 8003bf4:	0800b83c 	.word	0x0800b83c
 8003bf8:	0800b854 	.word	0x0800b854
 8003bfc:	0800b868 	.word	0x0800b868
 8003c00:	0800b87c 	.word	0x0800b87c
 8003c04:	0800b890 	.word	0x0800b890
 8003c08:	0800b8a4 	.word	0x0800b8a4
 8003c0c:	0800b8b4 	.word	0x0800b8b4
 8003c10:	0800b8c4 	.word	0x0800b8c4
 8003c14:	0800b8d4 	.word	0x0800b8d4
 8003c18:	0800b8e4 	.word	0x0800b8e4

08003c1c <HAL_MspInit>:
/* USER CODE END 0 */
/**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 8003c1c:	b480      	push	{r7}
 8003c1e:	b083      	sub	sp, #12
 8003c20:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_SYSCFG_CLK_ENABLE();
 8003c22:	4b0f      	ldr	r3, [pc, #60]	@ (8003c60 <HAL_MspInit+0x44>)
 8003c24:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8003c26:	4a0e      	ldr	r2, [pc, #56]	@ (8003c60 <HAL_MspInit+0x44>)
 8003c28:	f043 0301 	orr.w	r3, r3, #1
 8003c2c:	6613      	str	r3, [r2, #96]	@ 0x60
 8003c2e:	4b0c      	ldr	r3, [pc, #48]	@ (8003c60 <HAL_MspInit+0x44>)
 8003c30:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8003c32:	f003 0301 	and.w	r3, r3, #1
 8003c36:	607b      	str	r3, [r7, #4]
 8003c38:	687b      	ldr	r3, [r7, #4]
  __HAL_RCC_PWR_CLK_ENABLE();
 8003c3a:	4b09      	ldr	r3, [pc, #36]	@ (8003c60 <HAL_MspInit+0x44>)
 8003c3c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8003c3e:	4a08      	ldr	r2, [pc, #32]	@ (8003c60 <HAL_MspInit+0x44>)
 8003c40:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 8003c44:	6593      	str	r3, [r2, #88]	@ 0x58
 8003c46:	4b06      	ldr	r3, [pc, #24]	@ (8003c60 <HAL_MspInit+0x44>)
 8003c48:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8003c4a:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8003c4e:	603b      	str	r3, [r7, #0]
 8003c50:	683b      	ldr	r3, [r7, #0]
  /* System interrupt init*/

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 8003c52:	bf00      	nop
 8003c54:	370c      	adds	r7, #12
 8003c56:	46bd      	mov	sp, r7
 8003c58:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003c5c:	4770      	bx	lr
 8003c5e:	bf00      	nop
 8003c60:	40021000 	.word	0x40021000

08003c64 <HAL_I2C_MspInit>:
  * This function configures the hardware resources used in this example
  * @param hi2c: I2C handle pointer
  * @retval None
  */
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
 8003c64:	b580      	push	{r7, lr}
 8003c66:	b0a4      	sub	sp, #144	@ 0x90
 8003c68:	af00      	add	r7, sp, #0
 8003c6a:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8003c6c:	f107 037c 	add.w	r3, r7, #124	@ 0x7c
 8003c70:	2200      	movs	r2, #0
 8003c72:	601a      	str	r2, [r3, #0]
 8003c74:	605a      	str	r2, [r3, #4]
 8003c76:	609a      	str	r2, [r3, #8]
 8003c78:	60da      	str	r2, [r3, #12]
 8003c7a:	611a      	str	r2, [r3, #16]
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 8003c7c:	f107 0314 	add.w	r3, r7, #20
 8003c80:	2268      	movs	r2, #104	@ 0x68
 8003c82:	2100      	movs	r1, #0
 8003c84:	4618      	mov	r0, r3
 8003c86:	f004 f942 	bl	8007f0e <memset>
  if(hi2c->Instance==I2C1)
 8003c8a:	687b      	ldr	r3, [r7, #4]
 8003c8c:	681b      	ldr	r3, [r3, #0]
 8003c8e:	4a21      	ldr	r2, [pc, #132]	@ (8003d14 <HAL_I2C_MspInit+0xb0>)
 8003c90:	4293      	cmp	r3, r2
 8003c92:	d13a      	bne.n	8003d0a <HAL_I2C_MspInit+0xa6>

    /* USER CODE END I2C1_MspInit 0 */

  /** Initializes the peripherals clock
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
 8003c94:	2340      	movs	r3, #64	@ 0x40
 8003c96:	617b      	str	r3, [r7, #20]
    PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
 8003c98:	2300      	movs	r3, #0
 8003c9a:	64bb      	str	r3, [r7, #72]	@ 0x48
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8003c9c:	f107 0314 	add.w	r3, r7, #20
 8003ca0:	4618      	mov	r0, r3
 8003ca2:	f002 fabb 	bl	800621c <HAL_RCCEx_PeriphCLKConfig>
 8003ca6:	4603      	mov	r3, r0
 8003ca8:	2b00      	cmp	r3, #0
 8003caa:	d001      	beq.n	8003cb0 <HAL_I2C_MspInit+0x4c>
    {
      Error_Handler();
 8003cac:	f7ff fcd6 	bl	800365c <Error_Handler>
    }

    __HAL_RCC_GPIOB_CLK_ENABLE();
 8003cb0:	4b19      	ldr	r3, [pc, #100]	@ (8003d18 <HAL_I2C_MspInit+0xb4>)
 8003cb2:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8003cb4:	4a18      	ldr	r2, [pc, #96]	@ (8003d18 <HAL_I2C_MspInit+0xb4>)
 8003cb6:	f043 0302 	orr.w	r3, r3, #2
 8003cba:	64d3      	str	r3, [r2, #76]	@ 0x4c
 8003cbc:	4b16      	ldr	r3, [pc, #88]	@ (8003d18 <HAL_I2C_MspInit+0xb4>)
 8003cbe:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8003cc0:	f003 0302 	and.w	r3, r3, #2
 8003cc4:	613b      	str	r3, [r7, #16]
 8003cc6:	693b      	ldr	r3, [r7, #16]
    /**I2C1 GPIO Configuration
    PB8     ------> I2C1_SCL
    PB9     ------> I2C1_SDA
    */
    GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
 8003cc8:	f44f 7340 	mov.w	r3, #768	@ 0x300
 8003ccc:	67fb      	str	r3, [r7, #124]	@ 0x7c
    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
 8003cce:	2312      	movs	r3, #18
 8003cd0:	f8c7 3080 	str.w	r3, [r7, #128]	@ 0x80
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8003cd4:	2300      	movs	r3, #0
 8003cd6:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8003cda:	2303      	movs	r3, #3
 8003cdc:	f8c7 3088 	str.w	r3, [r7, #136]	@ 0x88
    GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
 8003ce0:	2304      	movs	r3, #4
 8003ce2:	f8c7 308c 	str.w	r3, [r7, #140]	@ 0x8c
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8003ce6:	f107 037c 	add.w	r3, r7, #124	@ 0x7c
 8003cea:	4619      	mov	r1, r3
 8003cec:	480b      	ldr	r0, [pc, #44]	@ (8003d1c <HAL_I2C_MspInit+0xb8>)
 8003cee:	f000 fb2b 	bl	8004348 <HAL_GPIO_Init>

    /* Peripheral clock enable */
    __HAL_RCC_I2C1_CLK_ENABLE();
 8003cf2:	4b09      	ldr	r3, [pc, #36]	@ (8003d18 <HAL_I2C_MspInit+0xb4>)
 8003cf4:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8003cf6:	4a08      	ldr	r2, [pc, #32]	@ (8003d18 <HAL_I2C_MspInit+0xb4>)
 8003cf8:	f443 1300 	orr.w	r3, r3, #2097152	@ 0x200000
 8003cfc:	6593      	str	r3, [r2, #88]	@ 0x58
 8003cfe:	4b06      	ldr	r3, [pc, #24]	@ (8003d18 <HAL_I2C_MspInit+0xb4>)
 8003d00:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8003d02:	f403 1300 	and.w	r3, r3, #2097152	@ 0x200000
 8003d06:	60fb      	str	r3, [r7, #12]
 8003d08:	68fb      	ldr	r3, [r7, #12]

    /* USER CODE END I2C1_MspInit 1 */

  }

}
 8003d0a:	bf00      	nop
 8003d0c:	3790      	adds	r7, #144	@ 0x90
 8003d0e:	46bd      	mov	sp, r7
 8003d10:	bd80      	pop	{r7, pc}
 8003d12:	bf00      	nop
 8003d14:	40005400 	.word	0x40005400
 8003d18:	40021000 	.word	0x40021000
 8003d1c:	48000400 	.word	0x48000400

08003d20 <HAL_UART_MspInit>:
  * This function configures the hardware resources used in this example
  * @param huart: UART handle pointer
  * @retval None
  */
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 8003d20:	b580      	push	{r7, lr}
 8003d22:	b0a4      	sub	sp, #144	@ 0x90
 8003d24:	af00      	add	r7, sp, #0
 8003d26:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8003d28:	f107 037c 	add.w	r3, r7, #124	@ 0x7c
 8003d2c:	2200      	movs	r2, #0
 8003d2e:	601a      	str	r2, [r3, #0]
 8003d30:	605a      	str	r2, [r3, #4]
 8003d32:	609a      	str	r2, [r3, #8]
 8003d34:	60da      	str	r2, [r3, #12]
 8003d36:	611a      	str	r2, [r3, #16]
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 8003d38:	f107 0314 	add.w	r3, r7, #20
 8003d3c:	2268      	movs	r2, #104	@ 0x68
 8003d3e:	2100      	movs	r1, #0
 8003d40:	4618      	mov	r0, r3
 8003d42:	f004 f8e4 	bl	8007f0e <memset>
  if(huart->Instance==USART2)
 8003d46:	687b      	ldr	r3, [r7, #4]
 8003d48:	681b      	ldr	r3, [r3, #0]
 8003d4a:	4a21      	ldr	r2, [pc, #132]	@ (8003dd0 <HAL_UART_MspInit+0xb0>)
 8003d4c:	4293      	cmp	r3, r2
 8003d4e:	d13a      	bne.n	8003dc6 <HAL_UART_MspInit+0xa6>

    /* USER CODE END USART2_MspInit 0 */

  /** Initializes the peripherals clock
  */
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
 8003d50:	2302      	movs	r3, #2
 8003d52:	617b      	str	r3, [r7, #20]
    PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
 8003d54:	2300      	movs	r3, #0
 8003d56:	63bb      	str	r3, [r7, #56]	@ 0x38
    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8003d58:	f107 0314 	add.w	r3, r7, #20
 8003d5c:	4618      	mov	r0, r3
 8003d5e:	f002 fa5d 	bl	800621c <HAL_RCCEx_PeriphCLKConfig>
 8003d62:	4603      	mov	r3, r0
 8003d64:	2b00      	cmp	r3, #0
 8003d66:	d001      	beq.n	8003d6c <HAL_UART_MspInit+0x4c>
    {
      Error_Handler();
 8003d68:	f7ff fc78 	bl	800365c <Error_Handler>
    }

    /* Peripheral clock enable */
    __HAL_RCC_USART2_CLK_ENABLE();
 8003d6c:	4b19      	ldr	r3, [pc, #100]	@ (8003dd4 <HAL_UART_MspInit+0xb4>)
 8003d6e:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8003d70:	4a18      	ldr	r2, [pc, #96]	@ (8003dd4 <HAL_UART_MspInit+0xb4>)
 8003d72:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 8003d76:	6593      	str	r3, [r2, #88]	@ 0x58
 8003d78:	4b16      	ldr	r3, [pc, #88]	@ (8003dd4 <HAL_UART_MspInit+0xb4>)
 8003d7a:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8003d7c:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8003d80:	613b      	str	r3, [r7, #16]
 8003d82:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOA_CLK_ENABLE();
 8003d84:	4b13      	ldr	r3, [pc, #76]	@ (8003dd4 <HAL_UART_MspInit+0xb4>)
 8003d86:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8003d88:	4a12      	ldr	r2, [pc, #72]	@ (8003dd4 <HAL_UART_MspInit+0xb4>)
 8003d8a:	f043 0301 	orr.w	r3, r3, #1
 8003d8e:	64d3      	str	r3, [r2, #76]	@ 0x4c
 8003d90:	4b10      	ldr	r3, [pc, #64]	@ (8003dd4 <HAL_UART_MspInit+0xb4>)
 8003d92:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 8003d94:	f003 0301 	and.w	r3, r3, #1
 8003d98:	60fb      	str	r3, [r7, #12]
 8003d9a:	68fb      	ldr	r3, [r7, #12]
    /**USART2 GPIO Configuration
    PA2     ------> USART2_TX
    PA3     ------> USART2_RX
    */
    GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;
 8003d9c:	230c      	movs	r3, #12
 8003d9e:	67fb      	str	r3, [r7, #124]	@ 0x7c
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8003da0:	2302      	movs	r3, #2
 8003da2:	f8c7 3080 	str.w	r3, [r7, #128]	@ 0x80
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8003da6:	2300      	movs	r3, #0
 8003da8:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8003dac:	2303      	movs	r3, #3
 8003dae:	f8c7 3088 	str.w	r3, [r7, #136]	@ 0x88
    GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
 8003db2:	2307      	movs	r3, #7
 8003db4:	f8c7 308c 	str.w	r3, [r7, #140]	@ 0x8c
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8003db8:	f107 037c 	add.w	r3, r7, #124	@ 0x7c
 8003dbc:	4619      	mov	r1, r3
 8003dbe:	f04f 4090 	mov.w	r0, #1207959552	@ 0x48000000
 8003dc2:	f000 fac1 	bl	8004348 <HAL_GPIO_Init>

    /* USER CODE END USART2_MspInit 1 */

  }

}
 8003dc6:	bf00      	nop
 8003dc8:	3790      	adds	r7, #144	@ 0x90
 8003dca:	46bd      	mov	sp, r7
 8003dcc:	bd80      	pop	{r7, pc}
 8003dce:	bf00      	nop
 8003dd0:	40004400 	.word	0x40004400
 8003dd4:	40021000 	.word	0x40021000

08003dd8 <NMI_Handler>:
/******************************************************************************/
/**
  * @brief This function handles Non maskable interrupt.
  */
void NMI_Handler(void)
{
 8003dd8:	b480      	push	{r7}
 8003dda:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
   while (1)
 8003ddc:	bf00      	nop
 8003dde:	e7fd      	b.n	8003ddc <NMI_Handler+0x4>

08003de0 <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 8003de0:	b480      	push	{r7}
 8003de2:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 8003de4:	bf00      	nop
 8003de6:	e7fd      	b.n	8003de4 <HardFault_Handler+0x4>

08003de8 <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 8003de8:	b480      	push	{r7}
 8003dea:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MemoryManagement_IRQn 0 */

  /* USER CODE END MemoryManagement_IRQn 0 */
  while (1)
 8003dec:	bf00      	nop
 8003dee:	e7fd      	b.n	8003dec <MemManage_Handler+0x4>

08003df0 <BusFault_Handler>:

/**
  * @brief This function handles Prefetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 8003df0:	b480      	push	{r7}
 8003df2:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN BusFault_IRQn 0 */

  /* USER CODE END BusFault_IRQn 0 */
  while (1)
 8003df4:	bf00      	nop
 8003df6:	e7fd      	b.n	8003df4 <BusFault_Handler+0x4>

08003df8 <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 8003df8:	b480      	push	{r7}
 8003dfa:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN UsageFault_IRQn 0 */

  /* USER CODE END UsageFault_IRQn 0 */
  while (1)
 8003dfc:	bf00      	nop
 8003dfe:	e7fd      	b.n	8003dfc <UsageFault_Handler+0x4>

08003e00 <SVC_Handler>:

/**
  * @brief This function handles System service call via SWI instruction.
  */
void SVC_Handler(void)
{
 8003e00:	b480      	push	{r7}
 8003e02:	af00      	add	r7, sp, #0

  /* USER CODE END SVCall_IRQn 0 */
  /* USER CODE BEGIN SVCall_IRQn 1 */

  /* USER CODE END SVCall_IRQn 1 */
}
 8003e04:	bf00      	nop
 8003e06:	46bd      	mov	sp, r7
 8003e08:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003e0c:	4770      	bx	lr

08003e0e <DebugMon_Handler>:

/**
  * @brief This function handles Debug monitor.
  */
void DebugMon_Handler(void)
{
 8003e0e:	b480      	push	{r7}
 8003e10:	af00      	add	r7, sp, #0

  /* USER CODE END DebugMonitor_IRQn 0 */
  /* USER CODE BEGIN DebugMonitor_IRQn 1 */

  /* USER CODE END DebugMonitor_IRQn 1 */
}
 8003e12:	bf00      	nop
 8003e14:	46bd      	mov	sp, r7
 8003e16:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003e1a:	4770      	bx	lr

08003e1c <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 8003e1c:	b480      	push	{r7}
 8003e1e:	af00      	add	r7, sp, #0

  /* USER CODE END PendSV_IRQn 0 */
  /* USER CODE BEGIN PendSV_IRQn 1 */

  /* USER CODE END PendSV_IRQn 1 */
}
 8003e20:	bf00      	nop
 8003e22:	46bd      	mov	sp, r7
 8003e24:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003e28:	4770      	bx	lr

08003e2a <SysTick_Handler>:

/**
  * @brief This function handles System tick timer.
  */
void SysTick_Handler(void)
{
 8003e2a:	b580      	push	{r7, lr}
 8003e2c:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 8003e2e:	f000 f961 	bl	80040f4 <HAL_IncTick>
  /* USER CODE BEGIN SysTick_IRQn 1 */

  /* USER CODE END SysTick_IRQn 1 */
}
 8003e32:	bf00      	nop
 8003e34:	bd80      	pop	{r7, pc}

08003e36 <_getpid>:
void initialise_monitor_handles()
{
}

int _getpid(void)
{
 8003e36:	b480      	push	{r7}
 8003e38:	af00      	add	r7, sp, #0
  return 1;
 8003e3a:	2301      	movs	r3, #1
}
 8003e3c:	4618      	mov	r0, r3
 8003e3e:	46bd      	mov	sp, r7
 8003e40:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003e44:	4770      	bx	lr

08003e46 <_kill>:

int _kill(int pid, int sig)
{
 8003e46:	b580      	push	{r7, lr}
 8003e48:	b082      	sub	sp, #8
 8003e4a:	af00      	add	r7, sp, #0
 8003e4c:	6078      	str	r0, [r7, #4]
 8003e4e:	6039      	str	r1, [r7, #0]
  (void)pid;
  (void)sig;
  errno = EINVAL;
 8003e50:	f004 f8b0 	bl	8007fb4 <__errno>
 8003e54:	4603      	mov	r3, r0
 8003e56:	2216      	movs	r2, #22
 8003e58:	601a      	str	r2, [r3, #0]
  return -1;
 8003e5a:	f04f 33ff 	mov.w	r3, #4294967295
}
 8003e5e:	4618      	mov	r0, r3
 8003e60:	3708      	adds	r7, #8
 8003e62:	46bd      	mov	sp, r7
 8003e64:	bd80      	pop	{r7, pc}

08003e66 <_exit>:

void _exit (int status)
{
 8003e66:	b580      	push	{r7, lr}
 8003e68:	b082      	sub	sp, #8
 8003e6a:	af00      	add	r7, sp, #0
 8003e6c:	6078      	str	r0, [r7, #4]
  _kill(status, -1);
 8003e6e:	f04f 31ff 	mov.w	r1, #4294967295
 8003e72:	6878      	ldr	r0, [r7, #4]
 8003e74:	f7ff ffe7 	bl	8003e46 <_kill>
  while (1) {}    /* Make sure we hang here */
 8003e78:	bf00      	nop
 8003e7a:	e7fd      	b.n	8003e78 <_exit+0x12>

08003e7c <_read>:
}

__attribute__((weak)) int _read(int file, char *ptr, int len)
{
 8003e7c:	b580      	push	{r7, lr}
 8003e7e:	b086      	sub	sp, #24
 8003e80:	af00      	add	r7, sp, #0
 8003e82:	60f8      	str	r0, [r7, #12]
 8003e84:	60b9      	str	r1, [r7, #8]
 8003e86:	607a      	str	r2, [r7, #4]
  (void)file;
  int DataIdx;

  for (DataIdx = 0; DataIdx < len; DataIdx++)
 8003e88:	2300      	movs	r3, #0
 8003e8a:	617b      	str	r3, [r7, #20]
 8003e8c:	e00a      	b.n	8003ea4 <_read+0x28>
  {
    *ptr++ = __io_getchar();
 8003e8e:	f3af 8000 	nop.w
 8003e92:	4601      	mov	r1, r0
 8003e94:	68bb      	ldr	r3, [r7, #8]
 8003e96:	1c5a      	adds	r2, r3, #1
 8003e98:	60ba      	str	r2, [r7, #8]
 8003e9a:	b2ca      	uxtb	r2, r1
 8003e9c:	701a      	strb	r2, [r3, #0]
  for (DataIdx = 0; DataIdx < len; DataIdx++)
 8003e9e:	697b      	ldr	r3, [r7, #20]
 8003ea0:	3301      	adds	r3, #1
 8003ea2:	617b      	str	r3, [r7, #20]
 8003ea4:	697a      	ldr	r2, [r7, #20]
 8003ea6:	687b      	ldr	r3, [r7, #4]
 8003ea8:	429a      	cmp	r2, r3
 8003eaa:	dbf0      	blt.n	8003e8e <_read+0x12>
  }

  return len;
 8003eac:	687b      	ldr	r3, [r7, #4]
}
 8003eae:	4618      	mov	r0, r3
 8003eb0:	3718      	adds	r7, #24
 8003eb2:	46bd      	mov	sp, r7
 8003eb4:	bd80      	pop	{r7, pc}

08003eb6 <_write>:

__attribute__((weak)) int _write(int file, char *ptr, int len)
{
 8003eb6:	b580      	push	{r7, lr}
 8003eb8:	b086      	sub	sp, #24
 8003eba:	af00      	add	r7, sp, #0
 8003ebc:	60f8      	str	r0, [r7, #12]
 8003ebe:	60b9      	str	r1, [r7, #8]
 8003ec0:	607a      	str	r2, [r7, #4]
  (void)file;
  int DataIdx;

  for (DataIdx = 0; DataIdx < len; DataIdx++)
 8003ec2:	2300      	movs	r3, #0
 8003ec4:	617b      	str	r3, [r7, #20]
 8003ec6:	e009      	b.n	8003edc <_write+0x26>
  {
    __io_putchar(*ptr++);
 8003ec8:	68bb      	ldr	r3, [r7, #8]
 8003eca:	1c5a      	adds	r2, r3, #1
 8003ecc:	60ba      	str	r2, [r7, #8]
 8003ece:	781b      	ldrb	r3, [r3, #0]
 8003ed0:	4618      	mov	r0, r3
 8003ed2:	f7ff f801 	bl	8002ed8 <__io_putchar>
  for (DataIdx = 0; DataIdx < len; DataIdx++)
 8003ed6:	697b      	ldr	r3, [r7, #20]
 8003ed8:	3301      	adds	r3, #1
 8003eda:	617b      	str	r3, [r7, #20]
 8003edc:	697a      	ldr	r2, [r7, #20]
 8003ede:	687b      	ldr	r3, [r7, #4]
 8003ee0:	429a      	cmp	r2, r3
 8003ee2:	dbf1      	blt.n	8003ec8 <_write+0x12>
  }
  return len;
 8003ee4:	687b      	ldr	r3, [r7, #4]
}
 8003ee6:	4618      	mov	r0, r3
 8003ee8:	3718      	adds	r7, #24
 8003eea:	46bd      	mov	sp, r7
 8003eec:	bd80      	pop	{r7, pc}

08003eee <_close>:

int _close(int file)
{
 8003eee:	b480      	push	{r7}
 8003ef0:	b083      	sub	sp, #12
 8003ef2:	af00      	add	r7, sp, #0
 8003ef4:	6078      	str	r0, [r7, #4]
  (void)file;
  return -1;
 8003ef6:	f04f 33ff 	mov.w	r3, #4294967295
}
 8003efa:	4618      	mov	r0, r3
 8003efc:	370c      	adds	r7, #12
 8003efe:	46bd      	mov	sp, r7
 8003f00:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003f04:	4770      	bx	lr

08003f06 <_fstat>:


int _fstat(int file, struct stat *st)
{
 8003f06:	b480      	push	{r7}
 8003f08:	b083      	sub	sp, #12
 8003f0a:	af00      	add	r7, sp, #0
 8003f0c:	6078      	str	r0, [r7, #4]
 8003f0e:	6039      	str	r1, [r7, #0]
  (void)file;
  st->st_mode = S_IFCHR;
 8003f10:	683b      	ldr	r3, [r7, #0]
 8003f12:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
 8003f16:	605a      	str	r2, [r3, #4]
  return 0;
 8003f18:	2300      	movs	r3, #0
}
 8003f1a:	4618      	mov	r0, r3
 8003f1c:	370c      	adds	r7, #12
 8003f1e:	46bd      	mov	sp, r7
 8003f20:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003f24:	4770      	bx	lr

08003f26 <_isatty>:

int _isatty(int file)
{
 8003f26:	b480      	push	{r7}
 8003f28:	b083      	sub	sp, #12
 8003f2a:	af00      	add	r7, sp, #0
 8003f2c:	6078      	str	r0, [r7, #4]
  (void)file;
  return 1;
 8003f2e:	2301      	movs	r3, #1
}
 8003f30:	4618      	mov	r0, r3
 8003f32:	370c      	adds	r7, #12
 8003f34:	46bd      	mov	sp, r7
 8003f36:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003f3a:	4770      	bx	lr

08003f3c <_lseek>:

int _lseek(int file, int ptr, int dir)
{
 8003f3c:	b480      	push	{r7}
 8003f3e:	b085      	sub	sp, #20
 8003f40:	af00      	add	r7, sp, #0
 8003f42:	60f8      	str	r0, [r7, #12]
 8003f44:	60b9      	str	r1, [r7, #8]
 8003f46:	607a      	str	r2, [r7, #4]
  (void)file;
  (void)ptr;
  (void)dir;
  return 0;
 8003f48:	2300      	movs	r3, #0
}
 8003f4a:	4618      	mov	r0, r3
 8003f4c:	3714      	adds	r7, #20
 8003f4e:	46bd      	mov	sp, r7
 8003f50:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003f54:	4770      	bx	lr
	...

08003f58 <_sbrk>:
 *
 * @param incr Memory size
 * @return Pointer to allocated memory
 */
void *_sbrk(ptrdiff_t incr)
{
 8003f58:	b580      	push	{r7, lr}
 8003f5a:	b086      	sub	sp, #24
 8003f5c:	af00      	add	r7, sp, #0
 8003f5e:	6078      	str	r0, [r7, #4]
  extern uint8_t _end; /* Symbol defined in the linker script */
  extern uint8_t _estack; /* Symbol defined in the linker script */
  extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
  const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
 8003f60:	4a14      	ldr	r2, [pc, #80]	@ (8003fb4 <_sbrk+0x5c>)
 8003f62:	4b15      	ldr	r3, [pc, #84]	@ (8003fb8 <_sbrk+0x60>)
 8003f64:	1ad3      	subs	r3, r2, r3
 8003f66:	617b      	str	r3, [r7, #20]
  const uint8_t *max_heap = (uint8_t *)stack_limit;
 8003f68:	697b      	ldr	r3, [r7, #20]
 8003f6a:	613b      	str	r3, [r7, #16]
  uint8_t *prev_heap_end;

  /* Initialize heap end at first call */
  if (NULL == __sbrk_heap_end)
 8003f6c:	4b13      	ldr	r3, [pc, #76]	@ (8003fbc <_sbrk+0x64>)
 8003f6e:	681b      	ldr	r3, [r3, #0]
 8003f70:	2b00      	cmp	r3, #0
 8003f72:	d102      	bne.n	8003f7a <_sbrk+0x22>
  {
    __sbrk_heap_end = &_end;
 8003f74:	4b11      	ldr	r3, [pc, #68]	@ (8003fbc <_sbrk+0x64>)
 8003f76:	4a12      	ldr	r2, [pc, #72]	@ (8003fc0 <_sbrk+0x68>)
 8003f78:	601a      	str	r2, [r3, #0]
  }

  /* Protect heap from growing into the reserved MSP stack */
  if (__sbrk_heap_end + incr > max_heap)
 8003f7a:	4b10      	ldr	r3, [pc, #64]	@ (8003fbc <_sbrk+0x64>)
 8003f7c:	681a      	ldr	r2, [r3, #0]
 8003f7e:	687b      	ldr	r3, [r7, #4]
 8003f80:	4413      	add	r3, r2
 8003f82:	693a      	ldr	r2, [r7, #16]
 8003f84:	429a      	cmp	r2, r3
 8003f86:	d207      	bcs.n	8003f98 <_sbrk+0x40>
  {
    errno = ENOMEM;
 8003f88:	f004 f814 	bl	8007fb4 <__errno>
 8003f8c:	4603      	mov	r3, r0
 8003f8e:	220c      	movs	r2, #12
 8003f90:	601a      	str	r2, [r3, #0]
    return (void *)-1;
 8003f92:	f04f 33ff 	mov.w	r3, #4294967295
 8003f96:	e009      	b.n	8003fac <_sbrk+0x54>
  }

  prev_heap_end = __sbrk_heap_end;
 8003f98:	4b08      	ldr	r3, [pc, #32]	@ (8003fbc <_sbrk+0x64>)
 8003f9a:	681b      	ldr	r3, [r3, #0]
 8003f9c:	60fb      	str	r3, [r7, #12]
  __sbrk_heap_end += incr;
 8003f9e:	4b07      	ldr	r3, [pc, #28]	@ (8003fbc <_sbrk+0x64>)
 8003fa0:	681a      	ldr	r2, [r3, #0]
 8003fa2:	687b      	ldr	r3, [r7, #4]
 8003fa4:	4413      	add	r3, r2
 8003fa6:	4a05      	ldr	r2, [pc, #20]	@ (8003fbc <_sbrk+0x64>)
 8003fa8:	6013      	str	r3, [r2, #0]

  return (void *)prev_heap_end;
 8003faa:	68fb      	ldr	r3, [r7, #12]
}
 8003fac:	4618      	mov	r0, r3
 8003fae:	3718      	adds	r7, #24
 8003fb0:	46bd      	mov	sp, r7
 8003fb2:	bd80      	pop	{r7, pc}
 8003fb4:	20020000 	.word	0x20020000
 8003fb8:	00000800 	.word	0x00000800
 8003fbc:	2000039c 	.word	0x2000039c
 8003fc0:	200004f0 	.word	0x200004f0

08003fc4 <SystemInit>:
  * @brief  Setup the microcontroller system.
  * @retval None
  */

void SystemInit(void)
{
 8003fc4:	b480      	push	{r7}
 8003fc6:	af00      	add	r7, sp, #0
  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
#endif

  /* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  SCB->CPACR |= ((3UL << 20U)|(3UL << 22U));  /* set CP10 and CP11 Full Access */
 8003fc8:	4b06      	ldr	r3, [pc, #24]	@ (8003fe4 <SystemInit+0x20>)
 8003fca:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8003fce:	4a05      	ldr	r2, [pc, #20]	@ (8003fe4 <SystemInit+0x20>)
 8003fd0:	f443 0370 	orr.w	r3, r3, #15728640	@ 0xf00000
 8003fd4:	f8c2 3088 	str.w	r3, [r2, #136]	@ 0x88
#endif
}
 8003fd8:	bf00      	nop
 8003fda:	46bd      	mov	sp, r7
 8003fdc:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003fe0:	4770      	bx	lr
 8003fe2:	bf00      	nop
 8003fe4:	e000ed00 	.word	0xe000ed00

08003fe8 <Reset_Handler>:

    .section	.text.Reset_Handler
	.weak	Reset_Handler
	.type	Reset_Handler, %function
Reset_Handler:
  ldr   sp, =_estack    /* Set stack pointer */
 8003fe8:	f8df d034 	ldr.w	sp, [pc, #52]	@ 8004020 <LoopForever+0x2>

/* Call the clock system initialization function.*/
    bl  SystemInit
 8003fec:	f7ff ffea 	bl	8003fc4 <SystemInit>

/* Copy the data segment initializers from flash to SRAM */
  ldr r0, =_sdata
 8003ff0:	480c      	ldr	r0, [pc, #48]	@ (8004024 <LoopForever+0x6>)
  ldr r1, =_edata
 8003ff2:	490d      	ldr	r1, [pc, #52]	@ (8004028 <LoopForever+0xa>)
  ldr r2, =_sidata
 8003ff4:	4a0d      	ldr	r2, [pc, #52]	@ (800402c <LoopForever+0xe>)
  movs r3, #0
 8003ff6:	2300      	movs	r3, #0
  b LoopCopyDataInit
 8003ff8:	e002      	b.n	8004000 <LoopCopyDataInit>

08003ffa <CopyDataInit>:

CopyDataInit:
  ldr r4, [r2, r3]
 8003ffa:	58d4      	ldr	r4, [r2, r3]
  str r4, [r0, r3]
 8003ffc:	50c4      	str	r4, [r0, r3]
  adds r3, r3, #4
 8003ffe:	3304      	adds	r3, #4

08004000 <LoopCopyDataInit>:

LoopCopyDataInit:
  adds r4, r0, r3
 8004000:	18c4      	adds	r4, r0, r3
  cmp r4, r1
 8004002:	428c      	cmp	r4, r1
  bcc CopyDataInit
 8004004:	d3f9      	bcc.n	8003ffa <CopyDataInit>
  
/* Zero fill the bss segment. */
  ldr r2, =_sbss
 8004006:	4a0a      	ldr	r2, [pc, #40]	@ (8004030 <LoopForever+0x12>)
  ldr r4, =_ebss
 8004008:	4c0a      	ldr	r4, [pc, #40]	@ (8004034 <LoopForever+0x16>)
  movs r3, #0
 800400a:	2300      	movs	r3, #0
  b LoopFillZerobss
 800400c:	e001      	b.n	8004012 <LoopFillZerobss>

0800400e <FillZerobss>:

FillZerobss:
  str  r3, [r2]
 800400e:	6013      	str	r3, [r2, #0]
  adds r2, r2, #4
 8004010:	3204      	adds	r2, #4

08004012 <LoopFillZerobss>:

LoopFillZerobss:
  cmp r2, r4
 8004012:	42a2      	cmp	r2, r4
  bcc FillZerobss
 8004014:	d3fb      	bcc.n	800400e <FillZerobss>

/* Call static constructors */
    bl __libc_init_array
 8004016:	f003 ffd3 	bl	8007fc0 <__libc_init_array>
/* Call the application's entry point.*/
	bl	main
 800401a:	f7fe ff6f 	bl	8002efc <main>

0800401e <LoopForever>:

LoopForever:
    b LoopForever
 800401e:	e7fe      	b.n	800401e <LoopForever>
  ldr   sp, =_estack    /* Set stack pointer */
 8004020:	20020000 	.word	0x20020000
  ldr r0, =_sdata
 8004024:	20000000 	.word	0x20000000
  ldr r1, =_edata
 8004028:	200001d4 	.word	0x200001d4
  ldr r2, =_sidata
 800402c:	0800c0e4 	.word	0x0800c0e4
  ldr r2, =_sbss
 8004030:	200001d4 	.word	0x200001d4
  ldr r4, =_ebss
 8004034:	200004f0 	.word	0x200004f0

08004038 <ADC1_IRQHandler>:
 * @retval : None
*/
    .section	.text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
	b	Infinite_Loop
 8004038:	e7fe      	b.n	8004038 <ADC1_IRQHandler>
	...

0800403c <HAL_Init>:
  *         each 1ms in the SysTick_Handler() interrupt handler.
  *
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_Init(void)
{
 800403c:	b580      	push	{r7, lr}
 800403e:	b082      	sub	sp, #8
 8004040:	af00      	add	r7, sp, #0
  HAL_StatusTypeDef  status = HAL_OK;
 8004042:	2300      	movs	r3, #0
 8004044:	71fb      	strb	r3, [r7, #7]
#if (DATA_CACHE_ENABLE == 0)
   __HAL_FLASH_DATA_CACHE_DISABLE();
#endif /* DATA_CACHE_ENABLE */

#if (PREFETCH_ENABLE != 0)
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8004046:	4b0c      	ldr	r3, [pc, #48]	@ (8004078 <HAL_Init+0x3c>)
 8004048:	681b      	ldr	r3, [r3, #0]
 800404a:	4a0b      	ldr	r2, [pc, #44]	@ (8004078 <HAL_Init+0x3c>)
 800404c:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 8004050:	6013      	str	r3, [r2, #0]
#endif /* PREFETCH_ENABLE */

  /* Set Interrupt Group Priority */
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 8004052:	2003      	movs	r0, #3
 8004054:	f000 f944 	bl	80042e0 <HAL_NVIC_SetPriorityGrouping>

  /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
 8004058:	2000      	movs	r0, #0
 800405a:	f000 f80f 	bl	800407c <HAL_InitTick>
 800405e:	4603      	mov	r3, r0
 8004060:	2b00      	cmp	r3, #0
 8004062:	d002      	beq.n	800406a <HAL_Init+0x2e>
  {
    status = HAL_ERROR;
 8004064:	2301      	movs	r3, #1
 8004066:	71fb      	strb	r3, [r7, #7]
 8004068:	e001      	b.n	800406e <HAL_Init+0x32>
  }
  else
  {
    /* Init the low level hardware */
    HAL_MspInit();
 800406a:	f7ff fdd7 	bl	8003c1c <HAL_MspInit>
  }

  /* Return function status */
  return status;
 800406e:	79fb      	ldrb	r3, [r7, #7]
}
 8004070:	4618      	mov	r0, r3
 8004072:	3708      	adds	r7, #8
 8004074:	46bd      	mov	sp, r7
 8004076:	bd80      	pop	{r7, pc}
 8004078:	40022000 	.word	0x40022000

0800407c <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority  Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 800407c:	b580      	push	{r7, lr}
 800407e:	b084      	sub	sp, #16
 8004080:	af00      	add	r7, sp, #0
 8004082:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef  status = HAL_OK;
 8004084:	2300      	movs	r3, #0
 8004086:	73fb      	strb	r3, [r7, #15]

  /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
  if ((uint32_t)uwTickFreq != 0U)
 8004088:	4b17      	ldr	r3, [pc, #92]	@ (80040e8 <HAL_InitTick+0x6c>)
 800408a:	781b      	ldrb	r3, [r3, #0]
 800408c:	2b00      	cmp	r3, #0
 800408e:	d023      	beq.n	80040d8 <HAL_InitTick+0x5c>
  {
    /*Configure the SysTick to have interrupt in 1ms time basis*/
    if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
 8004090:	4b16      	ldr	r3, [pc, #88]	@ (80040ec <HAL_InitTick+0x70>)
 8004092:	681a      	ldr	r2, [r3, #0]
 8004094:	4b14      	ldr	r3, [pc, #80]	@ (80040e8 <HAL_InitTick+0x6c>)
 8004096:	781b      	ldrb	r3, [r3, #0]
 8004098:	4619      	mov	r1, r3
 800409a:	f44f 737a 	mov.w	r3, #1000	@ 0x3e8
 800409e:	fbb3 f3f1 	udiv	r3, r3, r1
 80040a2:	fbb2 f3f3 	udiv	r3, r2, r3
 80040a6:	4618      	mov	r0, r3
 80040a8:	f000 f941 	bl	800432e <HAL_SYSTICK_Config>
 80040ac:	4603      	mov	r3, r0
 80040ae:	2b00      	cmp	r3, #0
 80040b0:	d10f      	bne.n	80040d2 <HAL_InitTick+0x56>
    {
      /* Configure the SysTick IRQ priority */
      if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 80040b2:	687b      	ldr	r3, [r7, #4]
 80040b4:	2b0f      	cmp	r3, #15
 80040b6:	d809      	bhi.n	80040cc <HAL_InitTick+0x50>
      {
        HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 80040b8:	2200      	movs	r2, #0
 80040ba:	6879      	ldr	r1, [r7, #4]
 80040bc:	f04f 30ff 	mov.w	r0, #4294967295
 80040c0:	f000 f919 	bl	80042f6 <HAL_NVIC_SetPriority>
        uwTickPrio = TickPriority;
 80040c4:	4a0a      	ldr	r2, [pc, #40]	@ (80040f0 <HAL_InitTick+0x74>)
 80040c6:	687b      	ldr	r3, [r7, #4]
 80040c8:	6013      	str	r3, [r2, #0]
 80040ca:	e007      	b.n	80040dc <HAL_InitTick+0x60>
      }
      else
      {
        status = HAL_ERROR;
 80040cc:	2301      	movs	r3, #1
 80040ce:	73fb      	strb	r3, [r7, #15]
 80040d0:	e004      	b.n	80040dc <HAL_InitTick+0x60>
      }
    }
    else
    {
      status = HAL_ERROR;
 80040d2:	2301      	movs	r3, #1
 80040d4:	73fb      	strb	r3, [r7, #15]
 80040d6:	e001      	b.n	80040dc <HAL_InitTick+0x60>
    }
  }
  else
  {
    status = HAL_ERROR;
 80040d8:	2301      	movs	r3, #1
 80040da:	73fb      	strb	r3, [r7, #15]
  }

  /* Return function status */
  return status;
 80040dc:	7bfb      	ldrb	r3, [r7, #15]
}
 80040de:	4618      	mov	r0, r3
 80040e0:	3710      	adds	r7, #16
 80040e2:	46bd      	mov	sp, r7
 80040e4:	bd80      	pop	{r7, pc}
 80040e6:	bf00      	nop
 80040e8:	20000008 	.word	0x20000008
 80040ec:	20000000 	.word	0x20000000
 80040f0:	20000004 	.word	0x20000004

080040f4 <HAL_IncTick>:
 * @note This function is declared as __weak to be overwritten in case of other
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
 80040f4:	b480      	push	{r7}
 80040f6:	af00      	add	r7, sp, #0
  uwTick += (uint32_t)uwTickFreq;
 80040f8:	4b06      	ldr	r3, [pc, #24]	@ (8004114 <HAL_IncTick+0x20>)
 80040fa:	781b      	ldrb	r3, [r3, #0]
 80040fc:	461a      	mov	r2, r3
 80040fe:	4b06      	ldr	r3, [pc, #24]	@ (8004118 <HAL_IncTick+0x24>)
 8004100:	681b      	ldr	r3, [r3, #0]
 8004102:	4413      	add	r3, r2
 8004104:	4a04      	ldr	r2, [pc, #16]	@ (8004118 <HAL_IncTick+0x24>)
 8004106:	6013      	str	r3, [r2, #0]
}
 8004108:	bf00      	nop
 800410a:	46bd      	mov	sp, r7
 800410c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004110:	4770      	bx	lr
 8004112:	bf00      	nop
 8004114:	20000008 	.word	0x20000008
 8004118:	200003a0 	.word	0x200003a0

0800411c <HAL_GetTick>:
  * @note This function is declared as __weak to be overwritten in case of other
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
 800411c:	b480      	push	{r7}
 800411e:	af00      	add	r7, sp, #0
  return uwTick;
 8004120:	4b03      	ldr	r3, [pc, #12]	@ (8004130 <HAL_GetTick+0x14>)
 8004122:	681b      	ldr	r3, [r3, #0]
}
 8004124:	4618      	mov	r0, r3
 8004126:	46bd      	mov	sp, r7
 8004128:	f85d 7b04 	ldr.w	r7, [sp], #4
 800412c:	4770      	bx	lr
 800412e:	bf00      	nop
 8004130:	200003a0 	.word	0x200003a0

08004134 <HAL_Delay>:
  *       implementations in user file.
  * @param Delay  specifies the delay time length, in milliseconds.
  * @retval None
  */
__weak void HAL_Delay(uint32_t Delay)
{
 8004134:	b580      	push	{r7, lr}
 8004136:	b084      	sub	sp, #16
 8004138:	af00      	add	r7, sp, #0
 800413a:	6078      	str	r0, [r7, #4]
  uint32_t tickstart = HAL_GetTick();
 800413c:	f7ff ffee 	bl	800411c <HAL_GetTick>
 8004140:	60b8      	str	r0, [r7, #8]
  uint32_t wait = Delay;
 8004142:	687b      	ldr	r3, [r7, #4]
 8004144:	60fb      	str	r3, [r7, #12]

  /* Add a period to guaranty minimum wait */
  if (wait < HAL_MAX_DELAY)
 8004146:	68fb      	ldr	r3, [r7, #12]
 8004148:	f1b3 3fff 	cmp.w	r3, #4294967295
 800414c:	d005      	beq.n	800415a <HAL_Delay+0x26>
  {
    wait += (uint32_t)uwTickFreq;
 800414e:	4b0a      	ldr	r3, [pc, #40]	@ (8004178 <HAL_Delay+0x44>)
 8004150:	781b      	ldrb	r3, [r3, #0]
 8004152:	461a      	mov	r2, r3
 8004154:	68fb      	ldr	r3, [r7, #12]
 8004156:	4413      	add	r3, r2
 8004158:	60fb      	str	r3, [r7, #12]
  }

  while ((HAL_GetTick() - tickstart) < wait)
 800415a:	bf00      	nop
 800415c:	f7ff ffde 	bl	800411c <HAL_GetTick>
 8004160:	4602      	mov	r2, r0
 8004162:	68bb      	ldr	r3, [r7, #8]
 8004164:	1ad3      	subs	r3, r2, r3
 8004166:	68fa      	ldr	r2, [r7, #12]
 8004168:	429a      	cmp	r2, r3
 800416a:	d8f7      	bhi.n	800415c <HAL_Delay+0x28>
  {
  }
}
 800416c:	bf00      	nop
 800416e:	bf00      	nop
 8004170:	3710      	adds	r7, #16
 8004172:	46bd      	mov	sp, r7
 8004174:	bd80      	pop	{r7, pc}
 8004176:	bf00      	nop
 8004178:	20000008 	.word	0x20000008

0800417c <__NVIC_SetPriorityGrouping>:
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]      PriorityGroup  Priority grouping field.
 */
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 800417c:	b480      	push	{r7}
 800417e:	b085      	sub	sp, #20
 8004180:	af00      	add	r7, sp, #0
 8004182:	6078      	str	r0, [r7, #4]
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 8004184:	687b      	ldr	r3, [r7, #4]
 8004186:	f003 0307 	and.w	r3, r3, #7
 800418a:	60fb      	str	r3, [r7, #12]

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 800418c:	4b0c      	ldr	r3, [pc, #48]	@ (80041c0 <__NVIC_SetPriorityGrouping+0x44>)
 800418e:	68db      	ldr	r3, [r3, #12]
 8004190:	60bb      	str	r3, [r7, #8]
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 8004192:	68ba      	ldr	r2, [r7, #8]
 8004194:	f64f 03ff 	movw	r3, #63743	@ 0xf8ff
 8004198:	4013      	ands	r3, r2
 800419a:	60bb      	str	r3, [r7, #8]
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
 800419c:	68fb      	ldr	r3, [r7, #12]
 800419e:	021a      	lsls	r2, r3, #8
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 80041a0:	68bb      	ldr	r3, [r7, #8]
 80041a2:	4313      	orrs	r3, r2
  reg_value  =  (reg_value                                   |
 80041a4:	f043 63bf 	orr.w	r3, r3, #100139008	@ 0x5f80000
 80041a8:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
 80041ac:	60bb      	str	r3, [r7, #8]
  SCB->AIRCR =  reg_value;
 80041ae:	4a04      	ldr	r2, [pc, #16]	@ (80041c0 <__NVIC_SetPriorityGrouping+0x44>)
 80041b0:	68bb      	ldr	r3, [r7, #8]
 80041b2:	60d3      	str	r3, [r2, #12]
}
 80041b4:	bf00      	nop
 80041b6:	3714      	adds	r7, #20
 80041b8:	46bd      	mov	sp, r7
 80041ba:	f85d 7b04 	ldr.w	r7, [sp], #4
 80041be:	4770      	bx	lr
 80041c0:	e000ed00 	.word	0xe000ed00

080041c4 <__NVIC_GetPriorityGrouping>:
  \brief   Get Priority Grouping
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
 80041c4:	b480      	push	{r7}
 80041c6:	af00      	add	r7, sp, #0
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 80041c8:	4b04      	ldr	r3, [pc, #16]	@ (80041dc <__NVIC_GetPriorityGrouping+0x18>)
 80041ca:	68db      	ldr	r3, [r3, #12]
 80041cc:	0a1b      	lsrs	r3, r3, #8
 80041ce:	f003 0307 	and.w	r3, r3, #7
}
 80041d2:	4618      	mov	r0, r3
 80041d4:	46bd      	mov	sp, r7
 80041d6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80041da:	4770      	bx	lr
 80041dc:	e000ed00 	.word	0xe000ed00

080041e0 <__NVIC_SetPriority>:
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
 80041e0:	b480      	push	{r7}
 80041e2:	b083      	sub	sp, #12
 80041e4:	af00      	add	r7, sp, #0
 80041e6:	4603      	mov	r3, r0
 80041e8:	6039      	str	r1, [r7, #0]
 80041ea:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 80041ec:	f997 3007 	ldrsb.w	r3, [r7, #7]
 80041f0:	2b00      	cmp	r3, #0
 80041f2:	db0a      	blt.n	800420a <__NVIC_SetPriority+0x2a>
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80041f4:	683b      	ldr	r3, [r7, #0]
 80041f6:	b2da      	uxtb	r2, r3
 80041f8:	490c      	ldr	r1, [pc, #48]	@ (800422c <__NVIC_SetPriority+0x4c>)
 80041fa:	f997 3007 	ldrsb.w	r3, [r7, #7]
 80041fe:	0112      	lsls	r2, r2, #4
 8004200:	b2d2      	uxtb	r2, r2
 8004202:	440b      	add	r3, r1
 8004204:	f883 2300 	strb.w	r2, [r3, #768]	@ 0x300
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  }
}
 8004208:	e00a      	b.n	8004220 <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800420a:	683b      	ldr	r3, [r7, #0]
 800420c:	b2da      	uxtb	r2, r3
 800420e:	4908      	ldr	r1, [pc, #32]	@ (8004230 <__NVIC_SetPriority+0x50>)
 8004210:	79fb      	ldrb	r3, [r7, #7]
 8004212:	f003 030f 	and.w	r3, r3, #15
 8004216:	3b04      	subs	r3, #4
 8004218:	0112      	lsls	r2, r2, #4
 800421a:	b2d2      	uxtb	r2, r2
 800421c:	440b      	add	r3, r1
 800421e:	761a      	strb	r2, [r3, #24]
}
 8004220:	bf00      	nop
 8004222:	370c      	adds	r7, #12
 8004224:	46bd      	mov	sp, r7
 8004226:	f85d 7b04 	ldr.w	r7, [sp], #4
 800422a:	4770      	bx	lr
 800422c:	e000e100 	.word	0xe000e100
 8004230:	e000ed00 	.word	0xe000ed00

08004234 <NVIC_EncodePriority>:
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8004234:	b480      	push	{r7}
 8004236:	b089      	sub	sp, #36	@ 0x24
 8004238:	af00      	add	r7, sp, #0
 800423a:	60f8      	str	r0, [r7, #12]
 800423c:	60b9      	str	r1, [r7, #8]
 800423e:	607a      	str	r2, [r7, #4]
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
 8004240:	68fb      	ldr	r3, [r7, #12]
 8004242:	f003 0307 	and.w	r3, r3, #7
 8004246:	61fb      	str	r3, [r7, #28]
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8004248:	69fb      	ldr	r3, [r7, #28]
 800424a:	f1c3 0307 	rsb	r3, r3, #7
 800424e:	2b04      	cmp	r3, #4
 8004250:	bf28      	it	cs
 8004252:	2304      	movcs	r3, #4
 8004254:	61bb      	str	r3, [r7, #24]
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8004256:	69fb      	ldr	r3, [r7, #28]
 8004258:	3304      	adds	r3, #4
 800425a:	2b06      	cmp	r3, #6
 800425c:	d902      	bls.n	8004264 <NVIC_EncodePriority+0x30>
 800425e:	69fb      	ldr	r3, [r7, #28]
 8004260:	3b03      	subs	r3, #3
 8004262:	e000      	b.n	8004266 <NVIC_EncodePriority+0x32>
 8004264:	2300      	movs	r3, #0
 8004266:	617b      	str	r3, [r7, #20]

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8004268:	f04f 32ff 	mov.w	r2, #4294967295
 800426c:	69bb      	ldr	r3, [r7, #24]
 800426e:	fa02 f303 	lsl.w	r3, r2, r3
 8004272:	43da      	mvns	r2, r3
 8004274:	68bb      	ldr	r3, [r7, #8]
 8004276:	401a      	ands	r2, r3
 8004278:	697b      	ldr	r3, [r7, #20]
 800427a:	409a      	lsls	r2, r3
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 800427c:	f04f 31ff 	mov.w	r1, #4294967295
 8004280:	697b      	ldr	r3, [r7, #20]
 8004282:	fa01 f303 	lsl.w	r3, r1, r3
 8004286:	43d9      	mvns	r1, r3
 8004288:	687b      	ldr	r3, [r7, #4]
 800428a:	400b      	ands	r3, r1
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 800428c:	4313      	orrs	r3, r2
         );
}
 800428e:	4618      	mov	r0, r3
 8004290:	3724      	adds	r7, #36	@ 0x24
 8004292:	46bd      	mov	sp, r7
 8004294:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004298:	4770      	bx	lr
	...

0800429c <SysTick_Config>:
  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
 800429c:	b580      	push	{r7, lr}
 800429e:	b082      	sub	sp, #8
 80042a0:	af00      	add	r7, sp, #0
 80042a2:	6078      	str	r0, [r7, #4]
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 80042a4:	687b      	ldr	r3, [r7, #4]
 80042a6:	3b01      	subs	r3, #1
 80042a8:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
 80042ac:	d301      	bcc.n	80042b2 <SysTick_Config+0x16>
  {
    return (1UL);                                                   /* Reload value impossible */
 80042ae:	2301      	movs	r3, #1
 80042b0:	e00f      	b.n	80042d2 <SysTick_Config+0x36>
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 80042b2:	4a0a      	ldr	r2, [pc, #40]	@ (80042dc <SysTick_Config+0x40>)
 80042b4:	687b      	ldr	r3, [r7, #4]
 80042b6:	3b01      	subs	r3, #1
 80042b8:	6053      	str	r3, [r2, #4]
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
 80042ba:	210f      	movs	r1, #15
 80042bc:	f04f 30ff 	mov.w	r0, #4294967295
 80042c0:	f7ff ff8e 	bl	80041e0 <__NVIC_SetPriority>
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 80042c4:	4b05      	ldr	r3, [pc, #20]	@ (80042dc <SysTick_Config+0x40>)
 80042c6:	2200      	movs	r2, #0
 80042c8:	609a      	str	r2, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 80042ca:	4b04      	ldr	r3, [pc, #16]	@ (80042dc <SysTick_Config+0x40>)
 80042cc:	2207      	movs	r2, #7
 80042ce:	601a      	str	r2, [r3, #0]
                   SysTick_CTRL_TICKINT_Msk   |
                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                     /* Function successful */
 80042d0:	2300      	movs	r3, #0
}
 80042d2:	4618      	mov	r0, r3
 80042d4:	3708      	adds	r7, #8
 80042d6:	46bd      	mov	sp, r7
 80042d8:	bd80      	pop	{r7, pc}
 80042da:	bf00      	nop
 80042dc:	e000e010 	.word	0xe000e010

080042e0 <HAL_NVIC_SetPriorityGrouping>:
  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
  *         The pending IRQ priority will be managed only by the subpriority.
  * @retval None
  */
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 80042e0:	b580      	push	{r7, lr}
 80042e2:	b082      	sub	sp, #8
 80042e4:	af00      	add	r7, sp, #0
 80042e6:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));

  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  NVIC_SetPriorityGrouping(PriorityGroup);
 80042e8:	6878      	ldr	r0, [r7, #4]
 80042ea:	f7ff ff47 	bl	800417c <__NVIC_SetPriorityGrouping>
}
 80042ee:	bf00      	nop
 80042f0:	3708      	adds	r7, #8
 80042f2:	46bd      	mov	sp, r7
 80042f4:	bd80      	pop	{r7, pc}

080042f6 <HAL_NVIC_SetPriority>:
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
 80042f6:	b580      	push	{r7, lr}
 80042f8:	b086      	sub	sp, #24
 80042fa:	af00      	add	r7, sp, #0
 80042fc:	4603      	mov	r3, r0
 80042fe:	60b9      	str	r1, [r7, #8]
 8004300:	607a      	str	r2, [r7, #4]
 8004302:	73fb      	strb	r3, [r7, #15]
  uint32_t prioritygroup = 0x00;
 8004304:	2300      	movs	r3, #0
 8004306:	617b      	str	r3, [r7, #20]

  /* Check the parameters */
  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));

  prioritygroup = NVIC_GetPriorityGrouping();
 8004308:	f7ff ff5c 	bl	80041c4 <__NVIC_GetPriorityGrouping>
 800430c:	6178      	str	r0, [r7, #20]

  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 800430e:	687a      	ldr	r2, [r7, #4]
 8004310:	68b9      	ldr	r1, [r7, #8]
 8004312:	6978      	ldr	r0, [r7, #20]
 8004314:	f7ff ff8e 	bl	8004234 <NVIC_EncodePriority>
 8004318:	4602      	mov	r2, r0
 800431a:	f997 300f 	ldrsb.w	r3, [r7, #15]
 800431e:	4611      	mov	r1, r2
 8004320:	4618      	mov	r0, r3
 8004322:	f7ff ff5d 	bl	80041e0 <__NVIC_SetPriority>
}
 8004326:	bf00      	nop
 8004328:	3718      	adds	r7, #24
 800432a:	46bd      	mov	sp, r7
 800432c:	bd80      	pop	{r7, pc}

0800432e <HAL_SYSTICK_Config>:
  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
  * @retval status:  - 0  Function succeeded.
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
 800432e:	b580      	push	{r7, lr}
 8004330:	b082      	sub	sp, #8
 8004332:	af00      	add	r7, sp, #0
 8004334:	6078      	str	r0, [r7, #4]
   return SysTick_Config(TicksNumb);
 8004336:	6878      	ldr	r0, [r7, #4]
 8004338:	f7ff ffb0 	bl	800429c <SysTick_Config>
 800433c:	4603      	mov	r3, r0
}
 800433e:	4618      	mov	r0, r3
 8004340:	3708      	adds	r7, #8
 8004342:	46bd      	mov	sp, r7
 8004344:	bd80      	pop	{r7, pc}
	...

08004348 <HAL_GPIO_Init>:
  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 8004348:	b480      	push	{r7}
 800434a:	b087      	sub	sp, #28
 800434c:	af00      	add	r7, sp, #0
 800434e:	6078      	str	r0, [r7, #4]
 8004350:	6039      	str	r1, [r7, #0]
  uint32_t position = 0x00u;
 8004352:	2300      	movs	r3, #0
 8004354:	617b      	str	r3, [r7, #20]
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 8004356:	e154      	b.n	8004602 <HAL_GPIO_Init+0x2ba>
  {
    /* Get current io position */
    iocurrent = (GPIO_Init->Pin) & (1uL << position);
 8004358:	683b      	ldr	r3, [r7, #0]
 800435a:	681a      	ldr	r2, [r3, #0]
 800435c:	2101      	movs	r1, #1
 800435e:	697b      	ldr	r3, [r7, #20]
 8004360:	fa01 f303 	lsl.w	r3, r1, r3
 8004364:	4013      	ands	r3, r2
 8004366:	60fb      	str	r3, [r7, #12]

    if (iocurrent != 0x00u)
 8004368:	68fb      	ldr	r3, [r7, #12]
 800436a:	2b00      	cmp	r3, #0
 800436c:	f000 8146 	beq.w	80045fc <HAL_GPIO_Init+0x2b4>
    {
      /*--------------------- GPIO Mode Configuration ------------------------*/
      /* In case of Output or Alternate function mode selection */
      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
 8004370:	683b      	ldr	r3, [r7, #0]
 8004372:	685b      	ldr	r3, [r3, #4]
 8004374:	f003 0303 	and.w	r3, r3, #3
 8004378:	2b01      	cmp	r3, #1
 800437a:	d005      	beq.n	8004388 <HAL_GPIO_Init+0x40>
 800437c:	683b      	ldr	r3, [r7, #0]
 800437e:	685b      	ldr	r3, [r3, #4]
 8004380:	f003 0303 	and.w	r3, r3, #3
 8004384:	2b02      	cmp	r3, #2
 8004386:	d130      	bne.n	80043ea <HAL_GPIO_Init+0xa2>
      {
        /* Check the Speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));

        /* Configure the IO Speed */
        temp = GPIOx->OSPEEDR;
 8004388:	687b      	ldr	r3, [r7, #4]
 800438a:	689b      	ldr	r3, [r3, #8]
 800438c:	613b      	str	r3, [r7, #16]
        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
 800438e:	697b      	ldr	r3, [r7, #20]
 8004390:	005b      	lsls	r3, r3, #1
 8004392:	2203      	movs	r2, #3
 8004394:	fa02 f303 	lsl.w	r3, r2, r3
 8004398:	43db      	mvns	r3, r3
 800439a:	693a      	ldr	r2, [r7, #16]
 800439c:	4013      	ands	r3, r2
 800439e:	613b      	str	r3, [r7, #16]
        temp |= (GPIO_Init->Speed << (position * 2u));
 80043a0:	683b      	ldr	r3, [r7, #0]
 80043a2:	68da      	ldr	r2, [r3, #12]
 80043a4:	697b      	ldr	r3, [r7, #20]
 80043a6:	005b      	lsls	r3, r3, #1
 80043a8:	fa02 f303 	lsl.w	r3, r2, r3
 80043ac:	693a      	ldr	r2, [r7, #16]
 80043ae:	4313      	orrs	r3, r2
 80043b0:	613b      	str	r3, [r7, #16]
        GPIOx->OSPEEDR = temp;
 80043b2:	687b      	ldr	r3, [r7, #4]
 80043b4:	693a      	ldr	r2, [r7, #16]
 80043b6:	609a      	str	r2, [r3, #8]

        /* Configure the IO Output Type */
        temp = GPIOx->OTYPER;
 80043b8:	687b      	ldr	r3, [r7, #4]
 80043ba:	685b      	ldr	r3, [r3, #4]
 80043bc:	613b      	str	r3, [r7, #16]
        temp &= ~(GPIO_OTYPER_OT0 << position) ;
 80043be:	2201      	movs	r2, #1
 80043c0:	697b      	ldr	r3, [r7, #20]
 80043c2:	fa02 f303 	lsl.w	r3, r2, r3
 80043c6:	43db      	mvns	r3, r3
 80043c8:	693a      	ldr	r2, [r7, #16]
 80043ca:	4013      	ands	r3, r2
 80043cc:	613b      	str	r3, [r7, #16]
        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
 80043ce:	683b      	ldr	r3, [r7, #0]
 80043d0:	685b      	ldr	r3, [r3, #4]
 80043d2:	091b      	lsrs	r3, r3, #4
 80043d4:	f003 0201 	and.w	r2, r3, #1
 80043d8:	697b      	ldr	r3, [r7, #20]
 80043da:	fa02 f303 	lsl.w	r3, r2, r3
 80043de:	693a      	ldr	r2, [r7, #16]
 80043e0:	4313      	orrs	r3, r2
 80043e2:	613b      	str	r3, [r7, #16]
        GPIOx->OTYPER = temp;
 80043e4:	687b      	ldr	r3, [r7, #4]
 80043e6:	693a      	ldr	r2, [r7, #16]
 80043e8:	605a      	str	r2, [r3, #4]
      }

#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */

      /* Activate the Pull-up or Pull down resistor for the current IO */
      if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
 80043ea:	683b      	ldr	r3, [r7, #0]
 80043ec:	685b      	ldr	r3, [r3, #4]
 80043ee:	f003 0303 	and.w	r3, r3, #3
 80043f2:	2b03      	cmp	r3, #3
 80043f4:	d017      	beq.n	8004426 <HAL_GPIO_Init+0xde>
      {
        /* Check the Pull parameter */
        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));

        temp = GPIOx->PUPDR;
 80043f6:	687b      	ldr	r3, [r7, #4]
 80043f8:	68db      	ldr	r3, [r3, #12]
 80043fa:	613b      	str	r3, [r7, #16]
        temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
 80043fc:	697b      	ldr	r3, [r7, #20]
 80043fe:	005b      	lsls	r3, r3, #1
 8004400:	2203      	movs	r2, #3
 8004402:	fa02 f303 	lsl.w	r3, r2, r3
 8004406:	43db      	mvns	r3, r3
 8004408:	693a      	ldr	r2, [r7, #16]
 800440a:	4013      	ands	r3, r2
 800440c:	613b      	str	r3, [r7, #16]
        temp |= ((GPIO_Init->Pull) << (position * 2U));
 800440e:	683b      	ldr	r3, [r7, #0]
 8004410:	689a      	ldr	r2, [r3, #8]
 8004412:	697b      	ldr	r3, [r7, #20]
 8004414:	005b      	lsls	r3, r3, #1
 8004416:	fa02 f303 	lsl.w	r3, r2, r3
 800441a:	693a      	ldr	r2, [r7, #16]
 800441c:	4313      	orrs	r3, r2
 800441e:	613b      	str	r3, [r7, #16]
        GPIOx->PUPDR = temp;
 8004420:	687b      	ldr	r3, [r7, #4]
 8004422:	693a      	ldr	r2, [r7, #16]
 8004424:	60da      	str	r2, [r3, #12]
      }

      /* In case of Alternate function mode selection */
      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
 8004426:	683b      	ldr	r3, [r7, #0]
 8004428:	685b      	ldr	r3, [r3, #4]
 800442a:	f003 0303 	and.w	r3, r3, #3
 800442e:	2b02      	cmp	r3, #2
 8004430:	d123      	bne.n	800447a <HAL_GPIO_Init+0x132>
        /* Check the Alternate function parameters */
        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));

        /* Configure Alternate function mapped with the current IO */
        temp = GPIOx->AFR[position >> 3u];
 8004432:	697b      	ldr	r3, [r7, #20]
 8004434:	08da      	lsrs	r2, r3, #3
 8004436:	687b      	ldr	r3, [r7, #4]
 8004438:	3208      	adds	r2, #8
 800443a:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
 800443e:	613b      	str	r3, [r7, #16]
        temp &= ~(0xFu << ((position & 0x07u) * 4u));
 8004440:	697b      	ldr	r3, [r7, #20]
 8004442:	f003 0307 	and.w	r3, r3, #7
 8004446:	009b      	lsls	r3, r3, #2
 8004448:	220f      	movs	r2, #15
 800444a:	fa02 f303 	lsl.w	r3, r2, r3
 800444e:	43db      	mvns	r3, r3
 8004450:	693a      	ldr	r2, [r7, #16]
 8004452:	4013      	ands	r3, r2
 8004454:	613b      	str	r3, [r7, #16]
        temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
 8004456:	683b      	ldr	r3, [r7, #0]
 8004458:	691a      	ldr	r2, [r3, #16]
 800445a:	697b      	ldr	r3, [r7, #20]
 800445c:	f003 0307 	and.w	r3, r3, #7
 8004460:	009b      	lsls	r3, r3, #2
 8004462:	fa02 f303 	lsl.w	r3, r2, r3
 8004466:	693a      	ldr	r2, [r7, #16]
 8004468:	4313      	orrs	r3, r2
 800446a:	613b      	str	r3, [r7, #16]
        GPIOx->AFR[position >> 3u] = temp;
 800446c:	697b      	ldr	r3, [r7, #20]
 800446e:	08da      	lsrs	r2, r3, #3
 8004470:	687b      	ldr	r3, [r7, #4]
 8004472:	3208      	adds	r2, #8
 8004474:	6939      	ldr	r1, [r7, #16]
 8004476:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
      }

      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
      temp = GPIOx->MODER;
 800447a:	687b      	ldr	r3, [r7, #4]
 800447c:	681b      	ldr	r3, [r3, #0]
 800447e:	613b      	str	r3, [r7, #16]
      temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
 8004480:	697b      	ldr	r3, [r7, #20]
 8004482:	005b      	lsls	r3, r3, #1
 8004484:	2203      	movs	r2, #3
 8004486:	fa02 f303 	lsl.w	r3, r2, r3
 800448a:	43db      	mvns	r3, r3
 800448c:	693a      	ldr	r2, [r7, #16]
 800448e:	4013      	ands	r3, r2
 8004490:	613b      	str	r3, [r7, #16]
      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
 8004492:	683b      	ldr	r3, [r7, #0]
 8004494:	685b      	ldr	r3, [r3, #4]
 8004496:	f003 0203 	and.w	r2, r3, #3
 800449a:	697b      	ldr	r3, [r7, #20]
 800449c:	005b      	lsls	r3, r3, #1
 800449e:	fa02 f303 	lsl.w	r3, r2, r3
 80044a2:	693a      	ldr	r2, [r7, #16]
 80044a4:	4313      	orrs	r3, r2
 80044a6:	613b      	str	r3, [r7, #16]
      GPIOx->MODER = temp;
 80044a8:	687b      	ldr	r3, [r7, #4]
 80044aa:	693a      	ldr	r2, [r7, #16]
 80044ac:	601a      	str	r2, [r3, #0]

      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
 80044ae:	683b      	ldr	r3, [r7, #0]
 80044b0:	685b      	ldr	r3, [r3, #4]
 80044b2:	f403 3340 	and.w	r3, r3, #196608	@ 0x30000
 80044b6:	2b00      	cmp	r3, #0
 80044b8:	f000 80a0 	beq.w	80045fc <HAL_GPIO_Init+0x2b4>
      {
        /* Enable SYSCFG Clock */
        __HAL_RCC_SYSCFG_CLK_ENABLE();
 80044bc:	4b58      	ldr	r3, [pc, #352]	@ (8004620 <HAL_GPIO_Init+0x2d8>)
 80044be:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 80044c0:	4a57      	ldr	r2, [pc, #348]	@ (8004620 <HAL_GPIO_Init+0x2d8>)
 80044c2:	f043 0301 	orr.w	r3, r3, #1
 80044c6:	6613      	str	r3, [r2, #96]	@ 0x60
 80044c8:	4b55      	ldr	r3, [pc, #340]	@ (8004620 <HAL_GPIO_Init+0x2d8>)
 80044ca:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 80044cc:	f003 0301 	and.w	r3, r3, #1
 80044d0:	60bb      	str	r3, [r7, #8]
 80044d2:	68bb      	ldr	r3, [r7, #8]

        temp = SYSCFG->EXTICR[position >> 2u];
 80044d4:	4a53      	ldr	r2, [pc, #332]	@ (8004624 <HAL_GPIO_Init+0x2dc>)
 80044d6:	697b      	ldr	r3, [r7, #20]
 80044d8:	089b      	lsrs	r3, r3, #2
 80044da:	3302      	adds	r3, #2
 80044dc:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 80044e0:	613b      	str	r3, [r7, #16]
        temp &= ~(0x0FuL << (4u * (position & 0x03u)));
 80044e2:	697b      	ldr	r3, [r7, #20]
 80044e4:	f003 0303 	and.w	r3, r3, #3
 80044e8:	009b      	lsls	r3, r3, #2
 80044ea:	220f      	movs	r2, #15
 80044ec:	fa02 f303 	lsl.w	r3, r2, r3
 80044f0:	43db      	mvns	r3, r3
 80044f2:	693a      	ldr	r2, [r7, #16]
 80044f4:	4013      	ands	r3, r2
 80044f6:	613b      	str	r3, [r7, #16]
        temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
 80044f8:	687b      	ldr	r3, [r7, #4]
 80044fa:	f1b3 4f90 	cmp.w	r3, #1207959552	@ 0x48000000
 80044fe:	d019      	beq.n	8004534 <HAL_GPIO_Init+0x1ec>
 8004500:	687b      	ldr	r3, [r7, #4]
 8004502:	4a49      	ldr	r2, [pc, #292]	@ (8004628 <HAL_GPIO_Init+0x2e0>)
 8004504:	4293      	cmp	r3, r2
 8004506:	d013      	beq.n	8004530 <HAL_GPIO_Init+0x1e8>
 8004508:	687b      	ldr	r3, [r7, #4]
 800450a:	4a48      	ldr	r2, [pc, #288]	@ (800462c <HAL_GPIO_Init+0x2e4>)
 800450c:	4293      	cmp	r3, r2
 800450e:	d00d      	beq.n	800452c <HAL_GPIO_Init+0x1e4>
 8004510:	687b      	ldr	r3, [r7, #4]
 8004512:	4a47      	ldr	r2, [pc, #284]	@ (8004630 <HAL_GPIO_Init+0x2e8>)
 8004514:	4293      	cmp	r3, r2
 8004516:	d007      	beq.n	8004528 <HAL_GPIO_Init+0x1e0>
 8004518:	687b      	ldr	r3, [r7, #4]
 800451a:	4a46      	ldr	r2, [pc, #280]	@ (8004634 <HAL_GPIO_Init+0x2ec>)
 800451c:	4293      	cmp	r3, r2
 800451e:	d101      	bne.n	8004524 <HAL_GPIO_Init+0x1dc>
 8004520:	2304      	movs	r3, #4
 8004522:	e008      	b.n	8004536 <HAL_GPIO_Init+0x1ee>
 8004524:	2307      	movs	r3, #7
 8004526:	e006      	b.n	8004536 <HAL_GPIO_Init+0x1ee>
 8004528:	2303      	movs	r3, #3
 800452a:	e004      	b.n	8004536 <HAL_GPIO_Init+0x1ee>
 800452c:	2302      	movs	r3, #2
 800452e:	e002      	b.n	8004536 <HAL_GPIO_Init+0x1ee>
 8004530:	2301      	movs	r3, #1
 8004532:	e000      	b.n	8004536 <HAL_GPIO_Init+0x1ee>
 8004534:	2300      	movs	r3, #0
 8004536:	697a      	ldr	r2, [r7, #20]
 8004538:	f002 0203 	and.w	r2, r2, #3
 800453c:	0092      	lsls	r2, r2, #2
 800453e:	4093      	lsls	r3, r2
 8004540:	693a      	ldr	r2, [r7, #16]
 8004542:	4313      	orrs	r3, r2
 8004544:	613b      	str	r3, [r7, #16]
        SYSCFG->EXTICR[position >> 2u] = temp;
 8004546:	4937      	ldr	r1, [pc, #220]	@ (8004624 <HAL_GPIO_Init+0x2dc>)
 8004548:	697b      	ldr	r3, [r7, #20]
 800454a:	089b      	lsrs	r3, r3, #2
 800454c:	3302      	adds	r3, #2
 800454e:	693a      	ldr	r2, [r7, #16]
 8004550:	f841 2023 	str.w	r2, [r1, r3, lsl #2]

        /* Clear Rising Falling edge configuration */
        temp = EXTI->RTSR1;
 8004554:	4b38      	ldr	r3, [pc, #224]	@ (8004638 <HAL_GPIO_Init+0x2f0>)
 8004556:	689b      	ldr	r3, [r3, #8]
 8004558:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 800455a:	68fb      	ldr	r3, [r7, #12]
 800455c:	43db      	mvns	r3, r3
 800455e:	693a      	ldr	r2, [r7, #16]
 8004560:	4013      	ands	r3, r2
 8004562:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
 8004564:	683b      	ldr	r3, [r7, #0]
 8004566:	685b      	ldr	r3, [r3, #4]
 8004568:	f403 1380 	and.w	r3, r3, #1048576	@ 0x100000
 800456c:	2b00      	cmp	r3, #0
 800456e:	d003      	beq.n	8004578 <HAL_GPIO_Init+0x230>
        {
          temp |= iocurrent;
 8004570:	693a      	ldr	r2, [r7, #16]
 8004572:	68fb      	ldr	r3, [r7, #12]
 8004574:	4313      	orrs	r3, r2
 8004576:	613b      	str	r3, [r7, #16]
        }
        EXTI->RTSR1 = temp;
 8004578:	4a2f      	ldr	r2, [pc, #188]	@ (8004638 <HAL_GPIO_Init+0x2f0>)
 800457a:	693b      	ldr	r3, [r7, #16]
 800457c:	6093      	str	r3, [r2, #8]

        temp = EXTI->FTSR1;
 800457e:	4b2e      	ldr	r3, [pc, #184]	@ (8004638 <HAL_GPIO_Init+0x2f0>)
 8004580:	68db      	ldr	r3, [r3, #12]
 8004582:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 8004584:	68fb      	ldr	r3, [r7, #12]
 8004586:	43db      	mvns	r3, r3
 8004588:	693a      	ldr	r2, [r7, #16]
 800458a:	4013      	ands	r3, r2
 800458c:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
 800458e:	683b      	ldr	r3, [r7, #0]
 8004590:	685b      	ldr	r3, [r3, #4]
 8004592:	f403 1300 	and.w	r3, r3, #2097152	@ 0x200000
 8004596:	2b00      	cmp	r3, #0
 8004598:	d003      	beq.n	80045a2 <HAL_GPIO_Init+0x25a>
        {
          temp |= iocurrent;
 800459a:	693a      	ldr	r2, [r7, #16]
 800459c:	68fb      	ldr	r3, [r7, #12]
 800459e:	4313      	orrs	r3, r2
 80045a0:	613b      	str	r3, [r7, #16]
        }
        EXTI->FTSR1 = temp;
 80045a2:	4a25      	ldr	r2, [pc, #148]	@ (8004638 <HAL_GPIO_Init+0x2f0>)
 80045a4:	693b      	ldr	r3, [r7, #16]
 80045a6:	60d3      	str	r3, [r2, #12]

        /* Clear EXTI line configuration */
        temp = EXTI->EMR1;
 80045a8:	4b23      	ldr	r3, [pc, #140]	@ (8004638 <HAL_GPIO_Init+0x2f0>)
 80045aa:	685b      	ldr	r3, [r3, #4]
 80045ac:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 80045ae:	68fb      	ldr	r3, [r7, #12]
 80045b0:	43db      	mvns	r3, r3
 80045b2:	693a      	ldr	r2, [r7, #16]
 80045b4:	4013      	ands	r3, r2
 80045b6:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
 80045b8:	683b      	ldr	r3, [r7, #0]
 80045ba:	685b      	ldr	r3, [r3, #4]
 80045bc:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 80045c0:	2b00      	cmp	r3, #0
 80045c2:	d003      	beq.n	80045cc <HAL_GPIO_Init+0x284>
        {
          temp |= iocurrent;
 80045c4:	693a      	ldr	r2, [r7, #16]
 80045c6:	68fb      	ldr	r3, [r7, #12]
 80045c8:	4313      	orrs	r3, r2
 80045ca:	613b      	str	r3, [r7, #16]
        }
        EXTI->EMR1 = temp;
 80045cc:	4a1a      	ldr	r2, [pc, #104]	@ (8004638 <HAL_GPIO_Init+0x2f0>)
 80045ce:	693b      	ldr	r3, [r7, #16]
 80045d0:	6053      	str	r3, [r2, #4]

        temp = EXTI->IMR1;
 80045d2:	4b19      	ldr	r3, [pc, #100]	@ (8004638 <HAL_GPIO_Init+0x2f0>)
 80045d4:	681b      	ldr	r3, [r3, #0]
 80045d6:	613b      	str	r3, [r7, #16]
        temp &= ~(iocurrent);
 80045d8:	68fb      	ldr	r3, [r7, #12]
 80045da:	43db      	mvns	r3, r3
 80045dc:	693a      	ldr	r2, [r7, #16]
 80045de:	4013      	ands	r3, r2
 80045e0:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
 80045e2:	683b      	ldr	r3, [r7, #0]
 80045e4:	685b      	ldr	r3, [r3, #4]
 80045e6:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 80045ea:	2b00      	cmp	r3, #0
 80045ec:	d003      	beq.n	80045f6 <HAL_GPIO_Init+0x2ae>
        {
          temp |= iocurrent;
 80045ee:	693a      	ldr	r2, [r7, #16]
 80045f0:	68fb      	ldr	r3, [r7, #12]
 80045f2:	4313      	orrs	r3, r2
 80045f4:	613b      	str	r3, [r7, #16]
        }
        EXTI->IMR1 = temp;
 80045f6:	4a10      	ldr	r2, [pc, #64]	@ (8004638 <HAL_GPIO_Init+0x2f0>)
 80045f8:	693b      	ldr	r3, [r7, #16]
 80045fa:	6013      	str	r3, [r2, #0]
      }
    }

    position++;
 80045fc:	697b      	ldr	r3, [r7, #20]
 80045fe:	3301      	adds	r3, #1
 8004600:	617b      	str	r3, [r7, #20]
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 8004602:	683b      	ldr	r3, [r7, #0]
 8004604:	681a      	ldr	r2, [r3, #0]
 8004606:	697b      	ldr	r3, [r7, #20]
 8004608:	fa22 f303 	lsr.w	r3, r2, r3
 800460c:	2b00      	cmp	r3, #0
 800460e:	f47f aea3 	bne.w	8004358 <HAL_GPIO_Init+0x10>
  }
}
 8004612:	bf00      	nop
 8004614:	bf00      	nop
 8004616:	371c      	adds	r7, #28
 8004618:	46bd      	mov	sp, r7
 800461a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800461e:	4770      	bx	lr
 8004620:	40021000 	.word	0x40021000
 8004624:	40010000 	.word	0x40010000
 8004628:	48000400 	.word	0x48000400
 800462c:	48000800 	.word	0x48000800
 8004630:	48000c00 	.word	0x48000c00
 8004634:	48001000 	.word	0x48001000
 8004638:	40010400 	.word	0x40010400

0800463c <HAL_GPIO_WritePin>:
  *            @arg GPIO_PIN_RESET: to clear the port pin
  *            @arg GPIO_PIN_SET: to set the port pin
  * @retval None
  */
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
 800463c:	b480      	push	{r7}
 800463e:	b083      	sub	sp, #12
 8004640:	af00      	add	r7, sp, #0
 8004642:	6078      	str	r0, [r7, #4]
 8004644:	460b      	mov	r3, r1
 8004646:	807b      	strh	r3, [r7, #2]
 8004648:	4613      	mov	r3, r2
 800464a:	707b      	strb	r3, [r7, #1]
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if(PinState != GPIO_PIN_RESET)
 800464c:	787b      	ldrb	r3, [r7, #1]
 800464e:	2b00      	cmp	r3, #0
 8004650:	d003      	beq.n	800465a <HAL_GPIO_WritePin+0x1e>
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin;
 8004652:	887a      	ldrh	r2, [r7, #2]
 8004654:	687b      	ldr	r3, [r7, #4]
 8004656:	619a      	str	r2, [r3, #24]
  }
  else
  {
    GPIOx->BRR = (uint32_t)GPIO_Pin;
  }
}
 8004658:	e002      	b.n	8004660 <HAL_GPIO_WritePin+0x24>
    GPIOx->BRR = (uint32_t)GPIO_Pin;
 800465a:	887a      	ldrh	r2, [r7, #2]
 800465c:	687b      	ldr	r3, [r7, #4]
 800465e:	629a      	str	r2, [r3, #40]	@ 0x28
}
 8004660:	bf00      	nop
 8004662:	370c      	adds	r7, #12
 8004664:	46bd      	mov	sp, r7
 8004666:	f85d 7b04 	ldr.w	r7, [sp], #4
 800466a:	4770      	bx	lr

0800466c <HAL_I2C_Init>:
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
  *                the configuration information for the specified I2C.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
 800466c:	b580      	push	{r7, lr}
 800466e:	b082      	sub	sp, #8
 8004670:	af00      	add	r7, sp, #0
 8004672:	6078      	str	r0, [r7, #4]
  /* Check the I2C handle allocation */
  if (hi2c == NULL)
 8004674:	687b      	ldr	r3, [r7, #4]
 8004676:	2b00      	cmp	r3, #0
 8004678:	d101      	bne.n	800467e <HAL_I2C_Init+0x12>
  {
    return HAL_ERROR;
 800467a:	2301      	movs	r3, #1
 800467c:	e08d      	b.n	800479a <HAL_I2C_Init+0x12e>
  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));

  if (hi2c->State == HAL_I2C_STATE_RESET)
 800467e:	687b      	ldr	r3, [r7, #4]
 8004680:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
 8004684:	b2db      	uxtb	r3, r3
 8004686:	2b00      	cmp	r3, #0
 8004688:	d106      	bne.n	8004698 <HAL_I2C_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    hi2c->Lock = HAL_UNLOCKED;
 800468a:	687b      	ldr	r3, [r7, #4]
 800468c:	2200      	movs	r2, #0
 800468e:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
    hi2c->MspInitCallback(hi2c);
#else
    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
    HAL_I2C_MspInit(hi2c);
 8004692:	6878      	ldr	r0, [r7, #4]
 8004694:	f7ff fae6 	bl	8003c64 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
  }

  hi2c->State = HAL_I2C_STATE_BUSY;
 8004698:	687b      	ldr	r3, [r7, #4]
 800469a:	2224      	movs	r2, #36	@ 0x24
 800469c:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41

  /* Disable the selected I2C peripheral */
  __HAL_I2C_DISABLE(hi2c);
 80046a0:	687b      	ldr	r3, [r7, #4]
 80046a2:	681b      	ldr	r3, [r3, #0]
 80046a4:	681a      	ldr	r2, [r3, #0]
 80046a6:	687b      	ldr	r3, [r7, #4]
 80046a8:	681b      	ldr	r3, [r3, #0]
 80046aa:	f022 0201 	bic.w	r2, r2, #1
 80046ae:	601a      	str	r2, [r3, #0]

  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
  /* Configure I2Cx: Frequency range */
  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
 80046b0:	687b      	ldr	r3, [r7, #4]
 80046b2:	685a      	ldr	r2, [r3, #4]
 80046b4:	687b      	ldr	r3, [r7, #4]
 80046b6:	681b      	ldr	r3, [r3, #0]
 80046b8:	f022 6270 	bic.w	r2, r2, #251658240	@ 0xf000000
 80046bc:	611a      	str	r2, [r3, #16]

  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
  /* Disable Own Address1 before set the Own Address1 configuration */
  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
 80046be:	687b      	ldr	r3, [r7, #4]
 80046c0:	681b      	ldr	r3, [r3, #0]
 80046c2:	689a      	ldr	r2, [r3, #8]
 80046c4:	687b      	ldr	r3, [r7, #4]
 80046c6:	681b      	ldr	r3, [r3, #0]
 80046c8:	f422 4200 	bic.w	r2, r2, #32768	@ 0x8000
 80046cc:	609a      	str	r2, [r3, #8]

  /* Configure I2Cx: Own Address1 and ack own address1 mode */
  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
 80046ce:	687b      	ldr	r3, [r7, #4]
 80046d0:	68db      	ldr	r3, [r3, #12]
 80046d2:	2b01      	cmp	r3, #1
 80046d4:	d107      	bne.n	80046e6 <HAL_I2C_Init+0x7a>
  {
    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
 80046d6:	687b      	ldr	r3, [r7, #4]
 80046d8:	689a      	ldr	r2, [r3, #8]
 80046da:	687b      	ldr	r3, [r7, #4]
 80046dc:	681b      	ldr	r3, [r3, #0]
 80046de:	f442 4200 	orr.w	r2, r2, #32768	@ 0x8000
 80046e2:	609a      	str	r2, [r3, #8]
 80046e4:	e006      	b.n	80046f4 <HAL_I2C_Init+0x88>
  }
  else /* I2C_ADDRESSINGMODE_10BIT */
  {
    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
 80046e6:	687b      	ldr	r3, [r7, #4]
 80046e8:	689a      	ldr	r2, [r3, #8]
 80046ea:	687b      	ldr	r3, [r7, #4]
 80046ec:	681b      	ldr	r3, [r3, #0]
 80046ee:	f442 4204 	orr.w	r2, r2, #33792	@ 0x8400
 80046f2:	609a      	str	r2, [r3, #8]
  }

  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
  /* Configure I2Cx: Addressing Master mode */
  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
 80046f4:	687b      	ldr	r3, [r7, #4]
 80046f6:	68db      	ldr	r3, [r3, #12]
 80046f8:	2b02      	cmp	r3, #2
 80046fa:	d108      	bne.n	800470e <HAL_I2C_Init+0xa2>
  {
    SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
 80046fc:	687b      	ldr	r3, [r7, #4]
 80046fe:	681b      	ldr	r3, [r3, #0]
 8004700:	685a      	ldr	r2, [r3, #4]
 8004702:	687b      	ldr	r3, [r7, #4]
 8004704:	681b      	ldr	r3, [r3, #0]
 8004706:	f442 6200 	orr.w	r2, r2, #2048	@ 0x800
 800470a:	605a      	str	r2, [r3, #4]
 800470c:	e007      	b.n	800471e <HAL_I2C_Init+0xb2>
  }
  else
  {
    /* Clear the I2C ADD10 bit */
    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
 800470e:	687b      	ldr	r3, [r7, #4]
 8004710:	681b      	ldr	r3, [r3, #0]
 8004712:	685a      	ldr	r2, [r3, #4]
 8004714:	687b      	ldr	r3, [r7, #4]
 8004716:	681b      	ldr	r3, [r3, #0]
 8004718:	f422 6200 	bic.w	r2, r2, #2048	@ 0x800
 800471c:	605a      	str	r2, [r3, #4]
  }
  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
 800471e:	687b      	ldr	r3, [r7, #4]
 8004720:	681b      	ldr	r3, [r3, #0]
 8004722:	685b      	ldr	r3, [r3, #4]
 8004724:	687a      	ldr	r2, [r7, #4]
 8004726:	6812      	ldr	r2, [r2, #0]
 8004728:	f043 7300 	orr.w	r3, r3, #33554432	@ 0x2000000
 800472c:	f443 4300 	orr.w	r3, r3, #32768	@ 0x8000
 8004730:	6053      	str	r3, [r2, #4]

  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
  /* Disable Own Address2 before set the Own Address2 configuration */
  hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
 8004732:	687b      	ldr	r3, [r7, #4]
 8004734:	681b      	ldr	r3, [r3, #0]
 8004736:	68da      	ldr	r2, [r3, #12]
 8004738:	687b      	ldr	r3, [r7, #4]
 800473a:	681b      	ldr	r3, [r3, #0]
 800473c:	f422 4200 	bic.w	r2, r2, #32768	@ 0x8000
 8004740:	60da      	str	r2, [r3, #12]

  /* Configure I2Cx: Dual mode and Own Address2 */
  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
 8004742:	687b      	ldr	r3, [r7, #4]
 8004744:	691a      	ldr	r2, [r3, #16]
 8004746:	687b      	ldr	r3, [r7, #4]
 8004748:	695b      	ldr	r3, [r3, #20]
 800474a:	ea42 0103 	orr.w	r1, r2, r3
                          (hi2c->Init.OwnAddress2Masks << 8));
 800474e:	687b      	ldr	r3, [r7, #4]
 8004750:	699b      	ldr	r3, [r3, #24]
 8004752:	021a      	lsls	r2, r3, #8
  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
 8004754:	687b      	ldr	r3, [r7, #4]
 8004756:	681b      	ldr	r3, [r3, #0]
 8004758:	430a      	orrs	r2, r1
 800475a:	60da      	str	r2, [r3, #12]

  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
  /* Configure I2Cx: Generalcall and NoStretch mode */
  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
 800475c:	687b      	ldr	r3, [r7, #4]
 800475e:	69d9      	ldr	r1, [r3, #28]
 8004760:	687b      	ldr	r3, [r7, #4]
 8004762:	6a1a      	ldr	r2, [r3, #32]
 8004764:	687b      	ldr	r3, [r7, #4]
 8004766:	681b      	ldr	r3, [r3, #0]
 8004768:	430a      	orrs	r2, r1
 800476a:	601a      	str	r2, [r3, #0]

  /* Enable the selected I2C peripheral */
  __HAL_I2C_ENABLE(hi2c);
 800476c:	687b      	ldr	r3, [r7, #4]
 800476e:	681b      	ldr	r3, [r3, #0]
 8004770:	681a      	ldr	r2, [r3, #0]
 8004772:	687b      	ldr	r3, [r7, #4]
 8004774:	681b      	ldr	r3, [r3, #0]
 8004776:	f042 0201 	orr.w	r2, r2, #1
 800477a:	601a      	str	r2, [r3, #0]

  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 800477c:	687b      	ldr	r3, [r7, #4]
 800477e:	2200      	movs	r2, #0
 8004780:	645a      	str	r2, [r3, #68]	@ 0x44
  hi2c->State = HAL_I2C_STATE_READY;
 8004782:	687b      	ldr	r3, [r7, #4]
 8004784:	2220      	movs	r2, #32
 8004786:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
  hi2c->PreviousState = I2C_STATE_NONE;
 800478a:	687b      	ldr	r3, [r7, #4]
 800478c:	2200      	movs	r2, #0
 800478e:	631a      	str	r2, [r3, #48]	@ 0x30
  hi2c->Mode = HAL_I2C_MODE_NONE;
 8004790:	687b      	ldr	r3, [r7, #4]
 8004792:	2200      	movs	r2, #0
 8004794:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42

  return HAL_OK;
 8004798:	2300      	movs	r3, #0
}
 800479a:	4618      	mov	r0, r3
 800479c:	3708      	adds	r7, #8
 800479e:	46bd      	mov	sp, r7
 80047a0:	bd80      	pop	{r7, pc}
	...

080047a4 <HAL_I2C_Master_Transmit>:
  * @param  Timeout Timeout duration
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
                                          uint16_t Size, uint32_t Timeout)
{
 80047a4:	b580      	push	{r7, lr}
 80047a6:	b088      	sub	sp, #32
 80047a8:	af02      	add	r7, sp, #8
 80047aa:	60f8      	str	r0, [r7, #12]
 80047ac:	607a      	str	r2, [r7, #4]
 80047ae:	461a      	mov	r2, r3
 80047b0:	460b      	mov	r3, r1
 80047b2:	817b      	strh	r3, [r7, #10]
 80047b4:	4613      	mov	r3, r2
 80047b6:	813b      	strh	r3, [r7, #8]
  uint32_t tickstart;
  uint32_t xfermode;

  if (hi2c->State == HAL_I2C_STATE_READY)
 80047b8:	68fb      	ldr	r3, [r7, #12]
 80047ba:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
 80047be:	b2db      	uxtb	r3, r3
 80047c0:	2b20      	cmp	r3, #32
 80047c2:	f040 80fd 	bne.w	80049c0 <HAL_I2C_Master_Transmit+0x21c>
  {
    /* Process Locked */
    __HAL_LOCK(hi2c);
 80047c6:	68fb      	ldr	r3, [r7, #12]
 80047c8:	f893 3040 	ldrb.w	r3, [r3, #64]	@ 0x40
 80047cc:	2b01      	cmp	r3, #1
 80047ce:	d101      	bne.n	80047d4 <HAL_I2C_Master_Transmit+0x30>
 80047d0:	2302      	movs	r3, #2
 80047d2:	e0f6      	b.n	80049c2 <HAL_I2C_Master_Transmit+0x21e>
 80047d4:	68fb      	ldr	r3, [r7, #12]
 80047d6:	2201      	movs	r2, #1
 80047d8:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    /* Init tickstart for timeout management*/
    tickstart = HAL_GetTick();
 80047dc:	f7ff fc9e 	bl	800411c <HAL_GetTick>
 80047e0:	6138      	str	r0, [r7, #16]

    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
 80047e2:	693b      	ldr	r3, [r7, #16]
 80047e4:	9300      	str	r3, [sp, #0]
 80047e6:	2319      	movs	r3, #25
 80047e8:	2201      	movs	r2, #1
 80047ea:	f44f 4100 	mov.w	r1, #32768	@ 0x8000
 80047ee:	68f8      	ldr	r0, [r7, #12]
 80047f0:	f000 fbea 	bl	8004fc8 <I2C_WaitOnFlagUntilTimeout>
 80047f4:	4603      	mov	r3, r0
 80047f6:	2b00      	cmp	r3, #0
 80047f8:	d001      	beq.n	80047fe <HAL_I2C_Master_Transmit+0x5a>
    {
      return HAL_ERROR;
 80047fa:	2301      	movs	r3, #1
 80047fc:	e0e1      	b.n	80049c2 <HAL_I2C_Master_Transmit+0x21e>
    }

    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
 80047fe:	68fb      	ldr	r3, [r7, #12]
 8004800:	2221      	movs	r2, #33	@ 0x21
 8004802:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
    hi2c->Mode      = HAL_I2C_MODE_MASTER;
 8004806:	68fb      	ldr	r3, [r7, #12]
 8004808:	2210      	movs	r2, #16
 800480a:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 800480e:	68fb      	ldr	r3, [r7, #12]
 8004810:	2200      	movs	r2, #0
 8004812:	645a      	str	r2, [r3, #68]	@ 0x44

    /* Prepare transfer parameters */
    hi2c->pBuffPtr  = pData;
 8004814:	68fb      	ldr	r3, [r7, #12]
 8004816:	687a      	ldr	r2, [r7, #4]
 8004818:	625a      	str	r2, [r3, #36]	@ 0x24
    hi2c->XferCount = Size;
 800481a:	68fb      	ldr	r3, [r7, #12]
 800481c:	893a      	ldrh	r2, [r7, #8]
 800481e:	855a      	strh	r2, [r3, #42]	@ 0x2a
    hi2c->XferISR   = NULL;
 8004820:	68fb      	ldr	r3, [r7, #12]
 8004822:	2200      	movs	r2, #0
 8004824:	635a      	str	r2, [r3, #52]	@ 0x34

    if (hi2c->XferCount > MAX_NBYTE_SIZE)
 8004826:	68fb      	ldr	r3, [r7, #12]
 8004828:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 800482a:	b29b      	uxth	r3, r3
 800482c:	2bff      	cmp	r3, #255	@ 0xff
 800482e:	d906      	bls.n	800483e <HAL_I2C_Master_Transmit+0x9a>
    {
      hi2c->XferSize = MAX_NBYTE_SIZE;
 8004830:	68fb      	ldr	r3, [r7, #12]
 8004832:	22ff      	movs	r2, #255	@ 0xff
 8004834:	851a      	strh	r2, [r3, #40]	@ 0x28
      xfermode = I2C_RELOAD_MODE;
 8004836:	f04f 7380 	mov.w	r3, #16777216	@ 0x1000000
 800483a:	617b      	str	r3, [r7, #20]
 800483c:	e007      	b.n	800484e <HAL_I2C_Master_Transmit+0xaa>
    }
    else
    {
      hi2c->XferSize = hi2c->XferCount;
 800483e:	68fb      	ldr	r3, [r7, #12]
 8004840:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 8004842:	b29a      	uxth	r2, r3
 8004844:	68fb      	ldr	r3, [r7, #12]
 8004846:	851a      	strh	r2, [r3, #40]	@ 0x28
      xfermode = I2C_AUTOEND_MODE;
 8004848:	f04f 7300 	mov.w	r3, #33554432	@ 0x2000000
 800484c:	617b      	str	r3, [r7, #20]
    }

    if (hi2c->XferSize > 0U)
 800484e:	68fb      	ldr	r3, [r7, #12]
 8004850:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 8004852:	2b00      	cmp	r3, #0
 8004854:	d024      	beq.n	80048a0 <HAL_I2C_Master_Transmit+0xfc>
    {
      /* Preload TX register */
      /* Write data to TXDR */
      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
 8004856:	68fb      	ldr	r3, [r7, #12]
 8004858:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800485a:	781a      	ldrb	r2, [r3, #0]
 800485c:	68fb      	ldr	r3, [r7, #12]
 800485e:	681b      	ldr	r3, [r3, #0]
 8004860:	629a      	str	r2, [r3, #40]	@ 0x28

      /* Increment Buffer pointer */
      hi2c->pBuffPtr++;
 8004862:	68fb      	ldr	r3, [r7, #12]
 8004864:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8004866:	1c5a      	adds	r2, r3, #1
 8004868:	68fb      	ldr	r3, [r7, #12]
 800486a:	625a      	str	r2, [r3, #36]	@ 0x24

      hi2c->XferCount--;
 800486c:	68fb      	ldr	r3, [r7, #12]
 800486e:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 8004870:	b29b      	uxth	r3, r3
 8004872:	3b01      	subs	r3, #1
 8004874:	b29a      	uxth	r2, r3
 8004876:	68fb      	ldr	r3, [r7, #12]
 8004878:	855a      	strh	r2, [r3, #42]	@ 0x2a
      hi2c->XferSize--;
 800487a:	68fb      	ldr	r3, [r7, #12]
 800487c:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 800487e:	3b01      	subs	r3, #1
 8004880:	b29a      	uxth	r2, r3
 8004882:	68fb      	ldr	r3, [r7, #12]
 8004884:	851a      	strh	r2, [r3, #40]	@ 0x28

      /* Send Slave Address */
      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
 8004886:	68fb      	ldr	r3, [r7, #12]
 8004888:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 800488a:	b2db      	uxtb	r3, r3
 800488c:	3301      	adds	r3, #1
 800488e:	b2da      	uxtb	r2, r3
 8004890:	8979      	ldrh	r1, [r7, #10]
 8004892:	4b4e      	ldr	r3, [pc, #312]	@ (80049cc <HAL_I2C_Master_Transmit+0x228>)
 8004894:	9300      	str	r3, [sp, #0]
 8004896:	697b      	ldr	r3, [r7, #20]
 8004898:	68f8      	ldr	r0, [r7, #12]
 800489a:	f000 fd59 	bl	8005350 <I2C_TransferConfig>
 800489e:	e066      	b.n	800496e <HAL_I2C_Master_Transmit+0x1ca>
    }
    else
    {
      /* Send Slave Address */
      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
 80048a0:	68fb      	ldr	r3, [r7, #12]
 80048a2:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 80048a4:	b2da      	uxtb	r2, r3
 80048a6:	8979      	ldrh	r1, [r7, #10]
 80048a8:	4b48      	ldr	r3, [pc, #288]	@ (80049cc <HAL_I2C_Master_Transmit+0x228>)
 80048aa:	9300      	str	r3, [sp, #0]
 80048ac:	697b      	ldr	r3, [r7, #20]
 80048ae:	68f8      	ldr	r0, [r7, #12]
 80048b0:	f000 fd4e 	bl	8005350 <I2C_TransferConfig>
                         I2C_GENERATE_START_WRITE);
    }

    while (hi2c->XferCount > 0U)
 80048b4:	e05b      	b.n	800496e <HAL_I2C_Master_Transmit+0x1ca>
    {
      /* Wait until TXIS flag is set */
      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
 80048b6:	693a      	ldr	r2, [r7, #16]
 80048b8:	6a39      	ldr	r1, [r7, #32]
 80048ba:	68f8      	ldr	r0, [r7, #12]
 80048bc:	f000 fbdd 	bl	800507a <I2C_WaitOnTXISFlagUntilTimeout>
 80048c0:	4603      	mov	r3, r0
 80048c2:	2b00      	cmp	r3, #0
 80048c4:	d001      	beq.n	80048ca <HAL_I2C_Master_Transmit+0x126>
      {
        return HAL_ERROR;
 80048c6:	2301      	movs	r3, #1
 80048c8:	e07b      	b.n	80049c2 <HAL_I2C_Master_Transmit+0x21e>
      }
      /* Write data to TXDR */
      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
 80048ca:	68fb      	ldr	r3, [r7, #12]
 80048cc:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80048ce:	781a      	ldrb	r2, [r3, #0]
 80048d0:	68fb      	ldr	r3, [r7, #12]
 80048d2:	681b      	ldr	r3, [r3, #0]
 80048d4:	629a      	str	r2, [r3, #40]	@ 0x28

      /* Increment Buffer pointer */
      hi2c->pBuffPtr++;
 80048d6:	68fb      	ldr	r3, [r7, #12]
 80048d8:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80048da:	1c5a      	adds	r2, r3, #1
 80048dc:	68fb      	ldr	r3, [r7, #12]
 80048de:	625a      	str	r2, [r3, #36]	@ 0x24

      hi2c->XferCount--;
 80048e0:	68fb      	ldr	r3, [r7, #12]
 80048e2:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 80048e4:	b29b      	uxth	r3, r3
 80048e6:	3b01      	subs	r3, #1
 80048e8:	b29a      	uxth	r2, r3
 80048ea:	68fb      	ldr	r3, [r7, #12]
 80048ec:	855a      	strh	r2, [r3, #42]	@ 0x2a
      hi2c->XferSize--;
 80048ee:	68fb      	ldr	r3, [r7, #12]
 80048f0:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 80048f2:	3b01      	subs	r3, #1
 80048f4:	b29a      	uxth	r2, r3
 80048f6:	68fb      	ldr	r3, [r7, #12]
 80048f8:	851a      	strh	r2, [r3, #40]	@ 0x28

      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
 80048fa:	68fb      	ldr	r3, [r7, #12]
 80048fc:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 80048fe:	b29b      	uxth	r3, r3
 8004900:	2b00      	cmp	r3, #0
 8004902:	d034      	beq.n	800496e <HAL_I2C_Master_Transmit+0x1ca>
 8004904:	68fb      	ldr	r3, [r7, #12]
 8004906:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 8004908:	2b00      	cmp	r3, #0
 800490a:	d130      	bne.n	800496e <HAL_I2C_Master_Transmit+0x1ca>
      {
        /* Wait until TCR flag is set */
        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
 800490c:	693b      	ldr	r3, [r7, #16]
 800490e:	9300      	str	r3, [sp, #0]
 8004910:	6a3b      	ldr	r3, [r7, #32]
 8004912:	2200      	movs	r2, #0
 8004914:	2180      	movs	r1, #128	@ 0x80
 8004916:	68f8      	ldr	r0, [r7, #12]
 8004918:	f000 fb56 	bl	8004fc8 <I2C_WaitOnFlagUntilTimeout>
 800491c:	4603      	mov	r3, r0
 800491e:	2b00      	cmp	r3, #0
 8004920:	d001      	beq.n	8004926 <HAL_I2C_Master_Transmit+0x182>
        {
          return HAL_ERROR;
 8004922:	2301      	movs	r3, #1
 8004924:	e04d      	b.n	80049c2 <HAL_I2C_Master_Transmit+0x21e>
        }

        if (hi2c->XferCount > MAX_NBYTE_SIZE)
 8004926:	68fb      	ldr	r3, [r7, #12]
 8004928:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 800492a:	b29b      	uxth	r3, r3
 800492c:	2bff      	cmp	r3, #255	@ 0xff
 800492e:	d90e      	bls.n	800494e <HAL_I2C_Master_Transmit+0x1aa>
        {
          hi2c->XferSize = MAX_NBYTE_SIZE;
 8004930:	68fb      	ldr	r3, [r7, #12]
 8004932:	22ff      	movs	r2, #255	@ 0xff
 8004934:	851a      	strh	r2, [r3, #40]	@ 0x28
          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
 8004936:	68fb      	ldr	r3, [r7, #12]
 8004938:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 800493a:	b2da      	uxtb	r2, r3
 800493c:	8979      	ldrh	r1, [r7, #10]
 800493e:	2300      	movs	r3, #0
 8004940:	9300      	str	r3, [sp, #0]
 8004942:	f04f 7380 	mov.w	r3, #16777216	@ 0x1000000
 8004946:	68f8      	ldr	r0, [r7, #12]
 8004948:	f000 fd02 	bl	8005350 <I2C_TransferConfig>
 800494c:	e00f      	b.n	800496e <HAL_I2C_Master_Transmit+0x1ca>
                             I2C_NO_STARTSTOP);
        }
        else
        {
          hi2c->XferSize = hi2c->XferCount;
 800494e:	68fb      	ldr	r3, [r7, #12]
 8004950:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 8004952:	b29a      	uxth	r2, r3
 8004954:	68fb      	ldr	r3, [r7, #12]
 8004956:	851a      	strh	r2, [r3, #40]	@ 0x28
          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
 8004958:	68fb      	ldr	r3, [r7, #12]
 800495a:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 800495c:	b2da      	uxtb	r2, r3
 800495e:	8979      	ldrh	r1, [r7, #10]
 8004960:	2300      	movs	r3, #0
 8004962:	9300      	str	r3, [sp, #0]
 8004964:	f04f 7300 	mov.w	r3, #33554432	@ 0x2000000
 8004968:	68f8      	ldr	r0, [r7, #12]
 800496a:	f000 fcf1 	bl	8005350 <I2C_TransferConfig>
    while (hi2c->XferCount > 0U)
 800496e:	68fb      	ldr	r3, [r7, #12]
 8004970:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 8004972:	b29b      	uxth	r3, r3
 8004974:	2b00      	cmp	r3, #0
 8004976:	d19e      	bne.n	80048b6 <HAL_I2C_Master_Transmit+0x112>
      }
    }

    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
    /* Wait until STOPF flag is set */
    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
 8004978:	693a      	ldr	r2, [r7, #16]
 800497a:	6a39      	ldr	r1, [r7, #32]
 800497c:	68f8      	ldr	r0, [r7, #12]
 800497e:	f000 fbc3 	bl	8005108 <I2C_WaitOnSTOPFlagUntilTimeout>
 8004982:	4603      	mov	r3, r0
 8004984:	2b00      	cmp	r3, #0
 8004986:	d001      	beq.n	800498c <HAL_I2C_Master_Transmit+0x1e8>
    {
      return HAL_ERROR;
 8004988:	2301      	movs	r3, #1
 800498a:	e01a      	b.n	80049c2 <HAL_I2C_Master_Transmit+0x21e>
    }

    /* Clear STOP Flag */
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
 800498c:	68fb      	ldr	r3, [r7, #12]
 800498e:	681b      	ldr	r3, [r3, #0]
 8004990:	2220      	movs	r2, #32
 8004992:	61da      	str	r2, [r3, #28]

    /* Clear Configuration Register 2 */
    I2C_RESET_CR2(hi2c);
 8004994:	68fb      	ldr	r3, [r7, #12]
 8004996:	681b      	ldr	r3, [r3, #0]
 8004998:	6859      	ldr	r1, [r3, #4]
 800499a:	68fb      	ldr	r3, [r7, #12]
 800499c:	681a      	ldr	r2, [r3, #0]
 800499e:	4b0c      	ldr	r3, [pc, #48]	@ (80049d0 <HAL_I2C_Master_Transmit+0x22c>)
 80049a0:	400b      	ands	r3, r1
 80049a2:	6053      	str	r3, [r2, #4]

    hi2c->State = HAL_I2C_STATE_READY;
 80049a4:	68fb      	ldr	r3, [r7, #12]
 80049a6:	2220      	movs	r2, #32
 80049a8:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
    hi2c->Mode  = HAL_I2C_MODE_NONE;
 80049ac:	68fb      	ldr	r3, [r7, #12]
 80049ae:	2200      	movs	r2, #0
 80049b0:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);
 80049b4:	68fb      	ldr	r3, [r7, #12]
 80049b6:	2200      	movs	r2, #0
 80049b8:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    return HAL_OK;
 80049bc:	2300      	movs	r3, #0
 80049be:	e000      	b.n	80049c2 <HAL_I2C_Master_Transmit+0x21e>
  }
  else
  {
    return HAL_BUSY;
 80049c0:	2302      	movs	r3, #2
  }
}
 80049c2:	4618      	mov	r0, r3
 80049c4:	3718      	adds	r7, #24
 80049c6:	46bd      	mov	sp, r7
 80049c8:	bd80      	pop	{r7, pc}
 80049ca:	bf00      	nop
 80049cc:	80002000 	.word	0x80002000
 80049d0:	fe00e800 	.word	0xfe00e800

080049d4 <HAL_I2C_Mem_Write>:
  * @param  Timeout Timeout duration
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
                                    uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
 80049d4:	b580      	push	{r7, lr}
 80049d6:	b088      	sub	sp, #32
 80049d8:	af02      	add	r7, sp, #8
 80049da:	60f8      	str	r0, [r7, #12]
 80049dc:	4608      	mov	r0, r1
 80049de:	4611      	mov	r1, r2
 80049e0:	461a      	mov	r2, r3
 80049e2:	4603      	mov	r3, r0
 80049e4:	817b      	strh	r3, [r7, #10]
 80049e6:	460b      	mov	r3, r1
 80049e8:	813b      	strh	r3, [r7, #8]
 80049ea:	4613      	mov	r3, r2
 80049ec:	80fb      	strh	r3, [r7, #6]
  uint32_t tickstart;

  /* Check the parameters */
  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));

  if (hi2c->State == HAL_I2C_STATE_READY)
 80049ee:	68fb      	ldr	r3, [r7, #12]
 80049f0:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
 80049f4:	b2db      	uxtb	r3, r3
 80049f6:	2b20      	cmp	r3, #32
 80049f8:	f040 80f9 	bne.w	8004bee <HAL_I2C_Mem_Write+0x21a>
  {
    if ((pData == NULL) || (Size == 0U))
 80049fc:	6a3b      	ldr	r3, [r7, #32]
 80049fe:	2b00      	cmp	r3, #0
 8004a00:	d002      	beq.n	8004a08 <HAL_I2C_Mem_Write+0x34>
 8004a02:	8cbb      	ldrh	r3, [r7, #36]	@ 0x24
 8004a04:	2b00      	cmp	r3, #0
 8004a06:	d105      	bne.n	8004a14 <HAL_I2C_Mem_Write+0x40>
    {
      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
 8004a08:	68fb      	ldr	r3, [r7, #12]
 8004a0a:	f44f 7200 	mov.w	r2, #512	@ 0x200
 8004a0e:	645a      	str	r2, [r3, #68]	@ 0x44
      return  HAL_ERROR;
 8004a10:	2301      	movs	r3, #1
 8004a12:	e0ed      	b.n	8004bf0 <HAL_I2C_Mem_Write+0x21c>
    }

    /* Process Locked */
    __HAL_LOCK(hi2c);
 8004a14:	68fb      	ldr	r3, [r7, #12]
 8004a16:	f893 3040 	ldrb.w	r3, [r3, #64]	@ 0x40
 8004a1a:	2b01      	cmp	r3, #1
 8004a1c:	d101      	bne.n	8004a22 <HAL_I2C_Mem_Write+0x4e>
 8004a1e:	2302      	movs	r3, #2
 8004a20:	e0e6      	b.n	8004bf0 <HAL_I2C_Mem_Write+0x21c>
 8004a22:	68fb      	ldr	r3, [r7, #12]
 8004a24:	2201      	movs	r2, #1
 8004a26:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    /* Init tickstart for timeout management*/
    tickstart = HAL_GetTick();
 8004a2a:	f7ff fb77 	bl	800411c <HAL_GetTick>
 8004a2e:	6178      	str	r0, [r7, #20]

    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
 8004a30:	697b      	ldr	r3, [r7, #20]
 8004a32:	9300      	str	r3, [sp, #0]
 8004a34:	2319      	movs	r3, #25
 8004a36:	2201      	movs	r2, #1
 8004a38:	f44f 4100 	mov.w	r1, #32768	@ 0x8000
 8004a3c:	68f8      	ldr	r0, [r7, #12]
 8004a3e:	f000 fac3 	bl	8004fc8 <I2C_WaitOnFlagUntilTimeout>
 8004a42:	4603      	mov	r3, r0
 8004a44:	2b00      	cmp	r3, #0
 8004a46:	d001      	beq.n	8004a4c <HAL_I2C_Mem_Write+0x78>
    {
      return HAL_ERROR;
 8004a48:	2301      	movs	r3, #1
 8004a4a:	e0d1      	b.n	8004bf0 <HAL_I2C_Mem_Write+0x21c>
    }

    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
 8004a4c:	68fb      	ldr	r3, [r7, #12]
 8004a4e:	2221      	movs	r2, #33	@ 0x21
 8004a50:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
    hi2c->Mode      = HAL_I2C_MODE_MEM;
 8004a54:	68fb      	ldr	r3, [r7, #12]
 8004a56:	2240      	movs	r2, #64	@ 0x40
 8004a58:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 8004a5c:	68fb      	ldr	r3, [r7, #12]
 8004a5e:	2200      	movs	r2, #0
 8004a60:	645a      	str	r2, [r3, #68]	@ 0x44

    /* Prepare transfer parameters */
    hi2c->pBuffPtr  = pData;
 8004a62:	68fb      	ldr	r3, [r7, #12]
 8004a64:	6a3a      	ldr	r2, [r7, #32]
 8004a66:	625a      	str	r2, [r3, #36]	@ 0x24
    hi2c->XferCount = Size;
 8004a68:	68fb      	ldr	r3, [r7, #12]
 8004a6a:	8cba      	ldrh	r2, [r7, #36]	@ 0x24
 8004a6c:	855a      	strh	r2, [r3, #42]	@ 0x2a
    hi2c->XferISR   = NULL;
 8004a6e:	68fb      	ldr	r3, [r7, #12]
 8004a70:	2200      	movs	r2, #0
 8004a72:	635a      	str	r2, [r3, #52]	@ 0x34

    /* Send Slave Address and Memory Address */
    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
 8004a74:	88f8      	ldrh	r0, [r7, #6]
 8004a76:	893a      	ldrh	r2, [r7, #8]
 8004a78:	8979      	ldrh	r1, [r7, #10]
 8004a7a:	697b      	ldr	r3, [r7, #20]
 8004a7c:	9301      	str	r3, [sp, #4]
 8004a7e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8004a80:	9300      	str	r3, [sp, #0]
 8004a82:	4603      	mov	r3, r0
 8004a84:	68f8      	ldr	r0, [r7, #12]
 8004a86:	f000 f9d3 	bl	8004e30 <I2C_RequestMemoryWrite>
 8004a8a:	4603      	mov	r3, r0
 8004a8c:	2b00      	cmp	r3, #0
 8004a8e:	d005      	beq.n	8004a9c <HAL_I2C_Mem_Write+0xc8>
    {
      /* Process Unlocked */
      __HAL_UNLOCK(hi2c);
 8004a90:	68fb      	ldr	r3, [r7, #12]
 8004a92:	2200      	movs	r2, #0
 8004a94:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
      return HAL_ERROR;
 8004a98:	2301      	movs	r3, #1
 8004a9a:	e0a9      	b.n	8004bf0 <HAL_I2C_Mem_Write+0x21c>
    }

    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
    if (hi2c->XferCount > MAX_NBYTE_SIZE)
 8004a9c:	68fb      	ldr	r3, [r7, #12]
 8004a9e:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 8004aa0:	b29b      	uxth	r3, r3
 8004aa2:	2bff      	cmp	r3, #255	@ 0xff
 8004aa4:	d90e      	bls.n	8004ac4 <HAL_I2C_Mem_Write+0xf0>
    {
      hi2c->XferSize = MAX_NBYTE_SIZE;
 8004aa6:	68fb      	ldr	r3, [r7, #12]
 8004aa8:	22ff      	movs	r2, #255	@ 0xff
 8004aaa:	851a      	strh	r2, [r3, #40]	@ 0x28
      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
 8004aac:	68fb      	ldr	r3, [r7, #12]
 8004aae:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 8004ab0:	b2da      	uxtb	r2, r3
 8004ab2:	8979      	ldrh	r1, [r7, #10]
 8004ab4:	2300      	movs	r3, #0
 8004ab6:	9300      	str	r3, [sp, #0]
 8004ab8:	f04f 7380 	mov.w	r3, #16777216	@ 0x1000000
 8004abc:	68f8      	ldr	r0, [r7, #12]
 8004abe:	f000 fc47 	bl	8005350 <I2C_TransferConfig>
 8004ac2:	e00f      	b.n	8004ae4 <HAL_I2C_Mem_Write+0x110>
    }
    else
    {
      hi2c->XferSize = hi2c->XferCount;
 8004ac4:	68fb      	ldr	r3, [r7, #12]
 8004ac6:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 8004ac8:	b29a      	uxth	r2, r3
 8004aca:	68fb      	ldr	r3, [r7, #12]
 8004acc:	851a      	strh	r2, [r3, #40]	@ 0x28
      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
 8004ace:	68fb      	ldr	r3, [r7, #12]
 8004ad0:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 8004ad2:	b2da      	uxtb	r2, r3
 8004ad4:	8979      	ldrh	r1, [r7, #10]
 8004ad6:	2300      	movs	r3, #0
 8004ad8:	9300      	str	r3, [sp, #0]
 8004ada:	f04f 7300 	mov.w	r3, #33554432	@ 0x2000000
 8004ade:	68f8      	ldr	r0, [r7, #12]
 8004ae0:	f000 fc36 	bl	8005350 <I2C_TransferConfig>
    }

    do
    {
      /* Wait until TXIS flag is set */
      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
 8004ae4:	697a      	ldr	r2, [r7, #20]
 8004ae6:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
 8004ae8:	68f8      	ldr	r0, [r7, #12]
 8004aea:	f000 fac6 	bl	800507a <I2C_WaitOnTXISFlagUntilTimeout>
 8004aee:	4603      	mov	r3, r0
 8004af0:	2b00      	cmp	r3, #0
 8004af2:	d001      	beq.n	8004af8 <HAL_I2C_Mem_Write+0x124>
      {
        return HAL_ERROR;
 8004af4:	2301      	movs	r3, #1
 8004af6:	e07b      	b.n	8004bf0 <HAL_I2C_Mem_Write+0x21c>
      }

      /* Write data to TXDR */
      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
 8004af8:	68fb      	ldr	r3, [r7, #12]
 8004afa:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8004afc:	781a      	ldrb	r2, [r3, #0]
 8004afe:	68fb      	ldr	r3, [r7, #12]
 8004b00:	681b      	ldr	r3, [r3, #0]
 8004b02:	629a      	str	r2, [r3, #40]	@ 0x28

      /* Increment Buffer pointer */
      hi2c->pBuffPtr++;
 8004b04:	68fb      	ldr	r3, [r7, #12]
 8004b06:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8004b08:	1c5a      	adds	r2, r3, #1
 8004b0a:	68fb      	ldr	r3, [r7, #12]
 8004b0c:	625a      	str	r2, [r3, #36]	@ 0x24

      hi2c->XferCount--;
 8004b0e:	68fb      	ldr	r3, [r7, #12]
 8004b10:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 8004b12:	b29b      	uxth	r3, r3
 8004b14:	3b01      	subs	r3, #1
 8004b16:	b29a      	uxth	r2, r3
 8004b18:	68fb      	ldr	r3, [r7, #12]
 8004b1a:	855a      	strh	r2, [r3, #42]	@ 0x2a
      hi2c->XferSize--;
 8004b1c:	68fb      	ldr	r3, [r7, #12]
 8004b1e:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 8004b20:	3b01      	subs	r3, #1
 8004b22:	b29a      	uxth	r2, r3
 8004b24:	68fb      	ldr	r3, [r7, #12]
 8004b26:	851a      	strh	r2, [r3, #40]	@ 0x28

      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
 8004b28:	68fb      	ldr	r3, [r7, #12]
 8004b2a:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 8004b2c:	b29b      	uxth	r3, r3
 8004b2e:	2b00      	cmp	r3, #0
 8004b30:	d034      	beq.n	8004b9c <HAL_I2C_Mem_Write+0x1c8>
 8004b32:	68fb      	ldr	r3, [r7, #12]
 8004b34:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 8004b36:	2b00      	cmp	r3, #0
 8004b38:	d130      	bne.n	8004b9c <HAL_I2C_Mem_Write+0x1c8>
      {
        /* Wait until TCR flag is set */
        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
 8004b3a:	697b      	ldr	r3, [r7, #20]
 8004b3c:	9300      	str	r3, [sp, #0]
 8004b3e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8004b40:	2200      	movs	r2, #0
 8004b42:	2180      	movs	r1, #128	@ 0x80
 8004b44:	68f8      	ldr	r0, [r7, #12]
 8004b46:	f000 fa3f 	bl	8004fc8 <I2C_WaitOnFlagUntilTimeout>
 8004b4a:	4603      	mov	r3, r0
 8004b4c:	2b00      	cmp	r3, #0
 8004b4e:	d001      	beq.n	8004b54 <HAL_I2C_Mem_Write+0x180>
        {
          return HAL_ERROR;
 8004b50:	2301      	movs	r3, #1
 8004b52:	e04d      	b.n	8004bf0 <HAL_I2C_Mem_Write+0x21c>
        }

        if (hi2c->XferCount > MAX_NBYTE_SIZE)
 8004b54:	68fb      	ldr	r3, [r7, #12]
 8004b56:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 8004b58:	b29b      	uxth	r3, r3
 8004b5a:	2bff      	cmp	r3, #255	@ 0xff
 8004b5c:	d90e      	bls.n	8004b7c <HAL_I2C_Mem_Write+0x1a8>
        {
          hi2c->XferSize = MAX_NBYTE_SIZE;
 8004b5e:	68fb      	ldr	r3, [r7, #12]
 8004b60:	22ff      	movs	r2, #255	@ 0xff
 8004b62:	851a      	strh	r2, [r3, #40]	@ 0x28
          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
 8004b64:	68fb      	ldr	r3, [r7, #12]
 8004b66:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 8004b68:	b2da      	uxtb	r2, r3
 8004b6a:	8979      	ldrh	r1, [r7, #10]
 8004b6c:	2300      	movs	r3, #0
 8004b6e:	9300      	str	r3, [sp, #0]
 8004b70:	f04f 7380 	mov.w	r3, #16777216	@ 0x1000000
 8004b74:	68f8      	ldr	r0, [r7, #12]
 8004b76:	f000 fbeb 	bl	8005350 <I2C_TransferConfig>
 8004b7a:	e00f      	b.n	8004b9c <HAL_I2C_Mem_Write+0x1c8>
                             I2C_NO_STARTSTOP);
        }
        else
        {
          hi2c->XferSize = hi2c->XferCount;
 8004b7c:	68fb      	ldr	r3, [r7, #12]
 8004b7e:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 8004b80:	b29a      	uxth	r2, r3
 8004b82:	68fb      	ldr	r3, [r7, #12]
 8004b84:	851a      	strh	r2, [r3, #40]	@ 0x28
          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
 8004b86:	68fb      	ldr	r3, [r7, #12]
 8004b88:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 8004b8a:	b2da      	uxtb	r2, r3
 8004b8c:	8979      	ldrh	r1, [r7, #10]
 8004b8e:	2300      	movs	r3, #0
 8004b90:	9300      	str	r3, [sp, #0]
 8004b92:	f04f 7300 	mov.w	r3, #33554432	@ 0x2000000
 8004b96:	68f8      	ldr	r0, [r7, #12]
 8004b98:	f000 fbda 	bl	8005350 <I2C_TransferConfig>
                             I2C_NO_STARTSTOP);
        }
      }

    } while (hi2c->XferCount > 0U);
 8004b9c:	68fb      	ldr	r3, [r7, #12]
 8004b9e:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 8004ba0:	b29b      	uxth	r3, r3
 8004ba2:	2b00      	cmp	r3, #0
 8004ba4:	d19e      	bne.n	8004ae4 <HAL_I2C_Mem_Write+0x110>

    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
    /* Wait until STOPF flag is reset */
    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
 8004ba6:	697a      	ldr	r2, [r7, #20]
 8004ba8:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
 8004baa:	68f8      	ldr	r0, [r7, #12]
 8004bac:	f000 faac 	bl	8005108 <I2C_WaitOnSTOPFlagUntilTimeout>
 8004bb0:	4603      	mov	r3, r0
 8004bb2:	2b00      	cmp	r3, #0
 8004bb4:	d001      	beq.n	8004bba <HAL_I2C_Mem_Write+0x1e6>
    {
      return HAL_ERROR;
 8004bb6:	2301      	movs	r3, #1
 8004bb8:	e01a      	b.n	8004bf0 <HAL_I2C_Mem_Write+0x21c>
    }

    /* Clear STOP Flag */
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
 8004bba:	68fb      	ldr	r3, [r7, #12]
 8004bbc:	681b      	ldr	r3, [r3, #0]
 8004bbe:	2220      	movs	r2, #32
 8004bc0:	61da      	str	r2, [r3, #28]

    /* Clear Configuration Register 2 */
    I2C_RESET_CR2(hi2c);
 8004bc2:	68fb      	ldr	r3, [r7, #12]
 8004bc4:	681b      	ldr	r3, [r3, #0]
 8004bc6:	6859      	ldr	r1, [r3, #4]
 8004bc8:	68fb      	ldr	r3, [r7, #12]
 8004bca:	681a      	ldr	r2, [r3, #0]
 8004bcc:	4b0a      	ldr	r3, [pc, #40]	@ (8004bf8 <HAL_I2C_Mem_Write+0x224>)
 8004bce:	400b      	ands	r3, r1
 8004bd0:	6053      	str	r3, [r2, #4]

    hi2c->State = HAL_I2C_STATE_READY;
 8004bd2:	68fb      	ldr	r3, [r7, #12]
 8004bd4:	2220      	movs	r2, #32
 8004bd6:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
    hi2c->Mode  = HAL_I2C_MODE_NONE;
 8004bda:	68fb      	ldr	r3, [r7, #12]
 8004bdc:	2200      	movs	r2, #0
 8004bde:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);
 8004be2:	68fb      	ldr	r3, [r7, #12]
 8004be4:	2200      	movs	r2, #0
 8004be6:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    return HAL_OK;
 8004bea:	2300      	movs	r3, #0
 8004bec:	e000      	b.n	8004bf0 <HAL_I2C_Mem_Write+0x21c>
  }
  else
  {
    return HAL_BUSY;
 8004bee:	2302      	movs	r3, #2
  }
}
 8004bf0:	4618      	mov	r0, r3
 8004bf2:	3718      	adds	r7, #24
 8004bf4:	46bd      	mov	sp, r7
 8004bf6:	bd80      	pop	{r7, pc}
 8004bf8:	fe00e800 	.word	0xfe00e800

08004bfc <HAL_I2C_Mem_Read>:
  * @param  Timeout Timeout duration
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
                                   uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
 8004bfc:	b580      	push	{r7, lr}
 8004bfe:	b088      	sub	sp, #32
 8004c00:	af02      	add	r7, sp, #8
 8004c02:	60f8      	str	r0, [r7, #12]
 8004c04:	4608      	mov	r0, r1
 8004c06:	4611      	mov	r1, r2
 8004c08:	461a      	mov	r2, r3
 8004c0a:	4603      	mov	r3, r0
 8004c0c:	817b      	strh	r3, [r7, #10]
 8004c0e:	460b      	mov	r3, r1
 8004c10:	813b      	strh	r3, [r7, #8]
 8004c12:	4613      	mov	r3, r2
 8004c14:	80fb      	strh	r3, [r7, #6]
  uint32_t tickstart;

  /* Check the parameters */
  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));

  if (hi2c->State == HAL_I2C_STATE_READY)
 8004c16:	68fb      	ldr	r3, [r7, #12]
 8004c18:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
 8004c1c:	b2db      	uxtb	r3, r3
 8004c1e:	2b20      	cmp	r3, #32
 8004c20:	f040 80fd 	bne.w	8004e1e <HAL_I2C_Mem_Read+0x222>
  {
    if ((pData == NULL) || (Size == 0U))
 8004c24:	6a3b      	ldr	r3, [r7, #32]
 8004c26:	2b00      	cmp	r3, #0
 8004c28:	d002      	beq.n	8004c30 <HAL_I2C_Mem_Read+0x34>
 8004c2a:	8cbb      	ldrh	r3, [r7, #36]	@ 0x24
 8004c2c:	2b00      	cmp	r3, #0
 8004c2e:	d105      	bne.n	8004c3c <HAL_I2C_Mem_Read+0x40>
    {
      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
 8004c30:	68fb      	ldr	r3, [r7, #12]
 8004c32:	f44f 7200 	mov.w	r2, #512	@ 0x200
 8004c36:	645a      	str	r2, [r3, #68]	@ 0x44
      return  HAL_ERROR;
 8004c38:	2301      	movs	r3, #1
 8004c3a:	e0f1      	b.n	8004e20 <HAL_I2C_Mem_Read+0x224>
    }

    /* Process Locked */
    __HAL_LOCK(hi2c);
 8004c3c:	68fb      	ldr	r3, [r7, #12]
 8004c3e:	f893 3040 	ldrb.w	r3, [r3, #64]	@ 0x40
 8004c42:	2b01      	cmp	r3, #1
 8004c44:	d101      	bne.n	8004c4a <HAL_I2C_Mem_Read+0x4e>
 8004c46:	2302      	movs	r3, #2
 8004c48:	e0ea      	b.n	8004e20 <HAL_I2C_Mem_Read+0x224>
 8004c4a:	68fb      	ldr	r3, [r7, #12]
 8004c4c:	2201      	movs	r2, #1
 8004c4e:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    /* Init tickstart for timeout management*/
    tickstart = HAL_GetTick();
 8004c52:	f7ff fa63 	bl	800411c <HAL_GetTick>
 8004c56:	6178      	str	r0, [r7, #20]

    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
 8004c58:	697b      	ldr	r3, [r7, #20]
 8004c5a:	9300      	str	r3, [sp, #0]
 8004c5c:	2319      	movs	r3, #25
 8004c5e:	2201      	movs	r2, #1
 8004c60:	f44f 4100 	mov.w	r1, #32768	@ 0x8000
 8004c64:	68f8      	ldr	r0, [r7, #12]
 8004c66:	f000 f9af 	bl	8004fc8 <I2C_WaitOnFlagUntilTimeout>
 8004c6a:	4603      	mov	r3, r0
 8004c6c:	2b00      	cmp	r3, #0
 8004c6e:	d001      	beq.n	8004c74 <HAL_I2C_Mem_Read+0x78>
    {
      return HAL_ERROR;
 8004c70:	2301      	movs	r3, #1
 8004c72:	e0d5      	b.n	8004e20 <HAL_I2C_Mem_Read+0x224>
    }

    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
 8004c74:	68fb      	ldr	r3, [r7, #12]
 8004c76:	2222      	movs	r2, #34	@ 0x22
 8004c78:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
    hi2c->Mode      = HAL_I2C_MODE_MEM;
 8004c7c:	68fb      	ldr	r3, [r7, #12]
 8004c7e:	2240      	movs	r2, #64	@ 0x40
 8004c80:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 8004c84:	68fb      	ldr	r3, [r7, #12]
 8004c86:	2200      	movs	r2, #0
 8004c88:	645a      	str	r2, [r3, #68]	@ 0x44

    /* Prepare transfer parameters */
    hi2c->pBuffPtr  = pData;
 8004c8a:	68fb      	ldr	r3, [r7, #12]
 8004c8c:	6a3a      	ldr	r2, [r7, #32]
 8004c8e:	625a      	str	r2, [r3, #36]	@ 0x24
    hi2c->XferCount = Size;
 8004c90:	68fb      	ldr	r3, [r7, #12]
 8004c92:	8cba      	ldrh	r2, [r7, #36]	@ 0x24
 8004c94:	855a      	strh	r2, [r3, #42]	@ 0x2a
    hi2c->XferISR   = NULL;
 8004c96:	68fb      	ldr	r3, [r7, #12]
 8004c98:	2200      	movs	r2, #0
 8004c9a:	635a      	str	r2, [r3, #52]	@ 0x34

    /* Send Slave Address and Memory Address */
    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
 8004c9c:	88f8      	ldrh	r0, [r7, #6]
 8004c9e:	893a      	ldrh	r2, [r7, #8]
 8004ca0:	8979      	ldrh	r1, [r7, #10]
 8004ca2:	697b      	ldr	r3, [r7, #20]
 8004ca4:	9301      	str	r3, [sp, #4]
 8004ca6:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8004ca8:	9300      	str	r3, [sp, #0]
 8004caa:	4603      	mov	r3, r0
 8004cac:	68f8      	ldr	r0, [r7, #12]
 8004cae:	f000 f913 	bl	8004ed8 <I2C_RequestMemoryRead>
 8004cb2:	4603      	mov	r3, r0
 8004cb4:	2b00      	cmp	r3, #0
 8004cb6:	d005      	beq.n	8004cc4 <HAL_I2C_Mem_Read+0xc8>
    {
      /* Process Unlocked */
      __HAL_UNLOCK(hi2c);
 8004cb8:	68fb      	ldr	r3, [r7, #12]
 8004cba:	2200      	movs	r2, #0
 8004cbc:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
      return HAL_ERROR;
 8004cc0:	2301      	movs	r3, #1
 8004cc2:	e0ad      	b.n	8004e20 <HAL_I2C_Mem_Read+0x224>
    }

    /* Send Slave Address */
    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
    if (hi2c->XferCount > MAX_NBYTE_SIZE)
 8004cc4:	68fb      	ldr	r3, [r7, #12]
 8004cc6:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 8004cc8:	b29b      	uxth	r3, r3
 8004cca:	2bff      	cmp	r3, #255	@ 0xff
 8004ccc:	d90e      	bls.n	8004cec <HAL_I2C_Mem_Read+0xf0>
    {
      hi2c->XferSize = 1U;
 8004cce:	68fb      	ldr	r3, [r7, #12]
 8004cd0:	2201      	movs	r2, #1
 8004cd2:	851a      	strh	r2, [r3, #40]	@ 0x28
      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
 8004cd4:	68fb      	ldr	r3, [r7, #12]
 8004cd6:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 8004cd8:	b2da      	uxtb	r2, r3
 8004cda:	8979      	ldrh	r1, [r7, #10]
 8004cdc:	4b52      	ldr	r3, [pc, #328]	@ (8004e28 <HAL_I2C_Mem_Read+0x22c>)
 8004cde:	9300      	str	r3, [sp, #0]
 8004ce0:	f04f 7380 	mov.w	r3, #16777216	@ 0x1000000
 8004ce4:	68f8      	ldr	r0, [r7, #12]
 8004ce6:	f000 fb33 	bl	8005350 <I2C_TransferConfig>
 8004cea:	e00f      	b.n	8004d0c <HAL_I2C_Mem_Read+0x110>
                         I2C_GENERATE_START_READ);
    }
    else
    {
      hi2c->XferSize = hi2c->XferCount;
 8004cec:	68fb      	ldr	r3, [r7, #12]
 8004cee:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 8004cf0:	b29a      	uxth	r2, r3
 8004cf2:	68fb      	ldr	r3, [r7, #12]
 8004cf4:	851a      	strh	r2, [r3, #40]	@ 0x28
      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
 8004cf6:	68fb      	ldr	r3, [r7, #12]
 8004cf8:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 8004cfa:	b2da      	uxtb	r2, r3
 8004cfc:	8979      	ldrh	r1, [r7, #10]
 8004cfe:	4b4a      	ldr	r3, [pc, #296]	@ (8004e28 <HAL_I2C_Mem_Read+0x22c>)
 8004d00:	9300      	str	r3, [sp, #0]
 8004d02:	f04f 7300 	mov.w	r3, #33554432	@ 0x2000000
 8004d06:	68f8      	ldr	r0, [r7, #12]
 8004d08:	f000 fb22 	bl	8005350 <I2C_TransferConfig>
    }

    do
    {
      /* Wait until RXNE flag is set */
      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
 8004d0c:	697b      	ldr	r3, [r7, #20]
 8004d0e:	9300      	str	r3, [sp, #0]
 8004d10:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8004d12:	2200      	movs	r2, #0
 8004d14:	2104      	movs	r1, #4
 8004d16:	68f8      	ldr	r0, [r7, #12]
 8004d18:	f000 f956 	bl	8004fc8 <I2C_WaitOnFlagUntilTimeout>
 8004d1c:	4603      	mov	r3, r0
 8004d1e:	2b00      	cmp	r3, #0
 8004d20:	d001      	beq.n	8004d26 <HAL_I2C_Mem_Read+0x12a>
      {
        return HAL_ERROR;
 8004d22:	2301      	movs	r3, #1
 8004d24:	e07c      	b.n	8004e20 <HAL_I2C_Mem_Read+0x224>
      }

      /* Read data from RXDR */
      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
 8004d26:	68fb      	ldr	r3, [r7, #12]
 8004d28:	681b      	ldr	r3, [r3, #0]
 8004d2a:	6a5a      	ldr	r2, [r3, #36]	@ 0x24
 8004d2c:	68fb      	ldr	r3, [r7, #12]
 8004d2e:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8004d30:	b2d2      	uxtb	r2, r2
 8004d32:	701a      	strb	r2, [r3, #0]

      /* Increment Buffer pointer */
      hi2c->pBuffPtr++;
 8004d34:	68fb      	ldr	r3, [r7, #12]
 8004d36:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8004d38:	1c5a      	adds	r2, r3, #1
 8004d3a:	68fb      	ldr	r3, [r7, #12]
 8004d3c:	625a      	str	r2, [r3, #36]	@ 0x24

      hi2c->XferSize--;
 8004d3e:	68fb      	ldr	r3, [r7, #12]
 8004d40:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 8004d42:	3b01      	subs	r3, #1
 8004d44:	b29a      	uxth	r2, r3
 8004d46:	68fb      	ldr	r3, [r7, #12]
 8004d48:	851a      	strh	r2, [r3, #40]	@ 0x28
      hi2c->XferCount--;
 8004d4a:	68fb      	ldr	r3, [r7, #12]
 8004d4c:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 8004d4e:	b29b      	uxth	r3, r3
 8004d50:	3b01      	subs	r3, #1
 8004d52:	b29a      	uxth	r2, r3
 8004d54:	68fb      	ldr	r3, [r7, #12]
 8004d56:	855a      	strh	r2, [r3, #42]	@ 0x2a

      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
 8004d58:	68fb      	ldr	r3, [r7, #12]
 8004d5a:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 8004d5c:	b29b      	uxth	r3, r3
 8004d5e:	2b00      	cmp	r3, #0
 8004d60:	d034      	beq.n	8004dcc <HAL_I2C_Mem_Read+0x1d0>
 8004d62:	68fb      	ldr	r3, [r7, #12]
 8004d64:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 8004d66:	2b00      	cmp	r3, #0
 8004d68:	d130      	bne.n	8004dcc <HAL_I2C_Mem_Read+0x1d0>
      {
        /* Wait until TCR flag is set */
        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
 8004d6a:	697b      	ldr	r3, [r7, #20]
 8004d6c:	9300      	str	r3, [sp, #0]
 8004d6e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 8004d70:	2200      	movs	r2, #0
 8004d72:	2180      	movs	r1, #128	@ 0x80
 8004d74:	68f8      	ldr	r0, [r7, #12]
 8004d76:	f000 f927 	bl	8004fc8 <I2C_WaitOnFlagUntilTimeout>
 8004d7a:	4603      	mov	r3, r0
 8004d7c:	2b00      	cmp	r3, #0
 8004d7e:	d001      	beq.n	8004d84 <HAL_I2C_Mem_Read+0x188>
        {
          return HAL_ERROR;
 8004d80:	2301      	movs	r3, #1
 8004d82:	e04d      	b.n	8004e20 <HAL_I2C_Mem_Read+0x224>
        }

        if (hi2c->XferCount > MAX_NBYTE_SIZE)
 8004d84:	68fb      	ldr	r3, [r7, #12]
 8004d86:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 8004d88:	b29b      	uxth	r3, r3
 8004d8a:	2bff      	cmp	r3, #255	@ 0xff
 8004d8c:	d90e      	bls.n	8004dac <HAL_I2C_Mem_Read+0x1b0>
        {
          hi2c->XferSize = 1U;
 8004d8e:	68fb      	ldr	r3, [r7, #12]
 8004d90:	2201      	movs	r2, #1
 8004d92:	851a      	strh	r2, [r3, #40]	@ 0x28
          I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
 8004d94:	68fb      	ldr	r3, [r7, #12]
 8004d96:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 8004d98:	b2da      	uxtb	r2, r3
 8004d9a:	8979      	ldrh	r1, [r7, #10]
 8004d9c:	2300      	movs	r3, #0
 8004d9e:	9300      	str	r3, [sp, #0]
 8004da0:	f04f 7380 	mov.w	r3, #16777216	@ 0x1000000
 8004da4:	68f8      	ldr	r0, [r7, #12]
 8004da6:	f000 fad3 	bl	8005350 <I2C_TransferConfig>
 8004daa:	e00f      	b.n	8004dcc <HAL_I2C_Mem_Read+0x1d0>
                             I2C_NO_STARTSTOP);
        }
        else
        {
          hi2c->XferSize = hi2c->XferCount;
 8004dac:	68fb      	ldr	r3, [r7, #12]
 8004dae:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 8004db0:	b29a      	uxth	r2, r3
 8004db2:	68fb      	ldr	r3, [r7, #12]
 8004db4:	851a      	strh	r2, [r3, #40]	@ 0x28
          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
 8004db6:	68fb      	ldr	r3, [r7, #12]
 8004db8:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
 8004dba:	b2da      	uxtb	r2, r3
 8004dbc:	8979      	ldrh	r1, [r7, #10]
 8004dbe:	2300      	movs	r3, #0
 8004dc0:	9300      	str	r3, [sp, #0]
 8004dc2:	f04f 7300 	mov.w	r3, #33554432	@ 0x2000000
 8004dc6:	68f8      	ldr	r0, [r7, #12]
 8004dc8:	f000 fac2 	bl	8005350 <I2C_TransferConfig>
                             I2C_NO_STARTSTOP);
        }
      }
    } while (hi2c->XferCount > 0U);
 8004dcc:	68fb      	ldr	r3, [r7, #12]
 8004dce:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
 8004dd0:	b29b      	uxth	r3, r3
 8004dd2:	2b00      	cmp	r3, #0
 8004dd4:	d19a      	bne.n	8004d0c <HAL_I2C_Mem_Read+0x110>

    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
    /* Wait until STOPF flag is reset */
    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
 8004dd6:	697a      	ldr	r2, [r7, #20]
 8004dd8:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
 8004dda:	68f8      	ldr	r0, [r7, #12]
 8004ddc:	f000 f994 	bl	8005108 <I2C_WaitOnSTOPFlagUntilTimeout>
 8004de0:	4603      	mov	r3, r0
 8004de2:	2b00      	cmp	r3, #0
 8004de4:	d001      	beq.n	8004dea <HAL_I2C_Mem_Read+0x1ee>
    {
      return HAL_ERROR;
 8004de6:	2301      	movs	r3, #1
 8004de8:	e01a      	b.n	8004e20 <HAL_I2C_Mem_Read+0x224>
    }

    /* Clear STOP Flag */
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
 8004dea:	68fb      	ldr	r3, [r7, #12]
 8004dec:	681b      	ldr	r3, [r3, #0]
 8004dee:	2220      	movs	r2, #32
 8004df0:	61da      	str	r2, [r3, #28]

    /* Clear Configuration Register 2 */
    I2C_RESET_CR2(hi2c);
 8004df2:	68fb      	ldr	r3, [r7, #12]
 8004df4:	681b      	ldr	r3, [r3, #0]
 8004df6:	6859      	ldr	r1, [r3, #4]
 8004df8:	68fb      	ldr	r3, [r7, #12]
 8004dfa:	681a      	ldr	r2, [r3, #0]
 8004dfc:	4b0b      	ldr	r3, [pc, #44]	@ (8004e2c <HAL_I2C_Mem_Read+0x230>)
 8004dfe:	400b      	ands	r3, r1
 8004e00:	6053      	str	r3, [r2, #4]

    hi2c->State = HAL_I2C_STATE_READY;
 8004e02:	68fb      	ldr	r3, [r7, #12]
 8004e04:	2220      	movs	r2, #32
 8004e06:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
    hi2c->Mode  = HAL_I2C_MODE_NONE;
 8004e0a:	68fb      	ldr	r3, [r7, #12]
 8004e0c:	2200      	movs	r2, #0
 8004e0e:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);
 8004e12:	68fb      	ldr	r3, [r7, #12]
 8004e14:	2200      	movs	r2, #0
 8004e16:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    return HAL_OK;
 8004e1a:	2300      	movs	r3, #0
 8004e1c:	e000      	b.n	8004e20 <HAL_I2C_Mem_Read+0x224>
  }
  else
  {
    return HAL_BUSY;
 8004e1e:	2302      	movs	r3, #2
  }
}
 8004e20:	4618      	mov	r0, r3
 8004e22:	3718      	adds	r7, #24
 8004e24:	46bd      	mov	sp, r7
 8004e26:	bd80      	pop	{r7, pc}
 8004e28:	80002400 	.word	0x80002400
 8004e2c:	fe00e800 	.word	0xfe00e800

08004e30 <I2C_RequestMemoryWrite>:
  * @retval HAL status
  */
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
                                                uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
                                                uint32_t Tickstart)
{
 8004e30:	b580      	push	{r7, lr}
 8004e32:	b086      	sub	sp, #24
 8004e34:	af02      	add	r7, sp, #8
 8004e36:	60f8      	str	r0, [r7, #12]
 8004e38:	4608      	mov	r0, r1
 8004e3a:	4611      	mov	r1, r2
 8004e3c:	461a      	mov	r2, r3
 8004e3e:	4603      	mov	r3, r0
 8004e40:	817b      	strh	r3, [r7, #10]
 8004e42:	460b      	mov	r3, r1
 8004e44:	813b      	strh	r3, [r7, #8]
 8004e46:	4613      	mov	r3, r2
 8004e48:	80fb      	strh	r3, [r7, #6]
  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
 8004e4a:	88fb      	ldrh	r3, [r7, #6]
 8004e4c:	b2da      	uxtb	r2, r3
 8004e4e:	8979      	ldrh	r1, [r7, #10]
 8004e50:	4b20      	ldr	r3, [pc, #128]	@ (8004ed4 <I2C_RequestMemoryWrite+0xa4>)
 8004e52:	9300      	str	r3, [sp, #0]
 8004e54:	f04f 7380 	mov.w	r3, #16777216	@ 0x1000000
 8004e58:	68f8      	ldr	r0, [r7, #12]
 8004e5a:	f000 fa79 	bl	8005350 <I2C_TransferConfig>

  /* Wait until TXIS flag is set */
  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
 8004e5e:	69fa      	ldr	r2, [r7, #28]
 8004e60:	69b9      	ldr	r1, [r7, #24]
 8004e62:	68f8      	ldr	r0, [r7, #12]
 8004e64:	f000 f909 	bl	800507a <I2C_WaitOnTXISFlagUntilTimeout>
 8004e68:	4603      	mov	r3, r0
 8004e6a:	2b00      	cmp	r3, #0
 8004e6c:	d001      	beq.n	8004e72 <I2C_RequestMemoryWrite+0x42>
  {
    return HAL_ERROR;
 8004e6e:	2301      	movs	r3, #1
 8004e70:	e02c      	b.n	8004ecc <I2C_RequestMemoryWrite+0x9c>
  }

  /* If Memory address size is 8Bit */
  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
 8004e72:	88fb      	ldrh	r3, [r7, #6]
 8004e74:	2b01      	cmp	r3, #1
 8004e76:	d105      	bne.n	8004e84 <I2C_RequestMemoryWrite+0x54>
  {
    /* Send Memory Address */
    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
 8004e78:	893b      	ldrh	r3, [r7, #8]
 8004e7a:	b2da      	uxtb	r2, r3
 8004e7c:	68fb      	ldr	r3, [r7, #12]
 8004e7e:	681b      	ldr	r3, [r3, #0]
 8004e80:	629a      	str	r2, [r3, #40]	@ 0x28
 8004e82:	e015      	b.n	8004eb0 <I2C_RequestMemoryWrite+0x80>
  }
  /* If Memory address size is 16Bit */
  else
  {
    /* Send MSB of Memory Address */
    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
 8004e84:	893b      	ldrh	r3, [r7, #8]
 8004e86:	0a1b      	lsrs	r3, r3, #8
 8004e88:	b29b      	uxth	r3, r3
 8004e8a:	b2da      	uxtb	r2, r3
 8004e8c:	68fb      	ldr	r3, [r7, #12]
 8004e8e:	681b      	ldr	r3, [r3, #0]
 8004e90:	629a      	str	r2, [r3, #40]	@ 0x28

    /* Wait until TXIS flag is set */
    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
 8004e92:	69fa      	ldr	r2, [r7, #28]
 8004e94:	69b9      	ldr	r1, [r7, #24]
 8004e96:	68f8      	ldr	r0, [r7, #12]
 8004e98:	f000 f8ef 	bl	800507a <I2C_WaitOnTXISFlagUntilTimeout>
 8004e9c:	4603      	mov	r3, r0
 8004e9e:	2b00      	cmp	r3, #0
 8004ea0:	d001      	beq.n	8004ea6 <I2C_RequestMemoryWrite+0x76>
    {
      return HAL_ERROR;
 8004ea2:	2301      	movs	r3, #1
 8004ea4:	e012      	b.n	8004ecc <I2C_RequestMemoryWrite+0x9c>
    }

    /* Send LSB of Memory Address */
    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
 8004ea6:	893b      	ldrh	r3, [r7, #8]
 8004ea8:	b2da      	uxtb	r2, r3
 8004eaa:	68fb      	ldr	r3, [r7, #12]
 8004eac:	681b      	ldr	r3, [r3, #0]
 8004eae:	629a      	str	r2, [r3, #40]	@ 0x28
  }

  /* Wait until TCR flag is set */
  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
 8004eb0:	69fb      	ldr	r3, [r7, #28]
 8004eb2:	9300      	str	r3, [sp, #0]
 8004eb4:	69bb      	ldr	r3, [r7, #24]
 8004eb6:	2200      	movs	r2, #0
 8004eb8:	2180      	movs	r1, #128	@ 0x80
 8004eba:	68f8      	ldr	r0, [r7, #12]
 8004ebc:	f000 f884 	bl	8004fc8 <I2C_WaitOnFlagUntilTimeout>
 8004ec0:	4603      	mov	r3, r0
 8004ec2:	2b00      	cmp	r3, #0
 8004ec4:	d001      	beq.n	8004eca <I2C_RequestMemoryWrite+0x9a>
  {
    return HAL_ERROR;
 8004ec6:	2301      	movs	r3, #1
 8004ec8:	e000      	b.n	8004ecc <I2C_RequestMemoryWrite+0x9c>
  }

  return HAL_OK;
 8004eca:	2300      	movs	r3, #0
}
 8004ecc:	4618      	mov	r0, r3
 8004ece:	3710      	adds	r7, #16
 8004ed0:	46bd      	mov	sp, r7
 8004ed2:	bd80      	pop	{r7, pc}
 8004ed4:	80002000 	.word	0x80002000

08004ed8 <I2C_RequestMemoryRead>:
  * @retval HAL status
  */
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
                                               uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
                                               uint32_t Tickstart)
{
 8004ed8:	b580      	push	{r7, lr}
 8004eda:	b086      	sub	sp, #24
 8004edc:	af02      	add	r7, sp, #8
 8004ede:	60f8      	str	r0, [r7, #12]
 8004ee0:	4608      	mov	r0, r1
 8004ee2:	4611      	mov	r1, r2
 8004ee4:	461a      	mov	r2, r3
 8004ee6:	4603      	mov	r3, r0
 8004ee8:	817b      	strh	r3, [r7, #10]
 8004eea:	460b      	mov	r3, r1
 8004eec:	813b      	strh	r3, [r7, #8]
 8004eee:	4613      	mov	r3, r2
 8004ef0:	80fb      	strh	r3, [r7, #6]
  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
 8004ef2:	88fb      	ldrh	r3, [r7, #6]
 8004ef4:	b2da      	uxtb	r2, r3
 8004ef6:	8979      	ldrh	r1, [r7, #10]
 8004ef8:	4b20      	ldr	r3, [pc, #128]	@ (8004f7c <I2C_RequestMemoryRead+0xa4>)
 8004efa:	9300      	str	r3, [sp, #0]
 8004efc:	2300      	movs	r3, #0
 8004efe:	68f8      	ldr	r0, [r7, #12]
 8004f00:	f000 fa26 	bl	8005350 <I2C_TransferConfig>

  /* Wait until TXIS flag is set */
  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
 8004f04:	69fa      	ldr	r2, [r7, #28]
 8004f06:	69b9      	ldr	r1, [r7, #24]
 8004f08:	68f8      	ldr	r0, [r7, #12]
 8004f0a:	f000 f8b6 	bl	800507a <I2C_WaitOnTXISFlagUntilTimeout>
 8004f0e:	4603      	mov	r3, r0
 8004f10:	2b00      	cmp	r3, #0
 8004f12:	d001      	beq.n	8004f18 <I2C_RequestMemoryRead+0x40>
  {
    return HAL_ERROR;
 8004f14:	2301      	movs	r3, #1
 8004f16:	e02c      	b.n	8004f72 <I2C_RequestMemoryRead+0x9a>
  }

  /* If Memory address size is 8Bit */
  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
 8004f18:	88fb      	ldrh	r3, [r7, #6]
 8004f1a:	2b01      	cmp	r3, #1
 8004f1c:	d105      	bne.n	8004f2a <I2C_RequestMemoryRead+0x52>
  {
    /* Send Memory Address */
    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
 8004f1e:	893b      	ldrh	r3, [r7, #8]
 8004f20:	b2da      	uxtb	r2, r3
 8004f22:	68fb      	ldr	r3, [r7, #12]
 8004f24:	681b      	ldr	r3, [r3, #0]
 8004f26:	629a      	str	r2, [r3, #40]	@ 0x28
 8004f28:	e015      	b.n	8004f56 <I2C_RequestMemoryRead+0x7e>
  }
  /* If Memory address size is 16Bit */
  else
  {
    /* Send MSB of Memory Address */
    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
 8004f2a:	893b      	ldrh	r3, [r7, #8]
 8004f2c:	0a1b      	lsrs	r3, r3, #8
 8004f2e:	b29b      	uxth	r3, r3
 8004f30:	b2da      	uxtb	r2, r3
 8004f32:	68fb      	ldr	r3, [r7, #12]
 8004f34:	681b      	ldr	r3, [r3, #0]
 8004f36:	629a      	str	r2, [r3, #40]	@ 0x28

    /* Wait until TXIS flag is set */
    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
 8004f38:	69fa      	ldr	r2, [r7, #28]
 8004f3a:	69b9      	ldr	r1, [r7, #24]
 8004f3c:	68f8      	ldr	r0, [r7, #12]
 8004f3e:	f000 f89c 	bl	800507a <I2C_WaitOnTXISFlagUntilTimeout>
 8004f42:	4603      	mov	r3, r0
 8004f44:	2b00      	cmp	r3, #0
 8004f46:	d001      	beq.n	8004f4c <I2C_RequestMemoryRead+0x74>
    {
      return HAL_ERROR;
 8004f48:	2301      	movs	r3, #1
 8004f4a:	e012      	b.n	8004f72 <I2C_RequestMemoryRead+0x9a>
    }

    /* Send LSB of Memory Address */
    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
 8004f4c:	893b      	ldrh	r3, [r7, #8]
 8004f4e:	b2da      	uxtb	r2, r3
 8004f50:	68fb      	ldr	r3, [r7, #12]
 8004f52:	681b      	ldr	r3, [r3, #0]
 8004f54:	629a      	str	r2, [r3, #40]	@ 0x28
  }

  /* Wait until TC flag is set */
  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
 8004f56:	69fb      	ldr	r3, [r7, #28]
 8004f58:	9300      	str	r3, [sp, #0]
 8004f5a:	69bb      	ldr	r3, [r7, #24]
 8004f5c:	2200      	movs	r2, #0
 8004f5e:	2140      	movs	r1, #64	@ 0x40
 8004f60:	68f8      	ldr	r0, [r7, #12]
 8004f62:	f000 f831 	bl	8004fc8 <I2C_WaitOnFlagUntilTimeout>
 8004f66:	4603      	mov	r3, r0
 8004f68:	2b00      	cmp	r3, #0
 8004f6a:	d001      	beq.n	8004f70 <I2C_RequestMemoryRead+0x98>
  {
    return HAL_ERROR;
 8004f6c:	2301      	movs	r3, #1
 8004f6e:	e000      	b.n	8004f72 <I2C_RequestMemoryRead+0x9a>
  }

  return HAL_OK;
 8004f70:	2300      	movs	r3, #0
}
 8004f72:	4618      	mov	r0, r3
 8004f74:	3710      	adds	r7, #16
 8004f76:	46bd      	mov	sp, r7
 8004f78:	bd80      	pop	{r7, pc}
 8004f7a:	bf00      	nop
 8004f7c:	80002000 	.word	0x80002000

08004f80 <I2C_Flush_TXDR>:
  * @brief  I2C Tx data register flush process.
  * @param  hi2c I2C handle.
  * @retval None
  */
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
{
 8004f80:	b480      	push	{r7}
 8004f82:	b083      	sub	sp, #12
 8004f84:	af00      	add	r7, sp, #0
 8004f86:	6078      	str	r0, [r7, #4]
  /* If a pending TXIS flag is set */
  /* Write a dummy data in TXDR to clear it */
  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
 8004f88:	687b      	ldr	r3, [r7, #4]
 8004f8a:	681b      	ldr	r3, [r3, #0]
 8004f8c:	699b      	ldr	r3, [r3, #24]
 8004f8e:	f003 0302 	and.w	r3, r3, #2
 8004f92:	2b02      	cmp	r3, #2
 8004f94:	d103      	bne.n	8004f9e <I2C_Flush_TXDR+0x1e>
  {
    hi2c->Instance->TXDR = 0x00U;
 8004f96:	687b      	ldr	r3, [r7, #4]
 8004f98:	681b      	ldr	r3, [r3, #0]
 8004f9a:	2200      	movs	r2, #0
 8004f9c:	629a      	str	r2, [r3, #40]	@ 0x28
  }

  /* Flush TX register if not empty */
  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
 8004f9e:	687b      	ldr	r3, [r7, #4]
 8004fa0:	681b      	ldr	r3, [r3, #0]
 8004fa2:	699b      	ldr	r3, [r3, #24]
 8004fa4:	f003 0301 	and.w	r3, r3, #1
 8004fa8:	2b01      	cmp	r3, #1
 8004faa:	d007      	beq.n	8004fbc <I2C_Flush_TXDR+0x3c>
  {
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
 8004fac:	687b      	ldr	r3, [r7, #4]
 8004fae:	681b      	ldr	r3, [r3, #0]
 8004fb0:	699a      	ldr	r2, [r3, #24]
 8004fb2:	687b      	ldr	r3, [r7, #4]
 8004fb4:	681b      	ldr	r3, [r3, #0]
 8004fb6:	f042 0201 	orr.w	r2, r2, #1
 8004fba:	619a      	str	r2, [r3, #24]
  }
}
 8004fbc:	bf00      	nop
 8004fbe:	370c      	adds	r7, #12
 8004fc0:	46bd      	mov	sp, r7
 8004fc2:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004fc6:	4770      	bx	lr

08004fc8 <I2C_WaitOnFlagUntilTimeout>:
  * @param  Tickstart Tick start value
  * @retval HAL status
  */
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
                                                    uint32_t Timeout, uint32_t Tickstart)
{
 8004fc8:	b580      	push	{r7, lr}
 8004fca:	b084      	sub	sp, #16
 8004fcc:	af00      	add	r7, sp, #0
 8004fce:	60f8      	str	r0, [r7, #12]
 8004fd0:	60b9      	str	r1, [r7, #8]
 8004fd2:	603b      	str	r3, [r7, #0]
 8004fd4:	4613      	mov	r3, r2
 8004fd6:	71fb      	strb	r3, [r7, #7]
  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
 8004fd8:	e03b      	b.n	8005052 <I2C_WaitOnFlagUntilTimeout+0x8a>
  {
    /* Check if an error is detected */
    if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
 8004fda:	69ba      	ldr	r2, [r7, #24]
 8004fdc:	6839      	ldr	r1, [r7, #0]
 8004fde:	68f8      	ldr	r0, [r7, #12]
 8004fe0:	f000 f8d6 	bl	8005190 <I2C_IsErrorOccurred>
 8004fe4:	4603      	mov	r3, r0
 8004fe6:	2b00      	cmp	r3, #0
 8004fe8:	d001      	beq.n	8004fee <I2C_WaitOnFlagUntilTimeout+0x26>
    {
      return HAL_ERROR;
 8004fea:	2301      	movs	r3, #1
 8004fec:	e041      	b.n	8005072 <I2C_WaitOnFlagUntilTimeout+0xaa>
    }

    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 8004fee:	683b      	ldr	r3, [r7, #0]
 8004ff0:	f1b3 3fff 	cmp.w	r3, #4294967295
 8004ff4:	d02d      	beq.n	8005052 <I2C_WaitOnFlagUntilTimeout+0x8a>
    {
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 8004ff6:	f7ff f891 	bl	800411c <HAL_GetTick>
 8004ffa:	4602      	mov	r2, r0
 8004ffc:	69bb      	ldr	r3, [r7, #24]
 8004ffe:	1ad3      	subs	r3, r2, r3
 8005000:	683a      	ldr	r2, [r7, #0]
 8005002:	429a      	cmp	r2, r3
 8005004:	d302      	bcc.n	800500c <I2C_WaitOnFlagUntilTimeout+0x44>
 8005006:	683b      	ldr	r3, [r7, #0]
 8005008:	2b00      	cmp	r3, #0
 800500a:	d122      	bne.n	8005052 <I2C_WaitOnFlagUntilTimeout+0x8a>
      {
        if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
 800500c:	68fb      	ldr	r3, [r7, #12]
 800500e:	681b      	ldr	r3, [r3, #0]
 8005010:	699a      	ldr	r2, [r3, #24]
 8005012:	68bb      	ldr	r3, [r7, #8]
 8005014:	4013      	ands	r3, r2
 8005016:	68ba      	ldr	r2, [r7, #8]
 8005018:	429a      	cmp	r2, r3
 800501a:	bf0c      	ite	eq
 800501c:	2301      	moveq	r3, #1
 800501e:	2300      	movne	r3, #0
 8005020:	b2db      	uxtb	r3, r3
 8005022:	461a      	mov	r2, r3
 8005024:	79fb      	ldrb	r3, [r7, #7]
 8005026:	429a      	cmp	r2, r3
 8005028:	d113      	bne.n	8005052 <I2C_WaitOnFlagUntilTimeout+0x8a>
        {
          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
 800502a:	68fb      	ldr	r3, [r7, #12]
 800502c:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 800502e:	f043 0220 	orr.w	r2, r3, #32
 8005032:	68fb      	ldr	r3, [r7, #12]
 8005034:	645a      	str	r2, [r3, #68]	@ 0x44
          hi2c->State = HAL_I2C_STATE_READY;
 8005036:	68fb      	ldr	r3, [r7, #12]
 8005038:	2220      	movs	r2, #32
 800503a:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
          hi2c->Mode = HAL_I2C_MODE_NONE;
 800503e:	68fb      	ldr	r3, [r7, #12]
 8005040:	2200      	movs	r2, #0
 8005042:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42

          /* Process Unlocked */
          __HAL_UNLOCK(hi2c);
 8005046:	68fb      	ldr	r3, [r7, #12]
 8005048:	2200      	movs	r2, #0
 800504a:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
          return HAL_ERROR;
 800504e:	2301      	movs	r3, #1
 8005050:	e00f      	b.n	8005072 <I2C_WaitOnFlagUntilTimeout+0xaa>
  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
 8005052:	68fb      	ldr	r3, [r7, #12]
 8005054:	681b      	ldr	r3, [r3, #0]
 8005056:	699a      	ldr	r2, [r3, #24]
 8005058:	68bb      	ldr	r3, [r7, #8]
 800505a:	4013      	ands	r3, r2
 800505c:	68ba      	ldr	r2, [r7, #8]
 800505e:	429a      	cmp	r2, r3
 8005060:	bf0c      	ite	eq
 8005062:	2301      	moveq	r3, #1
 8005064:	2300      	movne	r3, #0
 8005066:	b2db      	uxtb	r3, r3
 8005068:	461a      	mov	r2, r3
 800506a:	79fb      	ldrb	r3, [r7, #7]
 800506c:	429a      	cmp	r2, r3
 800506e:	d0b4      	beq.n	8004fda <I2C_WaitOnFlagUntilTimeout+0x12>
        }
      }
    }
  }
  return HAL_OK;
 8005070:	2300      	movs	r3, #0
}
 8005072:	4618      	mov	r0, r3
 8005074:	3710      	adds	r7, #16
 8005076:	46bd      	mov	sp, r7
 8005078:	bd80      	pop	{r7, pc}

0800507a <I2C_WaitOnTXISFlagUntilTimeout>:
  * @param  Tickstart Tick start value
  * @retval HAL status
  */
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
                                                        uint32_t Tickstart)
{
 800507a:	b580      	push	{r7, lr}
 800507c:	b084      	sub	sp, #16
 800507e:	af00      	add	r7, sp, #0
 8005080:	60f8      	str	r0, [r7, #12]
 8005082:	60b9      	str	r1, [r7, #8]
 8005084:	607a      	str	r2, [r7, #4]
  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
 8005086:	e033      	b.n	80050f0 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
  {
    /* Check if an error is detected */
    if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
 8005088:	687a      	ldr	r2, [r7, #4]
 800508a:	68b9      	ldr	r1, [r7, #8]
 800508c:	68f8      	ldr	r0, [r7, #12]
 800508e:	f000 f87f 	bl	8005190 <I2C_IsErrorOccurred>
 8005092:	4603      	mov	r3, r0
 8005094:	2b00      	cmp	r3, #0
 8005096:	d001      	beq.n	800509c <I2C_WaitOnTXISFlagUntilTimeout+0x22>
    {
      return HAL_ERROR;
 8005098:	2301      	movs	r3, #1
 800509a:	e031      	b.n	8005100 <I2C_WaitOnTXISFlagUntilTimeout+0x86>
    }

    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 800509c:	68bb      	ldr	r3, [r7, #8]
 800509e:	f1b3 3fff 	cmp.w	r3, #4294967295
 80050a2:	d025      	beq.n	80050f0 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
    {
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 80050a4:	f7ff f83a 	bl	800411c <HAL_GetTick>
 80050a8:	4602      	mov	r2, r0
 80050aa:	687b      	ldr	r3, [r7, #4]
 80050ac:	1ad3      	subs	r3, r2, r3
 80050ae:	68ba      	ldr	r2, [r7, #8]
 80050b0:	429a      	cmp	r2, r3
 80050b2:	d302      	bcc.n	80050ba <I2C_WaitOnTXISFlagUntilTimeout+0x40>
 80050b4:	68bb      	ldr	r3, [r7, #8]
 80050b6:	2b00      	cmp	r3, #0
 80050b8:	d11a      	bne.n	80050f0 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
      {
        if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
 80050ba:	68fb      	ldr	r3, [r7, #12]
 80050bc:	681b      	ldr	r3, [r3, #0]
 80050be:	699b      	ldr	r3, [r3, #24]
 80050c0:	f003 0302 	and.w	r3, r3, #2
 80050c4:	2b02      	cmp	r3, #2
 80050c6:	d013      	beq.n	80050f0 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
        {
          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
 80050c8:	68fb      	ldr	r3, [r7, #12]
 80050ca:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 80050cc:	f043 0220 	orr.w	r2, r3, #32
 80050d0:	68fb      	ldr	r3, [r7, #12]
 80050d2:	645a      	str	r2, [r3, #68]	@ 0x44
          hi2c->State = HAL_I2C_STATE_READY;
 80050d4:	68fb      	ldr	r3, [r7, #12]
 80050d6:	2220      	movs	r2, #32
 80050d8:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
          hi2c->Mode = HAL_I2C_MODE_NONE;
 80050dc:	68fb      	ldr	r3, [r7, #12]
 80050de:	2200      	movs	r2, #0
 80050e0:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42

          /* Process Unlocked */
          __HAL_UNLOCK(hi2c);
 80050e4:	68fb      	ldr	r3, [r7, #12]
 80050e6:	2200      	movs	r2, #0
 80050e8:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

          return HAL_ERROR;
 80050ec:	2301      	movs	r3, #1
 80050ee:	e007      	b.n	8005100 <I2C_WaitOnTXISFlagUntilTimeout+0x86>
  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
 80050f0:	68fb      	ldr	r3, [r7, #12]
 80050f2:	681b      	ldr	r3, [r3, #0]
 80050f4:	699b      	ldr	r3, [r3, #24]
 80050f6:	f003 0302 	and.w	r3, r3, #2
 80050fa:	2b02      	cmp	r3, #2
 80050fc:	d1c4      	bne.n	8005088 <I2C_WaitOnTXISFlagUntilTimeout+0xe>
        }
      }
    }
  }
  return HAL_OK;
 80050fe:	2300      	movs	r3, #0
}
 8005100:	4618      	mov	r0, r3
 8005102:	3710      	adds	r7, #16
 8005104:	46bd      	mov	sp, r7
 8005106:	bd80      	pop	{r7, pc}

08005108 <I2C_WaitOnSTOPFlagUntilTimeout>:
  * @param  Tickstart Tick start value
  * @retval HAL status
  */
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
                                                        uint32_t Tickstart)
{
 8005108:	b580      	push	{r7, lr}
 800510a:	b084      	sub	sp, #16
 800510c:	af00      	add	r7, sp, #0
 800510e:	60f8      	str	r0, [r7, #12]
 8005110:	60b9      	str	r1, [r7, #8]
 8005112:	607a      	str	r2, [r7, #4]
  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
 8005114:	e02f      	b.n	8005176 <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
  {
    /* Check if an error is detected */
    if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
 8005116:	687a      	ldr	r2, [r7, #4]
 8005118:	68b9      	ldr	r1, [r7, #8]
 800511a:	68f8      	ldr	r0, [r7, #12]
 800511c:	f000 f838 	bl	8005190 <I2C_IsErrorOccurred>
 8005120:	4603      	mov	r3, r0
 8005122:	2b00      	cmp	r3, #0
 8005124:	d001      	beq.n	800512a <I2C_WaitOnSTOPFlagUntilTimeout+0x22>
    {
      return HAL_ERROR;
 8005126:	2301      	movs	r3, #1
 8005128:	e02d      	b.n	8005186 <I2C_WaitOnSTOPFlagUntilTimeout+0x7e>
    }

    /* Check for the Timeout */
    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 800512a:	f7fe fff7 	bl	800411c <HAL_GetTick>
 800512e:	4602      	mov	r2, r0
 8005130:	687b      	ldr	r3, [r7, #4]
 8005132:	1ad3      	subs	r3, r2, r3
 8005134:	68ba      	ldr	r2, [r7, #8]
 8005136:	429a      	cmp	r2, r3
 8005138:	d302      	bcc.n	8005140 <I2C_WaitOnSTOPFlagUntilTimeout+0x38>
 800513a:	68bb      	ldr	r3, [r7, #8]
 800513c:	2b00      	cmp	r3, #0
 800513e:	d11a      	bne.n	8005176 <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
    {
      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
 8005140:	68fb      	ldr	r3, [r7, #12]
 8005142:	681b      	ldr	r3, [r3, #0]
 8005144:	699b      	ldr	r3, [r3, #24]
 8005146:	f003 0320 	and.w	r3, r3, #32
 800514a:	2b20      	cmp	r3, #32
 800514c:	d013      	beq.n	8005176 <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
      {
        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
 800514e:	68fb      	ldr	r3, [r7, #12]
 8005150:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 8005152:	f043 0220 	orr.w	r2, r3, #32
 8005156:	68fb      	ldr	r3, [r7, #12]
 8005158:	645a      	str	r2, [r3, #68]	@ 0x44
        hi2c->State = HAL_I2C_STATE_READY;
 800515a:	68fb      	ldr	r3, [r7, #12]
 800515c:	2220      	movs	r2, #32
 800515e:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
        hi2c->Mode = HAL_I2C_MODE_NONE;
 8005162:	68fb      	ldr	r3, [r7, #12]
 8005164:	2200      	movs	r2, #0
 8005166:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);
 800516a:	68fb      	ldr	r3, [r7, #12]
 800516c:	2200      	movs	r2, #0
 800516e:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

        return HAL_ERROR;
 8005172:	2301      	movs	r3, #1
 8005174:	e007      	b.n	8005186 <I2C_WaitOnSTOPFlagUntilTimeout+0x7e>
  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
 8005176:	68fb      	ldr	r3, [r7, #12]
 8005178:	681b      	ldr	r3, [r3, #0]
 800517a:	699b      	ldr	r3, [r3, #24]
 800517c:	f003 0320 	and.w	r3, r3, #32
 8005180:	2b20      	cmp	r3, #32
 8005182:	d1c8      	bne.n	8005116 <I2C_WaitOnSTOPFlagUntilTimeout+0xe>
      }
    }
  }
  return HAL_OK;
 8005184:	2300      	movs	r3, #0
}
 8005186:	4618      	mov	r0, r3
 8005188:	3710      	adds	r7, #16
 800518a:	46bd      	mov	sp, r7
 800518c:	bd80      	pop	{r7, pc}
	...

08005190 <I2C_IsErrorOccurred>:
  * @param  Timeout Timeout duration
  * @param  Tickstart Tick start value
  * @retval HAL status
  */
static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
 8005190:	b580      	push	{r7, lr}
 8005192:	b08a      	sub	sp, #40	@ 0x28
 8005194:	af00      	add	r7, sp, #0
 8005196:	60f8      	str	r0, [r7, #12]
 8005198:	60b9      	str	r1, [r7, #8]
 800519a:	607a      	str	r2, [r7, #4]
  HAL_StatusTypeDef status = HAL_OK;
 800519c:	2300      	movs	r3, #0
 800519e:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27
  uint32_t itflag   = hi2c->Instance->ISR;
 80051a2:	68fb      	ldr	r3, [r7, #12]
 80051a4:	681b      	ldr	r3, [r3, #0]
 80051a6:	699b      	ldr	r3, [r3, #24]
 80051a8:	61bb      	str	r3, [r7, #24]
  uint32_t error_code = 0;
 80051aa:	2300      	movs	r3, #0
 80051ac:	623b      	str	r3, [r7, #32]
  uint32_t tickstart = Tickstart;
 80051ae:	687b      	ldr	r3, [r7, #4]
 80051b0:	61fb      	str	r3, [r7, #28]
  uint32_t tmp1;
  HAL_I2C_ModeTypeDef tmp2;

  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
 80051b2:	69bb      	ldr	r3, [r7, #24]
 80051b4:	f003 0310 	and.w	r3, r3, #16
 80051b8:	2b00      	cmp	r3, #0
 80051ba:	d068      	beq.n	800528e <I2C_IsErrorOccurred+0xfe>
  {
    /* Clear NACKF Flag */
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
 80051bc:	68fb      	ldr	r3, [r7, #12]
 80051be:	681b      	ldr	r3, [r3, #0]
 80051c0:	2210      	movs	r2, #16
 80051c2:	61da      	str	r2, [r3, #28]

    /* Wait until STOP Flag is set or timeout occurred */
    /* AutoEnd should be initiate after AF */
    while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
 80051c4:	e049      	b.n	800525a <I2C_IsErrorOccurred+0xca>
    {
      /* Check for the Timeout */
      if (Timeout != HAL_MAX_DELAY)
 80051c6:	68bb      	ldr	r3, [r7, #8]
 80051c8:	f1b3 3fff 	cmp.w	r3, #4294967295
 80051cc:	d045      	beq.n	800525a <I2C_IsErrorOccurred+0xca>
      {
        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
 80051ce:	f7fe ffa5 	bl	800411c <HAL_GetTick>
 80051d2:	4602      	mov	r2, r0
 80051d4:	69fb      	ldr	r3, [r7, #28]
 80051d6:	1ad3      	subs	r3, r2, r3
 80051d8:	68ba      	ldr	r2, [r7, #8]
 80051da:	429a      	cmp	r2, r3
 80051dc:	d302      	bcc.n	80051e4 <I2C_IsErrorOccurred+0x54>
 80051de:	68bb      	ldr	r3, [r7, #8]
 80051e0:	2b00      	cmp	r3, #0
 80051e2:	d13a      	bne.n	800525a <I2C_IsErrorOccurred+0xca>
        {
          tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
 80051e4:	68fb      	ldr	r3, [r7, #12]
 80051e6:	681b      	ldr	r3, [r3, #0]
 80051e8:	685b      	ldr	r3, [r3, #4]
 80051ea:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
 80051ee:	617b      	str	r3, [r7, #20]
          tmp2 = hi2c->Mode;
 80051f0:	68fb      	ldr	r3, [r7, #12]
 80051f2:	f893 3042 	ldrb.w	r3, [r3, #66]	@ 0x42
 80051f6:	74fb      	strb	r3, [r7, #19]

          /* In case of I2C still busy, try to regenerate a STOP manually */
          if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
 80051f8:	68fb      	ldr	r3, [r7, #12]
 80051fa:	681b      	ldr	r3, [r3, #0]
 80051fc:	699b      	ldr	r3, [r3, #24]
 80051fe:	f403 4300 	and.w	r3, r3, #32768	@ 0x8000
 8005202:	f5b3 4f00 	cmp.w	r3, #32768	@ 0x8000
 8005206:	d121      	bne.n	800524c <I2C_IsErrorOccurred+0xbc>
 8005208:	697b      	ldr	r3, [r7, #20]
 800520a:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
 800520e:	d01d      	beq.n	800524c <I2C_IsErrorOccurred+0xbc>
              (tmp1 != I2C_CR2_STOP) && \
 8005210:	7cfb      	ldrb	r3, [r7, #19]
 8005212:	2b20      	cmp	r3, #32
 8005214:	d01a      	beq.n	800524c <I2C_IsErrorOccurred+0xbc>
              (tmp2 != HAL_I2C_MODE_SLAVE))
          {
            /* Generate Stop */
            hi2c->Instance->CR2 |= I2C_CR2_STOP;
 8005216:	68fb      	ldr	r3, [r7, #12]
 8005218:	681b      	ldr	r3, [r3, #0]
 800521a:	685a      	ldr	r2, [r3, #4]
 800521c:	68fb      	ldr	r3, [r7, #12]
 800521e:	681b      	ldr	r3, [r3, #0]
 8005220:	f442 4280 	orr.w	r2, r2, #16384	@ 0x4000
 8005224:	605a      	str	r2, [r3, #4]

            /* Update Tick with new reference */
            tickstart = HAL_GetTick();
 8005226:	f7fe ff79 	bl	800411c <HAL_GetTick>
 800522a:	61f8      	str	r0, [r7, #28]
          }

          while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
 800522c:	e00e      	b.n	800524c <I2C_IsErrorOccurred+0xbc>
          {
            /* Check for the Timeout */
            if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
 800522e:	f7fe ff75 	bl	800411c <HAL_GetTick>
 8005232:	4602      	mov	r2, r0
 8005234:	69fb      	ldr	r3, [r7, #28]
 8005236:	1ad3      	subs	r3, r2, r3
 8005238:	2b19      	cmp	r3, #25
 800523a:	d907      	bls.n	800524c <I2C_IsErrorOccurred+0xbc>
            {
              error_code |= HAL_I2C_ERROR_TIMEOUT;
 800523c:	6a3b      	ldr	r3, [r7, #32]
 800523e:	f043 0320 	orr.w	r3, r3, #32
 8005242:	623b      	str	r3, [r7, #32]

              status = HAL_ERROR;
 8005244:	2301      	movs	r3, #1
 8005246:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27

              break;
 800524a:	e006      	b.n	800525a <I2C_IsErrorOccurred+0xca>
          while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
 800524c:	68fb      	ldr	r3, [r7, #12]
 800524e:	681b      	ldr	r3, [r3, #0]
 8005250:	699b      	ldr	r3, [r3, #24]
 8005252:	f003 0320 	and.w	r3, r3, #32
 8005256:	2b20      	cmp	r3, #32
 8005258:	d1e9      	bne.n	800522e <I2C_IsErrorOccurred+0x9e>
    while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
 800525a:	68fb      	ldr	r3, [r7, #12]
 800525c:	681b      	ldr	r3, [r3, #0]
 800525e:	699b      	ldr	r3, [r3, #24]
 8005260:	f003 0320 	and.w	r3, r3, #32
 8005264:	2b20      	cmp	r3, #32
 8005266:	d003      	beq.n	8005270 <I2C_IsErrorOccurred+0xe0>
 8005268:	f897 3027 	ldrb.w	r3, [r7, #39]	@ 0x27
 800526c:	2b00      	cmp	r3, #0
 800526e:	d0aa      	beq.n	80051c6 <I2C_IsErrorOccurred+0x36>
        }
      }
    }

    /* In case STOP Flag is detected, clear it */
    if (status == HAL_OK)
 8005270:	f897 3027 	ldrb.w	r3, [r7, #39]	@ 0x27
 8005274:	2b00      	cmp	r3, #0
 8005276:	d103      	bne.n	8005280 <I2C_IsErrorOccurred+0xf0>
    {
      /* Clear STOP Flag */
      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
 8005278:	68fb      	ldr	r3, [r7, #12]
 800527a:	681b      	ldr	r3, [r3, #0]
 800527c:	2220      	movs	r2, #32
 800527e:	61da      	str	r2, [r3, #28]
    }

    error_code |= HAL_I2C_ERROR_AF;
 8005280:	6a3b      	ldr	r3, [r7, #32]
 8005282:	f043 0304 	orr.w	r3, r3, #4
 8005286:	623b      	str	r3, [r7, #32]

    status = HAL_ERROR;
 8005288:	2301      	movs	r3, #1
 800528a:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27
  }

  /* Refresh Content of Status register */
  itflag = hi2c->Instance->ISR;
 800528e:	68fb      	ldr	r3, [r7, #12]
 8005290:	681b      	ldr	r3, [r3, #0]
 8005292:	699b      	ldr	r3, [r3, #24]
 8005294:	61bb      	str	r3, [r7, #24]

  /* Then verify if an additional errors occurs */
  /* Check if a Bus error occurred */
  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
 8005296:	69bb      	ldr	r3, [r7, #24]
 8005298:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 800529c:	2b00      	cmp	r3, #0
 800529e:	d00b      	beq.n	80052b8 <I2C_IsErrorOccurred+0x128>
  {
    error_code |= HAL_I2C_ERROR_BERR;
 80052a0:	6a3b      	ldr	r3, [r7, #32]
 80052a2:	f043 0301 	orr.w	r3, r3, #1
 80052a6:	623b      	str	r3, [r7, #32]

    /* Clear BERR flag */
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
 80052a8:	68fb      	ldr	r3, [r7, #12]
 80052aa:	681b      	ldr	r3, [r3, #0]
 80052ac:	f44f 7280 	mov.w	r2, #256	@ 0x100
 80052b0:	61da      	str	r2, [r3, #28]

    status = HAL_ERROR;
 80052b2:	2301      	movs	r3, #1
 80052b4:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27
  }

  /* Check if an Over-Run/Under-Run error occurred */
  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
 80052b8:	69bb      	ldr	r3, [r7, #24]
 80052ba:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 80052be:	2b00      	cmp	r3, #0
 80052c0:	d00b      	beq.n	80052da <I2C_IsErrorOccurred+0x14a>
  {
    error_code |= HAL_I2C_ERROR_OVR;
 80052c2:	6a3b      	ldr	r3, [r7, #32]
 80052c4:	f043 0308 	orr.w	r3, r3, #8
 80052c8:	623b      	str	r3, [r7, #32]

    /* Clear OVR flag */
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
 80052ca:	68fb      	ldr	r3, [r7, #12]
 80052cc:	681b      	ldr	r3, [r3, #0]
 80052ce:	f44f 6280 	mov.w	r2, #1024	@ 0x400
 80052d2:	61da      	str	r2, [r3, #28]

    status = HAL_ERROR;
 80052d4:	2301      	movs	r3, #1
 80052d6:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27
  }

  /* Check if an Arbitration Loss error occurred */
  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
 80052da:	69bb      	ldr	r3, [r7, #24]
 80052dc:	f403 7300 	and.w	r3, r3, #512	@ 0x200
 80052e0:	2b00      	cmp	r3, #0
 80052e2:	d00b      	beq.n	80052fc <I2C_IsErrorOccurred+0x16c>
  {
    error_code |= HAL_I2C_ERROR_ARLO;
 80052e4:	6a3b      	ldr	r3, [r7, #32]
 80052e6:	f043 0302 	orr.w	r3, r3, #2
 80052ea:	623b      	str	r3, [r7, #32]

    /* Clear ARLO flag */
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
 80052ec:	68fb      	ldr	r3, [r7, #12]
 80052ee:	681b      	ldr	r3, [r3, #0]
 80052f0:	f44f 7200 	mov.w	r2, #512	@ 0x200
 80052f4:	61da      	str	r2, [r3, #28]

    status = HAL_ERROR;
 80052f6:	2301      	movs	r3, #1
 80052f8:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27
  }

  if (status != HAL_OK)
 80052fc:	f897 3027 	ldrb.w	r3, [r7, #39]	@ 0x27
 8005300:	2b00      	cmp	r3, #0
 8005302:	d01c      	beq.n	800533e <I2C_IsErrorOccurred+0x1ae>
  {
    /* Flush TX register */
    I2C_Flush_TXDR(hi2c);
 8005304:	68f8      	ldr	r0, [r7, #12]
 8005306:	f7ff fe3b 	bl	8004f80 <I2C_Flush_TXDR>

    /* Clear Configuration Register 2 */
    I2C_RESET_CR2(hi2c);
 800530a:	68fb      	ldr	r3, [r7, #12]
 800530c:	681b      	ldr	r3, [r3, #0]
 800530e:	6859      	ldr	r1, [r3, #4]
 8005310:	68fb      	ldr	r3, [r7, #12]
 8005312:	681a      	ldr	r2, [r3, #0]
 8005314:	4b0d      	ldr	r3, [pc, #52]	@ (800534c <I2C_IsErrorOccurred+0x1bc>)
 8005316:	400b      	ands	r3, r1
 8005318:	6053      	str	r3, [r2, #4]

    hi2c->ErrorCode |= error_code;
 800531a:	68fb      	ldr	r3, [r7, #12]
 800531c:	6c5a      	ldr	r2, [r3, #68]	@ 0x44
 800531e:	6a3b      	ldr	r3, [r7, #32]
 8005320:	431a      	orrs	r2, r3
 8005322:	68fb      	ldr	r3, [r7, #12]
 8005324:	645a      	str	r2, [r3, #68]	@ 0x44
    hi2c->State = HAL_I2C_STATE_READY;
 8005326:	68fb      	ldr	r3, [r7, #12]
 8005328:	2220      	movs	r2, #32
 800532a:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
    hi2c->Mode = HAL_I2C_MODE_NONE;
 800532e:	68fb      	ldr	r3, [r7, #12]
 8005330:	2200      	movs	r2, #0
 8005332:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);
 8005336:	68fb      	ldr	r3, [r7, #12]
 8005338:	2200      	movs	r2, #0
 800533a:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
  }

  return status;
 800533e:	f897 3027 	ldrb.w	r3, [r7, #39]	@ 0x27
}
 8005342:	4618      	mov	r0, r3
 8005344:	3728      	adds	r7, #40	@ 0x28
 8005346:	46bd      	mov	sp, r7
 8005348:	bd80      	pop	{r7, pc}
 800534a:	bf00      	nop
 800534c:	fe00e800 	.word	0xfe00e800

08005350 <I2C_TransferConfig>:
  *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
  * @retval None
  */
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
                               uint32_t Request)
{
 8005350:	b480      	push	{r7}
 8005352:	b087      	sub	sp, #28
 8005354:	af00      	add	r7, sp, #0
 8005356:	60f8      	str	r0, [r7, #12]
 8005358:	607b      	str	r3, [r7, #4]
 800535a:	460b      	mov	r3, r1
 800535c:	817b      	strh	r3, [r7, #10]
 800535e:	4613      	mov	r3, r2
 8005360:	727b      	strb	r3, [r7, #9]
  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
  assert_param(IS_TRANSFER_MODE(Mode));
  assert_param(IS_TRANSFER_REQUEST(Request));

  /* Declaration of tmp to prevent undefined behavior of volatile usage */
  uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
 8005362:	897b      	ldrh	r3, [r7, #10]
 8005364:	f3c3 0209 	ubfx	r2, r3, #0, #10
                             (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
 8005368:	7a7b      	ldrb	r3, [r7, #9]
 800536a:	041b      	lsls	r3, r3, #16
 800536c:	f403 037f 	and.w	r3, r3, #16711680	@ 0xff0000
  uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
 8005370:	431a      	orrs	r2, r3
                             (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
 8005372:	687b      	ldr	r3, [r7, #4]
 8005374:	431a      	orrs	r2, r3
  uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
 8005376:	6a3b      	ldr	r3, [r7, #32]
 8005378:	4313      	orrs	r3, r2
 800537a:	f023 4300 	bic.w	r3, r3, #2147483648	@ 0x80000000
 800537e:	617b      	str	r3, [r7, #20]
                             (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));

  /* update CR2 register */
  MODIFY_REG(hi2c->Instance->CR2, \
 8005380:	68fb      	ldr	r3, [r7, #12]
 8005382:	681b      	ldr	r3, [r3, #0]
 8005384:	685a      	ldr	r2, [r3, #4]
 8005386:	6a3b      	ldr	r3, [r7, #32]
 8005388:	0d5b      	lsrs	r3, r3, #21
 800538a:	f403 6180 	and.w	r1, r3, #1024	@ 0x400
 800538e:	4b08      	ldr	r3, [pc, #32]	@ (80053b0 <I2C_TransferConfig+0x60>)
 8005390:	430b      	orrs	r3, r1
 8005392:	43db      	mvns	r3, r3
 8005394:	ea02 0103 	and.w	r1, r2, r3
 8005398:	68fb      	ldr	r3, [r7, #12]
 800539a:	681b      	ldr	r3, [r3, #0]
 800539c:	697a      	ldr	r2, [r7, #20]
 800539e:	430a      	orrs	r2, r1
 80053a0:	605a      	str	r2, [r3, #4]
             ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
               (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
               I2C_CR2_START | I2C_CR2_STOP)), tmp);
}
 80053a2:	bf00      	nop
 80053a4:	371c      	adds	r7, #28
 80053a6:	46bd      	mov	sp, r7
 80053a8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80053ac:	4770      	bx	lr
 80053ae:	bf00      	nop
 80053b0:	03ff63ff 	.word	0x03ff63ff

080053b4 <HAL_I2CEx_ConfigAnalogFilter>:
  *                the configuration information for the specified I2Cx peripheral.
  * @param  AnalogFilter New state of the Analog filter.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
 80053b4:	b480      	push	{r7}
 80053b6:	b083      	sub	sp, #12
 80053b8:	af00      	add	r7, sp, #0
 80053ba:	6078      	str	r0, [r7, #4]
 80053bc:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));

  if (hi2c->State == HAL_I2C_STATE_READY)
 80053be:	687b      	ldr	r3, [r7, #4]
 80053c0:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
 80053c4:	b2db      	uxtb	r3, r3
 80053c6:	2b20      	cmp	r3, #32
 80053c8:	d138      	bne.n	800543c <HAL_I2CEx_ConfigAnalogFilter+0x88>
  {
    /* Process Locked */
    __HAL_LOCK(hi2c);
 80053ca:	687b      	ldr	r3, [r7, #4]
 80053cc:	f893 3040 	ldrb.w	r3, [r3, #64]	@ 0x40
 80053d0:	2b01      	cmp	r3, #1
 80053d2:	d101      	bne.n	80053d8 <HAL_I2CEx_ConfigAnalogFilter+0x24>
 80053d4:	2302      	movs	r3, #2
 80053d6:	e032      	b.n	800543e <HAL_I2CEx_ConfigAnalogFilter+0x8a>
 80053d8:	687b      	ldr	r3, [r7, #4]
 80053da:	2201      	movs	r2, #1
 80053dc:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    hi2c->State = HAL_I2C_STATE_BUSY;
 80053e0:	687b      	ldr	r3, [r7, #4]
 80053e2:	2224      	movs	r2, #36	@ 0x24
 80053e4:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41

    /* Disable the selected I2C peripheral */
    __HAL_I2C_DISABLE(hi2c);
 80053e8:	687b      	ldr	r3, [r7, #4]
 80053ea:	681b      	ldr	r3, [r3, #0]
 80053ec:	681a      	ldr	r2, [r3, #0]
 80053ee:	687b      	ldr	r3, [r7, #4]
 80053f0:	681b      	ldr	r3, [r3, #0]
 80053f2:	f022 0201 	bic.w	r2, r2, #1
 80053f6:	601a      	str	r2, [r3, #0]

    /* Reset I2Cx ANOFF bit */
    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
 80053f8:	687b      	ldr	r3, [r7, #4]
 80053fa:	681b      	ldr	r3, [r3, #0]
 80053fc:	681a      	ldr	r2, [r3, #0]
 80053fe:	687b      	ldr	r3, [r7, #4]
 8005400:	681b      	ldr	r3, [r3, #0]
 8005402:	f422 5280 	bic.w	r2, r2, #4096	@ 0x1000
 8005406:	601a      	str	r2, [r3, #0]

    /* Set analog filter bit*/
    hi2c->Instance->CR1 |= AnalogFilter;
 8005408:	687b      	ldr	r3, [r7, #4]
 800540a:	681b      	ldr	r3, [r3, #0]
 800540c:	6819      	ldr	r1, [r3, #0]
 800540e:	687b      	ldr	r3, [r7, #4]
 8005410:	681b      	ldr	r3, [r3, #0]
 8005412:	683a      	ldr	r2, [r7, #0]
 8005414:	430a      	orrs	r2, r1
 8005416:	601a      	str	r2, [r3, #0]

    __HAL_I2C_ENABLE(hi2c);
 8005418:	687b      	ldr	r3, [r7, #4]
 800541a:	681b      	ldr	r3, [r3, #0]
 800541c:	681a      	ldr	r2, [r3, #0]
 800541e:	687b      	ldr	r3, [r7, #4]
 8005420:	681b      	ldr	r3, [r3, #0]
 8005422:	f042 0201 	orr.w	r2, r2, #1
 8005426:	601a      	str	r2, [r3, #0]

    hi2c->State = HAL_I2C_STATE_READY;
 8005428:	687b      	ldr	r3, [r7, #4]
 800542a:	2220      	movs	r2, #32
 800542c:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);
 8005430:	687b      	ldr	r3, [r7, #4]
 8005432:	2200      	movs	r2, #0
 8005434:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    return HAL_OK;
 8005438:	2300      	movs	r3, #0
 800543a:	e000      	b.n	800543e <HAL_I2CEx_ConfigAnalogFilter+0x8a>
  }
  else
  {
    return HAL_BUSY;
 800543c:	2302      	movs	r3, #2
  }
}
 800543e:	4618      	mov	r0, r3
 8005440:	370c      	adds	r7, #12
 8005442:	46bd      	mov	sp, r7
 8005444:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005448:	4770      	bx	lr

0800544a <HAL_I2CEx_ConfigDigitalFilter>:
  *                the configuration information for the specified I2Cx peripheral.
  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
 800544a:	b480      	push	{r7}
 800544c:	b085      	sub	sp, #20
 800544e:	af00      	add	r7, sp, #0
 8005450:	6078      	str	r0, [r7, #4]
 8005452:	6039      	str	r1, [r7, #0]

  /* Check the parameters */
  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));

  if (hi2c->State == HAL_I2C_STATE_READY)
 8005454:	687b      	ldr	r3, [r7, #4]
 8005456:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
 800545a:	b2db      	uxtb	r3, r3
 800545c:	2b20      	cmp	r3, #32
 800545e:	d139      	bne.n	80054d4 <HAL_I2CEx_ConfigDigitalFilter+0x8a>
  {
    /* Process Locked */
    __HAL_LOCK(hi2c);
 8005460:	687b      	ldr	r3, [r7, #4]
 8005462:	f893 3040 	ldrb.w	r3, [r3, #64]	@ 0x40
 8005466:	2b01      	cmp	r3, #1
 8005468:	d101      	bne.n	800546e <HAL_I2CEx_ConfigDigitalFilter+0x24>
 800546a:	2302      	movs	r3, #2
 800546c:	e033      	b.n	80054d6 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
 800546e:	687b      	ldr	r3, [r7, #4]
 8005470:	2201      	movs	r2, #1
 8005472:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    hi2c->State = HAL_I2C_STATE_BUSY;
 8005476:	687b      	ldr	r3, [r7, #4]
 8005478:	2224      	movs	r2, #36	@ 0x24
 800547a:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41

    /* Disable the selected I2C peripheral */
    __HAL_I2C_DISABLE(hi2c);
 800547e:	687b      	ldr	r3, [r7, #4]
 8005480:	681b      	ldr	r3, [r3, #0]
 8005482:	681a      	ldr	r2, [r3, #0]
 8005484:	687b      	ldr	r3, [r7, #4]
 8005486:	681b      	ldr	r3, [r3, #0]
 8005488:	f022 0201 	bic.w	r2, r2, #1
 800548c:	601a      	str	r2, [r3, #0]

    /* Get the old register value */
    tmpreg = hi2c->Instance->CR1;
 800548e:	687b      	ldr	r3, [r7, #4]
 8005490:	681b      	ldr	r3, [r3, #0]
 8005492:	681b      	ldr	r3, [r3, #0]
 8005494:	60fb      	str	r3, [r7, #12]

    /* Reset I2Cx DNF bits [11:8] */
    tmpreg &= ~(I2C_CR1_DNF);
 8005496:	68fb      	ldr	r3, [r7, #12]
 8005498:	f423 6370 	bic.w	r3, r3, #3840	@ 0xf00
 800549c:	60fb      	str	r3, [r7, #12]

    /* Set I2Cx DNF coefficient */
    tmpreg |= DigitalFilter << 8U;
 800549e:	683b      	ldr	r3, [r7, #0]
 80054a0:	021b      	lsls	r3, r3, #8
 80054a2:	68fa      	ldr	r2, [r7, #12]
 80054a4:	4313      	orrs	r3, r2
 80054a6:	60fb      	str	r3, [r7, #12]

    /* Store the new register value */
    hi2c->Instance->CR1 = tmpreg;
 80054a8:	687b      	ldr	r3, [r7, #4]
 80054aa:	681b      	ldr	r3, [r3, #0]
 80054ac:	68fa      	ldr	r2, [r7, #12]
 80054ae:	601a      	str	r2, [r3, #0]

    __HAL_I2C_ENABLE(hi2c);
 80054b0:	687b      	ldr	r3, [r7, #4]
 80054b2:	681b      	ldr	r3, [r3, #0]
 80054b4:	681a      	ldr	r2, [r3, #0]
 80054b6:	687b      	ldr	r3, [r7, #4]
 80054b8:	681b      	ldr	r3, [r3, #0]
 80054ba:	f042 0201 	orr.w	r2, r2, #1
 80054be:	601a      	str	r2, [r3, #0]

    hi2c->State = HAL_I2C_STATE_READY;
 80054c0:	687b      	ldr	r3, [r7, #4]
 80054c2:	2220      	movs	r2, #32
 80054c4:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);
 80054c8:	687b      	ldr	r3, [r7, #4]
 80054ca:	2200      	movs	r2, #0
 80054cc:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40

    return HAL_OK;
 80054d0:	2300      	movs	r3, #0
 80054d2:	e000      	b.n	80054d6 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
  }
  else
  {
    return HAL_BUSY;
 80054d4:	2302      	movs	r3, #2
  }
}
 80054d6:	4618      	mov	r0, r3
 80054d8:	3714      	adds	r7, #20
 80054da:	46bd      	mov	sp, r7
 80054dc:	f85d 7b04 	ldr.w	r7, [sp], #4
 80054e0:	4770      	bx	lr
	...

080054e4 <HAL_PWREx_GetVoltageRange>:
  * @brief Return Voltage Scaling Range.
  * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
  *         or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
  */
uint32_t HAL_PWREx_GetVoltageRange(void)
{
 80054e4:	b480      	push	{r7}
 80054e6:	af00      	add	r7, sp, #0
    else
    {
      return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
    }
#else
  return  (PWR->CR1 & PWR_CR1_VOS);
 80054e8:	4b04      	ldr	r3, [pc, #16]	@ (80054fc <HAL_PWREx_GetVoltageRange+0x18>)
 80054ea:	681b      	ldr	r3, [r3, #0]
 80054ec:	f403 63c0 	and.w	r3, r3, #1536	@ 0x600
#endif
}
 80054f0:	4618      	mov	r0, r3
 80054f2:	46bd      	mov	sp, r7
 80054f4:	f85d 7b04 	ldr.w	r7, [sp], #4
 80054f8:	4770      	bx	lr
 80054fa:	bf00      	nop
 80054fc:	40007000 	.word	0x40007000

08005500 <HAL_PWREx_ControlVoltageScaling>:
  *        cleared before returning the status. If the flag is not cleared within
  *        50 microseconds, HAL_TIMEOUT status is reported.
  * @retval HAL Status
  */
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
 8005500:	b480      	push	{r7}
 8005502:	b085      	sub	sp, #20
 8005504:	af00      	add	r7, sp, #0
 8005506:	6078      	str	r0, [r7, #4]
  }

#else

  /* If Set Range 1 */
  if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
 8005508:	687b      	ldr	r3, [r7, #4]
 800550a:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 800550e:	d130      	bne.n	8005572 <HAL_PWREx_ControlVoltageScaling+0x72>
  {
    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
 8005510:	4b23      	ldr	r3, [pc, #140]	@ (80055a0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 8005512:	681b      	ldr	r3, [r3, #0]
 8005514:	f403 63c0 	and.w	r3, r3, #1536	@ 0x600
 8005518:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 800551c:	d038      	beq.n	8005590 <HAL_PWREx_ControlVoltageScaling+0x90>
    {
      /* Set Range 1 */
      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
 800551e:	4b20      	ldr	r3, [pc, #128]	@ (80055a0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 8005520:	681b      	ldr	r3, [r3, #0]
 8005522:	f423 63c0 	bic.w	r3, r3, #1536	@ 0x600
 8005526:	4a1e      	ldr	r2, [pc, #120]	@ (80055a0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 8005528:	f443 7300 	orr.w	r3, r3, #512	@ 0x200
 800552c:	6013      	str	r3, [r2, #0]

      /* Wait until VOSF is cleared */
      wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
 800552e:	4b1d      	ldr	r3, [pc, #116]	@ (80055a4 <HAL_PWREx_ControlVoltageScaling+0xa4>)
 8005530:	681b      	ldr	r3, [r3, #0]
 8005532:	2232      	movs	r2, #50	@ 0x32
 8005534:	fb02 f303 	mul.w	r3, r2, r3
 8005538:	4a1b      	ldr	r2, [pc, #108]	@ (80055a8 <HAL_PWREx_ControlVoltageScaling+0xa8>)
 800553a:	fba2 2303 	umull	r2, r3, r2, r3
 800553e:	0c9b      	lsrs	r3, r3, #18
 8005540:	3301      	adds	r3, #1
 8005542:	60fb      	str	r3, [r7, #12]
      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
 8005544:	e002      	b.n	800554c <HAL_PWREx_ControlVoltageScaling+0x4c>
      {
        wait_loop_index--;
 8005546:	68fb      	ldr	r3, [r7, #12]
 8005548:	3b01      	subs	r3, #1
 800554a:	60fb      	str	r3, [r7, #12]
      while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
 800554c:	4b14      	ldr	r3, [pc, #80]	@ (80055a0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 800554e:	695b      	ldr	r3, [r3, #20]
 8005550:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 8005554:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
 8005558:	d102      	bne.n	8005560 <HAL_PWREx_ControlVoltageScaling+0x60>
 800555a:	68fb      	ldr	r3, [r7, #12]
 800555c:	2b00      	cmp	r3, #0
 800555e:	d1f2      	bne.n	8005546 <HAL_PWREx_ControlVoltageScaling+0x46>
      }
      if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
 8005560:	4b0f      	ldr	r3, [pc, #60]	@ (80055a0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 8005562:	695b      	ldr	r3, [r3, #20]
 8005564:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 8005568:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
 800556c:	d110      	bne.n	8005590 <HAL_PWREx_ControlVoltageScaling+0x90>
      {
        return HAL_TIMEOUT;
 800556e:	2303      	movs	r3, #3
 8005570:	e00f      	b.n	8005592 <HAL_PWREx_ControlVoltageScaling+0x92>
      }
    }
  }
  else
  {
    if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
 8005572:	4b0b      	ldr	r3, [pc, #44]	@ (80055a0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 8005574:	681b      	ldr	r3, [r3, #0]
 8005576:	f403 63c0 	and.w	r3, r3, #1536	@ 0x600
 800557a:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
 800557e:	d007      	beq.n	8005590 <HAL_PWREx_ControlVoltageScaling+0x90>
    {
      /* Set Range 2 */
      MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
 8005580:	4b07      	ldr	r3, [pc, #28]	@ (80055a0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 8005582:	681b      	ldr	r3, [r3, #0]
 8005584:	f423 63c0 	bic.w	r3, r3, #1536	@ 0x600
 8005588:	4a05      	ldr	r2, [pc, #20]	@ (80055a0 <HAL_PWREx_ControlVoltageScaling+0xa0>)
 800558a:	f443 6380 	orr.w	r3, r3, #1024	@ 0x400
 800558e:	6013      	str	r3, [r2, #0]
      /* No need to wait for VOSF to be cleared for this transition */
    }
  }
#endif

  return HAL_OK;
 8005590:	2300      	movs	r3, #0
}
 8005592:	4618      	mov	r0, r3
 8005594:	3714      	adds	r7, #20
 8005596:	46bd      	mov	sp, r7
 8005598:	f85d 7b04 	ldr.w	r7, [sp], #4
 800559c:	4770      	bx	lr
 800559e:	bf00      	nop
 80055a0:	40007000 	.word	0x40007000
 80055a4:	20000000 	.word	0x20000000
 80055a8:	431bde83 	.word	0x431bde83

080055ac <HAL_RCC_OscConfig>:
  * @note   If HSE failed to start, HSE should be disabled before recalling
            HAL_RCC_OscConfig().
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 80055ac:	b580      	push	{r7, lr}
 80055ae:	b088      	sub	sp, #32
 80055b0:	af00      	add	r7, sp, #0
 80055b2:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;
  HAL_StatusTypeDef status;
  uint32_t sysclk_source, pll_config;

  /* Check Null pointer */
  if(RCC_OscInitStruct == NULL)
 80055b4:	687b      	ldr	r3, [r7, #4]
 80055b6:	2b00      	cmp	r3, #0
 80055b8:	d102      	bne.n	80055c0 <HAL_RCC_OscConfig+0x14>
  {
    return HAL_ERROR;
 80055ba:	2301      	movs	r3, #1
 80055bc:	f000 bc02 	b.w	8005dc4 <HAL_RCC_OscConfig+0x818>
  }

  /* Check the parameters */
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));

  sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
 80055c0:	4b96      	ldr	r3, [pc, #600]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 80055c2:	689b      	ldr	r3, [r3, #8]
 80055c4:	f003 030c 	and.w	r3, r3, #12
 80055c8:	61bb      	str	r3, [r7, #24]
  pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
 80055ca:	4b94      	ldr	r3, [pc, #592]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 80055cc:	68db      	ldr	r3, [r3, #12]
 80055ce:	f003 0303 	and.w	r3, r3, #3
 80055d2:	617b      	str	r3, [r7, #20]

  /*----------------------------- MSI Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
 80055d4:	687b      	ldr	r3, [r7, #4]
 80055d6:	681b      	ldr	r3, [r3, #0]
 80055d8:	f003 0310 	and.w	r3, r3, #16
 80055dc:	2b00      	cmp	r3, #0
 80055de:	f000 80e4 	beq.w	80057aa <HAL_RCC_OscConfig+0x1fe>
    assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
    assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
    assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));

    /* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
    if((sysclk_source == RCC_CFGR_SWS_MSI) ||
 80055e2:	69bb      	ldr	r3, [r7, #24]
 80055e4:	2b00      	cmp	r3, #0
 80055e6:	d007      	beq.n	80055f8 <HAL_RCC_OscConfig+0x4c>
 80055e8:	69bb      	ldr	r3, [r7, #24]
 80055ea:	2b0c      	cmp	r3, #12
 80055ec:	f040 808b 	bne.w	8005706 <HAL_RCC_OscConfig+0x15a>
       ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))
 80055f0:	697b      	ldr	r3, [r7, #20]
 80055f2:	2b01      	cmp	r3, #1
 80055f4:	f040 8087 	bne.w	8005706 <HAL_RCC_OscConfig+0x15a>
    {
      if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
 80055f8:	4b88      	ldr	r3, [pc, #544]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 80055fa:	681b      	ldr	r3, [r3, #0]
 80055fc:	f003 0302 	and.w	r3, r3, #2
 8005600:	2b00      	cmp	r3, #0
 8005602:	d005      	beq.n	8005610 <HAL_RCC_OscConfig+0x64>
 8005604:	687b      	ldr	r3, [r7, #4]
 8005606:	699b      	ldr	r3, [r3, #24]
 8005608:	2b00      	cmp	r3, #0
 800560a:	d101      	bne.n	8005610 <HAL_RCC_OscConfig+0x64>
      {
        return HAL_ERROR;
 800560c:	2301      	movs	r3, #1
 800560e:	e3d9      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
      else
      {
        /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
           must be correctly programmed according to the frequency of the CPU clock
           (HCLK) and the supply voltage of the device. */
        if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
 8005610:	687b      	ldr	r3, [r7, #4]
 8005612:	6a1a      	ldr	r2, [r3, #32]
 8005614:	4b81      	ldr	r3, [pc, #516]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 8005616:	681b      	ldr	r3, [r3, #0]
 8005618:	f003 0308 	and.w	r3, r3, #8
 800561c:	2b00      	cmp	r3, #0
 800561e:	d004      	beq.n	800562a <HAL_RCC_OscConfig+0x7e>
 8005620:	4b7e      	ldr	r3, [pc, #504]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 8005622:	681b      	ldr	r3, [r3, #0]
 8005624:	f003 03f0 	and.w	r3, r3, #240	@ 0xf0
 8005628:	e005      	b.n	8005636 <HAL_RCC_OscConfig+0x8a>
 800562a:	4b7c      	ldr	r3, [pc, #496]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 800562c:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 8005630:	091b      	lsrs	r3, r3, #4
 8005632:	f003 03f0 	and.w	r3, r3, #240	@ 0xf0
 8005636:	4293      	cmp	r3, r2
 8005638:	d223      	bcs.n	8005682 <HAL_RCC_OscConfig+0xd6>
        {
          /* First increase number of wait states update if necessary */
          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
 800563a:	687b      	ldr	r3, [r7, #4]
 800563c:	6a1b      	ldr	r3, [r3, #32]
 800563e:	4618      	mov	r0, r3
 8005640:	f000 fd8c 	bl	800615c <RCC_SetFlashLatencyFromMSIRange>
 8005644:	4603      	mov	r3, r0
 8005646:	2b00      	cmp	r3, #0
 8005648:	d001      	beq.n	800564e <HAL_RCC_OscConfig+0xa2>
          {
            return HAL_ERROR;
 800564a:	2301      	movs	r3, #1
 800564c:	e3ba      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
          }

          /* Selects the Multiple Speed oscillator (MSI) clock range .*/
          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 800564e:	4b73      	ldr	r3, [pc, #460]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 8005650:	681b      	ldr	r3, [r3, #0]
 8005652:	4a72      	ldr	r2, [pc, #456]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 8005654:	f043 0308 	orr.w	r3, r3, #8
 8005658:	6013      	str	r3, [r2, #0]
 800565a:	4b70      	ldr	r3, [pc, #448]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 800565c:	681b      	ldr	r3, [r3, #0]
 800565e:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
 8005662:	687b      	ldr	r3, [r7, #4]
 8005664:	6a1b      	ldr	r3, [r3, #32]
 8005666:	496d      	ldr	r1, [pc, #436]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 8005668:	4313      	orrs	r3, r2
 800566a:	600b      	str	r3, [r1, #0]
          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 800566c:	4b6b      	ldr	r3, [pc, #428]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 800566e:	685b      	ldr	r3, [r3, #4]
 8005670:	f423 427f 	bic.w	r2, r3, #65280	@ 0xff00
 8005674:	687b      	ldr	r3, [r7, #4]
 8005676:	69db      	ldr	r3, [r3, #28]
 8005678:	021b      	lsls	r3, r3, #8
 800567a:	4968      	ldr	r1, [pc, #416]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 800567c:	4313      	orrs	r3, r2
 800567e:	604b      	str	r3, [r1, #4]
 8005680:	e025      	b.n	80056ce <HAL_RCC_OscConfig+0x122>
        }
        else
        {
          /* Else, keep current flash latency while decreasing applies */
          /* Selects the Multiple Speed oscillator (MSI) clock range .*/
          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 8005682:	4b66      	ldr	r3, [pc, #408]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 8005684:	681b      	ldr	r3, [r3, #0]
 8005686:	4a65      	ldr	r2, [pc, #404]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 8005688:	f043 0308 	orr.w	r3, r3, #8
 800568c:	6013      	str	r3, [r2, #0]
 800568e:	4b63      	ldr	r3, [pc, #396]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 8005690:	681b      	ldr	r3, [r3, #0]
 8005692:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
 8005696:	687b      	ldr	r3, [r7, #4]
 8005698:	6a1b      	ldr	r3, [r3, #32]
 800569a:	4960      	ldr	r1, [pc, #384]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 800569c:	4313      	orrs	r3, r2
 800569e:	600b      	str	r3, [r1, #0]
          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 80056a0:	4b5e      	ldr	r3, [pc, #376]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 80056a2:	685b      	ldr	r3, [r3, #4]
 80056a4:	f423 427f 	bic.w	r2, r3, #65280	@ 0xff00
 80056a8:	687b      	ldr	r3, [r7, #4]
 80056aa:	69db      	ldr	r3, [r3, #28]
 80056ac:	021b      	lsls	r3, r3, #8
 80056ae:	495b      	ldr	r1, [pc, #364]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 80056b0:	4313      	orrs	r3, r2
 80056b2:	604b      	str	r3, [r1, #4]

          /* Decrease number of wait states update if necessary */
          /* Only possible when MSI is the System clock source  */
          if(sysclk_source == RCC_CFGR_SWS_MSI)
 80056b4:	69bb      	ldr	r3, [r7, #24]
 80056b6:	2b00      	cmp	r3, #0
 80056b8:	d109      	bne.n	80056ce <HAL_RCC_OscConfig+0x122>
          {
            if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
 80056ba:	687b      	ldr	r3, [r7, #4]
 80056bc:	6a1b      	ldr	r3, [r3, #32]
 80056be:	4618      	mov	r0, r3
 80056c0:	f000 fd4c 	bl	800615c <RCC_SetFlashLatencyFromMSIRange>
 80056c4:	4603      	mov	r3, r0
 80056c6:	2b00      	cmp	r3, #0
 80056c8:	d001      	beq.n	80056ce <HAL_RCC_OscConfig+0x122>
            {
              return HAL_ERROR;
 80056ca:	2301      	movs	r3, #1
 80056cc:	e37a      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
            }
          }
        }

        /* Update the SystemCoreClock global variable */
        SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
 80056ce:	f000 fc81 	bl	8005fd4 <HAL_RCC_GetSysClockFreq>
 80056d2:	4602      	mov	r2, r0
 80056d4:	4b51      	ldr	r3, [pc, #324]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 80056d6:	689b      	ldr	r3, [r3, #8]
 80056d8:	091b      	lsrs	r3, r3, #4
 80056da:	f003 030f 	and.w	r3, r3, #15
 80056de:	4950      	ldr	r1, [pc, #320]	@ (8005820 <HAL_RCC_OscConfig+0x274>)
 80056e0:	5ccb      	ldrb	r3, [r1, r3]
 80056e2:	f003 031f 	and.w	r3, r3, #31
 80056e6:	fa22 f303 	lsr.w	r3, r2, r3
 80056ea:	4a4e      	ldr	r2, [pc, #312]	@ (8005824 <HAL_RCC_OscConfig+0x278>)
 80056ec:	6013      	str	r3, [r2, #0]

        /* Configure the source of time base considering new system clocks settings*/
        status = HAL_InitTick(uwTickPrio);
 80056ee:	4b4e      	ldr	r3, [pc, #312]	@ (8005828 <HAL_RCC_OscConfig+0x27c>)
 80056f0:	681b      	ldr	r3, [r3, #0]
 80056f2:	4618      	mov	r0, r3
 80056f4:	f7fe fcc2 	bl	800407c <HAL_InitTick>
 80056f8:	4603      	mov	r3, r0
 80056fa:	73fb      	strb	r3, [r7, #15]
        if(status != HAL_OK)
 80056fc:	7bfb      	ldrb	r3, [r7, #15]
 80056fe:	2b00      	cmp	r3, #0
 8005700:	d052      	beq.n	80057a8 <HAL_RCC_OscConfig+0x1fc>
        {
          return status;
 8005702:	7bfb      	ldrb	r3, [r7, #15]
 8005704:	e35e      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
      }
    }
    else
    {
      /* Check the MSI State */
      if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
 8005706:	687b      	ldr	r3, [r7, #4]
 8005708:	699b      	ldr	r3, [r3, #24]
 800570a:	2b00      	cmp	r3, #0
 800570c:	d032      	beq.n	8005774 <HAL_RCC_OscConfig+0x1c8>
      {
        /* Enable the Internal High Speed oscillator (MSI). */
        __HAL_RCC_MSI_ENABLE();
 800570e:	4b43      	ldr	r3, [pc, #268]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 8005710:	681b      	ldr	r3, [r3, #0]
 8005712:	4a42      	ldr	r2, [pc, #264]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 8005714:	f043 0301 	orr.w	r3, r3, #1
 8005718:	6013      	str	r3, [r2, #0]

        /* Get timeout */
        tickstart = HAL_GetTick();
 800571a:	f7fe fcff 	bl	800411c <HAL_GetTick>
 800571e:	6138      	str	r0, [r7, #16]

        /* Wait till MSI is ready */
        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
 8005720:	e008      	b.n	8005734 <HAL_RCC_OscConfig+0x188>
        {
          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
 8005722:	f7fe fcfb 	bl	800411c <HAL_GetTick>
 8005726:	4602      	mov	r2, r0
 8005728:	693b      	ldr	r3, [r7, #16]
 800572a:	1ad3      	subs	r3, r2, r3
 800572c:	2b02      	cmp	r3, #2
 800572e:	d901      	bls.n	8005734 <HAL_RCC_OscConfig+0x188>
          {
            return HAL_TIMEOUT;
 8005730:	2303      	movs	r3, #3
 8005732:	e347      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
 8005734:	4b39      	ldr	r3, [pc, #228]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 8005736:	681b      	ldr	r3, [r3, #0]
 8005738:	f003 0302 	and.w	r3, r3, #2
 800573c:	2b00      	cmp	r3, #0
 800573e:	d0f0      	beq.n	8005722 <HAL_RCC_OscConfig+0x176>
          }
        }
         /* Selects the Multiple Speed oscillator (MSI) clock range .*/
        __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 8005740:	4b36      	ldr	r3, [pc, #216]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 8005742:	681b      	ldr	r3, [r3, #0]
 8005744:	4a35      	ldr	r2, [pc, #212]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 8005746:	f043 0308 	orr.w	r3, r3, #8
 800574a:	6013      	str	r3, [r2, #0]
 800574c:	4b33      	ldr	r3, [pc, #204]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 800574e:	681b      	ldr	r3, [r3, #0]
 8005750:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
 8005754:	687b      	ldr	r3, [r7, #4]
 8005756:	6a1b      	ldr	r3, [r3, #32]
 8005758:	4930      	ldr	r1, [pc, #192]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 800575a:	4313      	orrs	r3, r2
 800575c:	600b      	str	r3, [r1, #0]
         /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 800575e:	4b2f      	ldr	r3, [pc, #188]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 8005760:	685b      	ldr	r3, [r3, #4]
 8005762:	f423 427f 	bic.w	r2, r3, #65280	@ 0xff00
 8005766:	687b      	ldr	r3, [r7, #4]
 8005768:	69db      	ldr	r3, [r3, #28]
 800576a:	021b      	lsls	r3, r3, #8
 800576c:	492b      	ldr	r1, [pc, #172]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 800576e:	4313      	orrs	r3, r2
 8005770:	604b      	str	r3, [r1, #4]
 8005772:	e01a      	b.n	80057aa <HAL_RCC_OscConfig+0x1fe>

      }
      else
      {
        /* Disable the Internal High Speed oscillator (MSI). */
        __HAL_RCC_MSI_DISABLE();
 8005774:	4b29      	ldr	r3, [pc, #164]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 8005776:	681b      	ldr	r3, [r3, #0]
 8005778:	4a28      	ldr	r2, [pc, #160]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 800577a:	f023 0301 	bic.w	r3, r3, #1
 800577e:	6013      	str	r3, [r2, #0]

        /* Get timeout */
        tickstart = HAL_GetTick();
 8005780:	f7fe fccc 	bl	800411c <HAL_GetTick>
 8005784:	6138      	str	r0, [r7, #16]

        /* Wait till MSI is ready */
        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
 8005786:	e008      	b.n	800579a <HAL_RCC_OscConfig+0x1ee>
        {
          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
 8005788:	f7fe fcc8 	bl	800411c <HAL_GetTick>
 800578c:	4602      	mov	r2, r0
 800578e:	693b      	ldr	r3, [r7, #16]
 8005790:	1ad3      	subs	r3, r2, r3
 8005792:	2b02      	cmp	r3, #2
 8005794:	d901      	bls.n	800579a <HAL_RCC_OscConfig+0x1ee>
          {
            return HAL_TIMEOUT;
 8005796:	2303      	movs	r3, #3
 8005798:	e314      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
        while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
 800579a:	4b20      	ldr	r3, [pc, #128]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 800579c:	681b      	ldr	r3, [r3, #0]
 800579e:	f003 0302 	and.w	r3, r3, #2
 80057a2:	2b00      	cmp	r3, #0
 80057a4:	d1f0      	bne.n	8005788 <HAL_RCC_OscConfig+0x1dc>
 80057a6:	e000      	b.n	80057aa <HAL_RCC_OscConfig+0x1fe>
      if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
 80057a8:	bf00      	nop
        }
      }
    }
  }
  /*------------------------------- HSE Configuration ------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 80057aa:	687b      	ldr	r3, [r7, #4]
 80057ac:	681b      	ldr	r3, [r3, #0]
 80057ae:	f003 0301 	and.w	r3, r3, #1
 80057b2:	2b00      	cmp	r3, #0
 80057b4:	d073      	beq.n	800589e <HAL_RCC_OscConfig+0x2f2>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));

    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
    if((sysclk_source == RCC_CFGR_SWS_HSE) ||
 80057b6:	69bb      	ldr	r3, [r7, #24]
 80057b8:	2b08      	cmp	r3, #8
 80057ba:	d005      	beq.n	80057c8 <HAL_RCC_OscConfig+0x21c>
 80057bc:	69bb      	ldr	r3, [r7, #24]
 80057be:	2b0c      	cmp	r3, #12
 80057c0:	d10e      	bne.n	80057e0 <HAL_RCC_OscConfig+0x234>
       ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))
 80057c2:	697b      	ldr	r3, [r7, #20]
 80057c4:	2b03      	cmp	r3, #3
 80057c6:	d10b      	bne.n	80057e0 <HAL_RCC_OscConfig+0x234>
    {
      if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 80057c8:	4b14      	ldr	r3, [pc, #80]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 80057ca:	681b      	ldr	r3, [r3, #0]
 80057cc:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 80057d0:	2b00      	cmp	r3, #0
 80057d2:	d063      	beq.n	800589c <HAL_RCC_OscConfig+0x2f0>
 80057d4:	687b      	ldr	r3, [r7, #4]
 80057d6:	685b      	ldr	r3, [r3, #4]
 80057d8:	2b00      	cmp	r3, #0
 80057da:	d15f      	bne.n	800589c <HAL_RCC_OscConfig+0x2f0>
      {
        return HAL_ERROR;
 80057dc:	2301      	movs	r3, #1
 80057de:	e2f1      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 80057e0:	687b      	ldr	r3, [r7, #4]
 80057e2:	685b      	ldr	r3, [r3, #4]
 80057e4:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 80057e8:	d106      	bne.n	80057f8 <HAL_RCC_OscConfig+0x24c>
 80057ea:	4b0c      	ldr	r3, [pc, #48]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 80057ec:	681b      	ldr	r3, [r3, #0]
 80057ee:	4a0b      	ldr	r2, [pc, #44]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 80057f0:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 80057f4:	6013      	str	r3, [r2, #0]
 80057f6:	e025      	b.n	8005844 <HAL_RCC_OscConfig+0x298>
 80057f8:	687b      	ldr	r3, [r7, #4]
 80057fa:	685b      	ldr	r3, [r3, #4]
 80057fc:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
 8005800:	d114      	bne.n	800582c <HAL_RCC_OscConfig+0x280>
 8005802:	4b06      	ldr	r3, [pc, #24]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 8005804:	681b      	ldr	r3, [r3, #0]
 8005806:	4a05      	ldr	r2, [pc, #20]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 8005808:	f443 2380 	orr.w	r3, r3, #262144	@ 0x40000
 800580c:	6013      	str	r3, [r2, #0]
 800580e:	4b03      	ldr	r3, [pc, #12]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 8005810:	681b      	ldr	r3, [r3, #0]
 8005812:	4a02      	ldr	r2, [pc, #8]	@ (800581c <HAL_RCC_OscConfig+0x270>)
 8005814:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 8005818:	6013      	str	r3, [r2, #0]
 800581a:	e013      	b.n	8005844 <HAL_RCC_OscConfig+0x298>
 800581c:	40021000 	.word	0x40021000
 8005820:	0800b8f4 	.word	0x0800b8f4
 8005824:	20000000 	.word	0x20000000
 8005828:	20000004 	.word	0x20000004
 800582c:	4ba0      	ldr	r3, [pc, #640]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 800582e:	681b      	ldr	r3, [r3, #0]
 8005830:	4a9f      	ldr	r2, [pc, #636]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 8005832:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 8005836:	6013      	str	r3, [r2, #0]
 8005838:	4b9d      	ldr	r3, [pc, #628]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 800583a:	681b      	ldr	r3, [r3, #0]
 800583c:	4a9c      	ldr	r2, [pc, #624]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 800583e:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
 8005842:	6013      	str	r3, [r2, #0]

      /* Check the HSE State */
      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
 8005844:	687b      	ldr	r3, [r7, #4]
 8005846:	685b      	ldr	r3, [r3, #4]
 8005848:	2b00      	cmp	r3, #0
 800584a:	d013      	beq.n	8005874 <HAL_RCC_OscConfig+0x2c8>
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 800584c:	f7fe fc66 	bl	800411c <HAL_GetTick>
 8005850:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is ready */
        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 8005852:	e008      	b.n	8005866 <HAL_RCC_OscConfig+0x2ba>
        {
          if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 8005854:	f7fe fc62 	bl	800411c <HAL_GetTick>
 8005858:	4602      	mov	r2, r0
 800585a:	693b      	ldr	r3, [r7, #16]
 800585c:	1ad3      	subs	r3, r2, r3
 800585e:	2b64      	cmp	r3, #100	@ 0x64
 8005860:	d901      	bls.n	8005866 <HAL_RCC_OscConfig+0x2ba>
          {
            return HAL_TIMEOUT;
 8005862:	2303      	movs	r3, #3
 8005864:	e2ae      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 8005866:	4b92      	ldr	r3, [pc, #584]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 8005868:	681b      	ldr	r3, [r3, #0]
 800586a:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 800586e:	2b00      	cmp	r3, #0
 8005870:	d0f0      	beq.n	8005854 <HAL_RCC_OscConfig+0x2a8>
 8005872:	e014      	b.n	800589e <HAL_RCC_OscConfig+0x2f2>
        }
      }
      else
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8005874:	f7fe fc52 	bl	800411c <HAL_GetTick>
 8005878:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is disabled */
        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
 800587a:	e008      	b.n	800588e <HAL_RCC_OscConfig+0x2e2>
        {
          if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 800587c:	f7fe fc4e 	bl	800411c <HAL_GetTick>
 8005880:	4602      	mov	r2, r0
 8005882:	693b      	ldr	r3, [r7, #16]
 8005884:	1ad3      	subs	r3, r2, r3
 8005886:	2b64      	cmp	r3, #100	@ 0x64
 8005888:	d901      	bls.n	800588e <HAL_RCC_OscConfig+0x2e2>
          {
            return HAL_TIMEOUT;
 800588a:	2303      	movs	r3, #3
 800588c:	e29a      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
        while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
 800588e:	4b88      	ldr	r3, [pc, #544]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 8005890:	681b      	ldr	r3, [r3, #0]
 8005892:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8005896:	2b00      	cmp	r3, #0
 8005898:	d1f0      	bne.n	800587c <HAL_RCC_OscConfig+0x2d0>
 800589a:	e000      	b.n	800589e <HAL_RCC_OscConfig+0x2f2>
      if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 800589c:	bf00      	nop
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 800589e:	687b      	ldr	r3, [r7, #4]
 80058a0:	681b      	ldr	r3, [r3, #0]
 80058a2:	f003 0302 	and.w	r3, r3, #2
 80058a6:	2b00      	cmp	r3, #0
 80058a8:	d060      	beq.n	800596c <HAL_RCC_OscConfig+0x3c0>
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
    if((sysclk_source == RCC_CFGR_SWS_HSI) ||
 80058aa:	69bb      	ldr	r3, [r7, #24]
 80058ac:	2b04      	cmp	r3, #4
 80058ae:	d005      	beq.n	80058bc <HAL_RCC_OscConfig+0x310>
 80058b0:	69bb      	ldr	r3, [r7, #24]
 80058b2:	2b0c      	cmp	r3, #12
 80058b4:	d119      	bne.n	80058ea <HAL_RCC_OscConfig+0x33e>
       ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))
 80058b6:	697b      	ldr	r3, [r7, #20]
 80058b8:	2b02      	cmp	r3, #2
 80058ba:	d116      	bne.n	80058ea <HAL_RCC_OscConfig+0x33e>
    {
      /* When HSI is used as system clock it will not be disabled */
      if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
 80058bc:	4b7c      	ldr	r3, [pc, #496]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 80058be:	681b      	ldr	r3, [r3, #0]
 80058c0:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 80058c4:	2b00      	cmp	r3, #0
 80058c6:	d005      	beq.n	80058d4 <HAL_RCC_OscConfig+0x328>
 80058c8:	687b      	ldr	r3, [r7, #4]
 80058ca:	68db      	ldr	r3, [r3, #12]
 80058cc:	2b00      	cmp	r3, #0
 80058ce:	d101      	bne.n	80058d4 <HAL_RCC_OscConfig+0x328>
      {
        return HAL_ERROR;
 80058d0:	2301      	movs	r3, #1
 80058d2:	e277      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
      }
      /* Otherwise, just the calibration is allowed */
      else
      {
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 80058d4:	4b76      	ldr	r3, [pc, #472]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 80058d6:	685b      	ldr	r3, [r3, #4]
 80058d8:	f023 42fe 	bic.w	r2, r3, #2130706432	@ 0x7f000000
 80058dc:	687b      	ldr	r3, [r7, #4]
 80058de:	691b      	ldr	r3, [r3, #16]
 80058e0:	061b      	lsls	r3, r3, #24
 80058e2:	4973      	ldr	r1, [pc, #460]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 80058e4:	4313      	orrs	r3, r2
 80058e6:	604b      	str	r3, [r1, #4]
      if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
 80058e8:	e040      	b.n	800596c <HAL_RCC_OscConfig+0x3c0>
      }
    }
    else
    {
      /* Check the HSI State */
      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 80058ea:	687b      	ldr	r3, [r7, #4]
 80058ec:	68db      	ldr	r3, [r3, #12]
 80058ee:	2b00      	cmp	r3, #0
 80058f0:	d023      	beq.n	800593a <HAL_RCC_OscConfig+0x38e>
      {
        /* Enable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_ENABLE();
 80058f2:	4b6f      	ldr	r3, [pc, #444]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 80058f4:	681b      	ldr	r3, [r3, #0]
 80058f6:	4a6e      	ldr	r2, [pc, #440]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 80058f8:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 80058fc:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 80058fe:	f7fe fc0d 	bl	800411c <HAL_GetTick>
 8005902:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is ready */
        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
 8005904:	e008      	b.n	8005918 <HAL_RCC_OscConfig+0x36c>
        {
          if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 8005906:	f7fe fc09 	bl	800411c <HAL_GetTick>
 800590a:	4602      	mov	r2, r0
 800590c:	693b      	ldr	r3, [r7, #16]
 800590e:	1ad3      	subs	r3, r2, r3
 8005910:	2b02      	cmp	r3, #2
 8005912:	d901      	bls.n	8005918 <HAL_RCC_OscConfig+0x36c>
          {
            return HAL_TIMEOUT;
 8005914:	2303      	movs	r3, #3
 8005916:	e255      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
 8005918:	4b65      	ldr	r3, [pc, #404]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 800591a:	681b      	ldr	r3, [r3, #0]
 800591c:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 8005920:	2b00      	cmp	r3, #0
 8005922:	d0f0      	beq.n	8005906 <HAL_RCC_OscConfig+0x35a>
          }
        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8005924:	4b62      	ldr	r3, [pc, #392]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 8005926:	685b      	ldr	r3, [r3, #4]
 8005928:	f023 42fe 	bic.w	r2, r3, #2130706432	@ 0x7f000000
 800592c:	687b      	ldr	r3, [r7, #4]
 800592e:	691b      	ldr	r3, [r3, #16]
 8005930:	061b      	lsls	r3, r3, #24
 8005932:	495f      	ldr	r1, [pc, #380]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 8005934:	4313      	orrs	r3, r2
 8005936:	604b      	str	r3, [r1, #4]
 8005938:	e018      	b.n	800596c <HAL_RCC_OscConfig+0x3c0>
      }
      else
      {
        /* Disable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_DISABLE();
 800593a:	4b5d      	ldr	r3, [pc, #372]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 800593c:	681b      	ldr	r3, [r3, #0]
 800593e:	4a5c      	ldr	r2, [pc, #368]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 8005940:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
 8005944:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8005946:	f7fe fbe9 	bl	800411c <HAL_GetTick>
 800594a:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is disabled */
        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
 800594c:	e008      	b.n	8005960 <HAL_RCC_OscConfig+0x3b4>
        {
          if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 800594e:	f7fe fbe5 	bl	800411c <HAL_GetTick>
 8005952:	4602      	mov	r2, r0
 8005954:	693b      	ldr	r3, [r7, #16]
 8005956:	1ad3      	subs	r3, r2, r3
 8005958:	2b02      	cmp	r3, #2
 800595a:	d901      	bls.n	8005960 <HAL_RCC_OscConfig+0x3b4>
          {
            return HAL_TIMEOUT;
 800595c:	2303      	movs	r3, #3
 800595e:	e231      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
        while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
 8005960:	4b53      	ldr	r3, [pc, #332]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 8005962:	681b      	ldr	r3, [r3, #0]
 8005964:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 8005968:	2b00      	cmp	r3, #0
 800596a:	d1f0      	bne.n	800594e <HAL_RCC_OscConfig+0x3a2>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 800596c:	687b      	ldr	r3, [r7, #4]
 800596e:	681b      	ldr	r3, [r3, #0]
 8005970:	f003 0308 	and.w	r3, r3, #8
 8005974:	2b00      	cmp	r3, #0
 8005976:	d03c      	beq.n	80059f2 <HAL_RCC_OscConfig+0x446>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */
    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 8005978:	687b      	ldr	r3, [r7, #4]
 800597a:	695b      	ldr	r3, [r3, #20]
 800597c:	2b00      	cmp	r3, #0
 800597e:	d01c      	beq.n	80059ba <HAL_RCC_OscConfig+0x40e>
        MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);
      }
#endif /* RCC_CSR_LSIPREDIV */

      /* Enable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_ENABLE();
 8005980:	4b4b      	ldr	r3, [pc, #300]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 8005982:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 8005986:	4a4a      	ldr	r2, [pc, #296]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 8005988:	f043 0301 	orr.w	r3, r3, #1
 800598c:	f8c2 3094 	str.w	r3, [r2, #148]	@ 0x94

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8005990:	f7fe fbc4 	bl	800411c <HAL_GetTick>
 8005994:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is ready */
      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
 8005996:	e008      	b.n	80059aa <HAL_RCC_OscConfig+0x3fe>
      {
        if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 8005998:	f7fe fbc0 	bl	800411c <HAL_GetTick>
 800599c:	4602      	mov	r2, r0
 800599e:	693b      	ldr	r3, [r7, #16]
 80059a0:	1ad3      	subs	r3, r2, r3
 80059a2:	2b02      	cmp	r3, #2
 80059a4:	d901      	bls.n	80059aa <HAL_RCC_OscConfig+0x3fe>
        {
          return HAL_TIMEOUT;
 80059a6:	2303      	movs	r3, #3
 80059a8:	e20c      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
 80059aa:	4b41      	ldr	r3, [pc, #260]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 80059ac:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 80059b0:	f003 0302 	and.w	r3, r3, #2
 80059b4:	2b00      	cmp	r3, #0
 80059b6:	d0ef      	beq.n	8005998 <HAL_RCC_OscConfig+0x3ec>
 80059b8:	e01b      	b.n	80059f2 <HAL_RCC_OscConfig+0x446>
      }
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_DISABLE();
 80059ba:	4b3d      	ldr	r3, [pc, #244]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 80059bc:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 80059c0:	4a3b      	ldr	r2, [pc, #236]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 80059c2:	f023 0301 	bic.w	r3, r3, #1
 80059c6:	f8c2 3094 	str.w	r3, [r2, #148]	@ 0x94

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 80059ca:	f7fe fba7 	bl	800411c <HAL_GetTick>
 80059ce:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is disabled */
      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
 80059d0:	e008      	b.n	80059e4 <HAL_RCC_OscConfig+0x438>
      {
        if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 80059d2:	f7fe fba3 	bl	800411c <HAL_GetTick>
 80059d6:	4602      	mov	r2, r0
 80059d8:	693b      	ldr	r3, [r7, #16]
 80059da:	1ad3      	subs	r3, r2, r3
 80059dc:	2b02      	cmp	r3, #2
 80059de:	d901      	bls.n	80059e4 <HAL_RCC_OscConfig+0x438>
        {
          return HAL_TIMEOUT;
 80059e0:	2303      	movs	r3, #3
 80059e2:	e1ef      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
      while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
 80059e4:	4b32      	ldr	r3, [pc, #200]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 80059e6:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 80059ea:	f003 0302 	and.w	r3, r3, #2
 80059ee:	2b00      	cmp	r3, #0
 80059f0:	d1ef      	bne.n	80059d2 <HAL_RCC_OscConfig+0x426>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 80059f2:	687b      	ldr	r3, [r7, #4]
 80059f4:	681b      	ldr	r3, [r3, #0]
 80059f6:	f003 0304 	and.w	r3, r3, #4
 80059fa:	2b00      	cmp	r3, #0
 80059fc:	f000 80a6 	beq.w	8005b4c <HAL_RCC_OscConfig+0x5a0>
  {
    FlagStatus       pwrclkchanged = RESET;
 8005a00:	2300      	movs	r3, #0
 8005a02:	77fb      	strb	r3, [r7, #31]
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */
    /* Requires to enable write access to Backup Domain of necessary */
    if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
 8005a04:	4b2a      	ldr	r3, [pc, #168]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 8005a06:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8005a08:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8005a0c:	2b00      	cmp	r3, #0
 8005a0e:	d10d      	bne.n	8005a2c <HAL_RCC_OscConfig+0x480>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 8005a10:	4b27      	ldr	r3, [pc, #156]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 8005a12:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8005a14:	4a26      	ldr	r2, [pc, #152]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 8005a16:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 8005a1a:	6593      	str	r3, [r2, #88]	@ 0x58
 8005a1c:	4b24      	ldr	r3, [pc, #144]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 8005a1e:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8005a20:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8005a24:	60bb      	str	r3, [r7, #8]
 8005a26:	68bb      	ldr	r3, [r7, #8]
      pwrclkchanged = SET;
 8005a28:	2301      	movs	r3, #1
 8005a2a:	77fb      	strb	r3, [r7, #31]
    }

    if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
 8005a2c:	4b21      	ldr	r3, [pc, #132]	@ (8005ab4 <HAL_RCC_OscConfig+0x508>)
 8005a2e:	681b      	ldr	r3, [r3, #0]
 8005a30:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8005a34:	2b00      	cmp	r3, #0
 8005a36:	d118      	bne.n	8005a6a <HAL_RCC_OscConfig+0x4be>
    {
      /* Enable write access to Backup domain */
      SET_BIT(PWR->CR1, PWR_CR1_DBP);
 8005a38:	4b1e      	ldr	r3, [pc, #120]	@ (8005ab4 <HAL_RCC_OscConfig+0x508>)
 8005a3a:	681b      	ldr	r3, [r3, #0]
 8005a3c:	4a1d      	ldr	r2, [pc, #116]	@ (8005ab4 <HAL_RCC_OscConfig+0x508>)
 8005a3e:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 8005a42:	6013      	str	r3, [r2, #0]

      /* Wait for Backup domain Write protection disable */
      tickstart = HAL_GetTick();
 8005a44:	f7fe fb6a 	bl	800411c <HAL_GetTick>
 8005a48:	6138      	str	r0, [r7, #16]

      while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
 8005a4a:	e008      	b.n	8005a5e <HAL_RCC_OscConfig+0x4b2>
      {
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8005a4c:	f7fe fb66 	bl	800411c <HAL_GetTick>
 8005a50:	4602      	mov	r2, r0
 8005a52:	693b      	ldr	r3, [r7, #16]
 8005a54:	1ad3      	subs	r3, r2, r3
 8005a56:	2b02      	cmp	r3, #2
 8005a58:	d901      	bls.n	8005a5e <HAL_RCC_OscConfig+0x4b2>
        {
          return HAL_TIMEOUT;
 8005a5a:	2303      	movs	r3, #3
 8005a5c:	e1b2      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
      while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
 8005a5e:	4b15      	ldr	r3, [pc, #84]	@ (8005ab4 <HAL_RCC_OscConfig+0x508>)
 8005a60:	681b      	ldr	r3, [r3, #0]
 8005a62:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8005a66:	2b00      	cmp	r3, #0
 8005a68:	d0f0      	beq.n	8005a4c <HAL_RCC_OscConfig+0x4a0>
    {
      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
    }
#else
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8005a6a:	687b      	ldr	r3, [r7, #4]
 8005a6c:	689b      	ldr	r3, [r3, #8]
 8005a6e:	2b01      	cmp	r3, #1
 8005a70:	d108      	bne.n	8005a84 <HAL_RCC_OscConfig+0x4d8>
 8005a72:	4b0f      	ldr	r3, [pc, #60]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 8005a74:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8005a78:	4a0d      	ldr	r2, [pc, #52]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 8005a7a:	f043 0301 	orr.w	r3, r3, #1
 8005a7e:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
 8005a82:	e029      	b.n	8005ad8 <HAL_RCC_OscConfig+0x52c>
 8005a84:	687b      	ldr	r3, [r7, #4]
 8005a86:	689b      	ldr	r3, [r3, #8]
 8005a88:	2b05      	cmp	r3, #5
 8005a8a:	d115      	bne.n	8005ab8 <HAL_RCC_OscConfig+0x50c>
 8005a8c:	4b08      	ldr	r3, [pc, #32]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 8005a8e:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8005a92:	4a07      	ldr	r2, [pc, #28]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 8005a94:	f043 0304 	orr.w	r3, r3, #4
 8005a98:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
 8005a9c:	4b04      	ldr	r3, [pc, #16]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 8005a9e:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8005aa2:	4a03      	ldr	r2, [pc, #12]	@ (8005ab0 <HAL_RCC_OscConfig+0x504>)
 8005aa4:	f043 0301 	orr.w	r3, r3, #1
 8005aa8:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
 8005aac:	e014      	b.n	8005ad8 <HAL_RCC_OscConfig+0x52c>
 8005aae:	bf00      	nop
 8005ab0:	40021000 	.word	0x40021000
 8005ab4:	40007000 	.word	0x40007000
 8005ab8:	4b9a      	ldr	r3, [pc, #616]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005aba:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8005abe:	4a99      	ldr	r2, [pc, #612]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005ac0:	f023 0301 	bic.w	r3, r3, #1
 8005ac4:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
 8005ac8:	4b96      	ldr	r3, [pc, #600]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005aca:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8005ace:	4a95      	ldr	r2, [pc, #596]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005ad0:	f023 0304 	bic.w	r3, r3, #4
 8005ad4:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
#endif /* RCC_BDCR_LSESYSDIS */

    /* Check the LSE State */
    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
 8005ad8:	687b      	ldr	r3, [r7, #4]
 8005ada:	689b      	ldr	r3, [r3, #8]
 8005adc:	2b00      	cmp	r3, #0
 8005ade:	d016      	beq.n	8005b0e <HAL_RCC_OscConfig+0x562>
    {
      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8005ae0:	f7fe fb1c 	bl	800411c <HAL_GetTick>
 8005ae4:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is ready */
      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 8005ae6:	e00a      	b.n	8005afe <HAL_RCC_OscConfig+0x552>
      {
        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8005ae8:	f7fe fb18 	bl	800411c <HAL_GetTick>
 8005aec:	4602      	mov	r2, r0
 8005aee:	693b      	ldr	r3, [r7, #16]
 8005af0:	1ad3      	subs	r3, r2, r3
 8005af2:	f241 3288 	movw	r2, #5000	@ 0x1388
 8005af6:	4293      	cmp	r3, r2
 8005af8:	d901      	bls.n	8005afe <HAL_RCC_OscConfig+0x552>
        {
          return HAL_TIMEOUT;
 8005afa:	2303      	movs	r3, #3
 8005afc:	e162      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 8005afe:	4b89      	ldr	r3, [pc, #548]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005b00:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8005b04:	f003 0302 	and.w	r3, r3, #2
 8005b08:	2b00      	cmp	r3, #0
 8005b0a:	d0ed      	beq.n	8005ae8 <HAL_RCC_OscConfig+0x53c>
 8005b0c:	e015      	b.n	8005b3a <HAL_RCC_OscConfig+0x58e>
      }
    }
    else
    {
      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8005b0e:	f7fe fb05 	bl	800411c <HAL_GetTick>
 8005b12:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is disabled */
      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
 8005b14:	e00a      	b.n	8005b2c <HAL_RCC_OscConfig+0x580>
      {
        if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8005b16:	f7fe fb01 	bl	800411c <HAL_GetTick>
 8005b1a:	4602      	mov	r2, r0
 8005b1c:	693b      	ldr	r3, [r7, #16]
 8005b1e:	1ad3      	subs	r3, r2, r3
 8005b20:	f241 3288 	movw	r2, #5000	@ 0x1388
 8005b24:	4293      	cmp	r3, r2
 8005b26:	d901      	bls.n	8005b2c <HAL_RCC_OscConfig+0x580>
        {
          return HAL_TIMEOUT;
 8005b28:	2303      	movs	r3, #3
 8005b2a:	e14b      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
      while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
 8005b2c:	4b7d      	ldr	r3, [pc, #500]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005b2e:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8005b32:	f003 0302 	and.w	r3, r3, #2
 8005b36:	2b00      	cmp	r3, #0
 8005b38:	d1ed      	bne.n	8005b16 <HAL_RCC_OscConfig+0x56a>
      CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
#endif /* RCC_BDCR_LSESYSDIS */
    }

    /* Restore clock configuration if changed */
    if(pwrclkchanged == SET)
 8005b3a:	7ffb      	ldrb	r3, [r7, #31]
 8005b3c:	2b01      	cmp	r3, #1
 8005b3e:	d105      	bne.n	8005b4c <HAL_RCC_OscConfig+0x5a0>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 8005b40:	4b78      	ldr	r3, [pc, #480]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005b42:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8005b44:	4a77      	ldr	r2, [pc, #476]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005b46:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 8005b4a:	6593      	str	r3, [r2, #88]	@ 0x58
    }
  }
#if defined(RCC_HSI48_SUPPORT)
  /*------------------------------ HSI48 Configuration -----------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
 8005b4c:	687b      	ldr	r3, [r7, #4]
 8005b4e:	681b      	ldr	r3, [r3, #0]
 8005b50:	f003 0320 	and.w	r3, r3, #32
 8005b54:	2b00      	cmp	r3, #0
 8005b56:	d03c      	beq.n	8005bd2 <HAL_RCC_OscConfig+0x626>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));

    /* Check the LSI State */
    if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
 8005b58:	687b      	ldr	r3, [r7, #4]
 8005b5a:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8005b5c:	2b00      	cmp	r3, #0
 8005b5e:	d01c      	beq.n	8005b9a <HAL_RCC_OscConfig+0x5ee>
    {
      /* Enable the Internal Low Speed oscillator (HSI48). */
      __HAL_RCC_HSI48_ENABLE();
 8005b60:	4b70      	ldr	r3, [pc, #448]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005b62:	f8d3 3098 	ldr.w	r3, [r3, #152]	@ 0x98
 8005b66:	4a6f      	ldr	r2, [pc, #444]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005b68:	f043 0301 	orr.w	r3, r3, #1
 8005b6c:	f8c2 3098 	str.w	r3, [r2, #152]	@ 0x98

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8005b70:	f7fe fad4 	bl	800411c <HAL_GetTick>
 8005b74:	6138      	str	r0, [r7, #16]

      /* Wait till HSI48 is ready */
      while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
 8005b76:	e008      	b.n	8005b8a <HAL_RCC_OscConfig+0x5de>
      {
        if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
 8005b78:	f7fe fad0 	bl	800411c <HAL_GetTick>
 8005b7c:	4602      	mov	r2, r0
 8005b7e:	693b      	ldr	r3, [r7, #16]
 8005b80:	1ad3      	subs	r3, r2, r3
 8005b82:	2b02      	cmp	r3, #2
 8005b84:	d901      	bls.n	8005b8a <HAL_RCC_OscConfig+0x5de>
        {
          return HAL_TIMEOUT;
 8005b86:	2303      	movs	r3, #3
 8005b88:	e11c      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
      while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
 8005b8a:	4b66      	ldr	r3, [pc, #408]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005b8c:	f8d3 3098 	ldr.w	r3, [r3, #152]	@ 0x98
 8005b90:	f003 0302 	and.w	r3, r3, #2
 8005b94:	2b00      	cmp	r3, #0
 8005b96:	d0ef      	beq.n	8005b78 <HAL_RCC_OscConfig+0x5cc>
 8005b98:	e01b      	b.n	8005bd2 <HAL_RCC_OscConfig+0x626>
      }
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (HSI48). */
      __HAL_RCC_HSI48_DISABLE();
 8005b9a:	4b62      	ldr	r3, [pc, #392]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005b9c:	f8d3 3098 	ldr.w	r3, [r3, #152]	@ 0x98
 8005ba0:	4a60      	ldr	r2, [pc, #384]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005ba2:	f023 0301 	bic.w	r3, r3, #1
 8005ba6:	f8c2 3098 	str.w	r3, [r2, #152]	@ 0x98

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8005baa:	f7fe fab7 	bl	800411c <HAL_GetTick>
 8005bae:	6138      	str	r0, [r7, #16]

      /* Wait till HSI48 is disabled */
      while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
 8005bb0:	e008      	b.n	8005bc4 <HAL_RCC_OscConfig+0x618>
      {
        if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
 8005bb2:	f7fe fab3 	bl	800411c <HAL_GetTick>
 8005bb6:	4602      	mov	r2, r0
 8005bb8:	693b      	ldr	r3, [r7, #16]
 8005bba:	1ad3      	subs	r3, r2, r3
 8005bbc:	2b02      	cmp	r3, #2
 8005bbe:	d901      	bls.n	8005bc4 <HAL_RCC_OscConfig+0x618>
        {
          return HAL_TIMEOUT;
 8005bc0:	2303      	movs	r3, #3
 8005bc2:	e0ff      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
      while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
 8005bc4:	4b57      	ldr	r3, [pc, #348]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005bc6:	f8d3 3098 	ldr.w	r3, [r3, #152]	@ 0x98
 8005bca:	f003 0302 	and.w	r3, r3, #2
 8005bce:	2b00      	cmp	r3, #0
 8005bd0:	d1ef      	bne.n	8005bb2 <HAL_RCC_OscConfig+0x606>
#endif /* RCC_HSI48_SUPPORT */
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));

  if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
 8005bd2:	687b      	ldr	r3, [r7, #4]
 8005bd4:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8005bd6:	2b00      	cmp	r3, #0
 8005bd8:	f000 80f3 	beq.w	8005dc2 <HAL_RCC_OscConfig+0x816>
  {
    /* PLL On ? */
    if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
 8005bdc:	687b      	ldr	r3, [r7, #4]
 8005bde:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8005be0:	2b02      	cmp	r3, #2
 8005be2:	f040 80c9 	bne.w	8005d78 <HAL_RCC_OscConfig+0x7cc>
#endif /* RCC_PLLP_SUPPORT */
      assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
      assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));

      /* Do nothing if PLL configuration is the unchanged */
      pll_config = RCC->PLLCFGR;
 8005be6:	4b4f      	ldr	r3, [pc, #316]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005be8:	68db      	ldr	r3, [r3, #12]
 8005bea:	617b      	str	r3, [r7, #20]
      if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||
 8005bec:	697b      	ldr	r3, [r7, #20]
 8005bee:	f003 0203 	and.w	r2, r3, #3
 8005bf2:	687b      	ldr	r3, [r7, #4]
 8005bf4:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8005bf6:	429a      	cmp	r2, r3
 8005bf8:	d12c      	bne.n	8005c54 <HAL_RCC_OscConfig+0x6a8>
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLM)    != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
 8005bfa:	697b      	ldr	r3, [r7, #20]
 8005bfc:	f003 0270 	and.w	r2, r3, #112	@ 0x70
 8005c00:	687b      	ldr	r3, [r7, #4]
 8005c02:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8005c04:	3b01      	subs	r3, #1
 8005c06:	011b      	lsls	r3, r3, #4
      if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||
 8005c08:	429a      	cmp	r2, r3
 8005c0a:	d123      	bne.n	8005c54 <HAL_RCC_OscConfig+0x6a8>
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLN)    != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
 8005c0c:	697b      	ldr	r3, [r7, #20]
 8005c0e:	f403 42fe 	and.w	r2, r3, #32512	@ 0x7f00
 8005c12:	687b      	ldr	r3, [r7, #4]
 8005c14:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 8005c16:	021b      	lsls	r3, r3, #8
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLM)    != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
 8005c18:	429a      	cmp	r2, r3
 8005c1a:	d11b      	bne.n	8005c54 <HAL_RCC_OscConfig+0x6a8>
#if defined(RCC_PLLP_SUPPORT)
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
 8005c1c:	697b      	ldr	r3, [r7, #20]
 8005c1e:	f003 4278 	and.w	r2, r3, #4160749568	@ 0xf8000000
 8005c22:	687b      	ldr	r3, [r7, #4]
 8005c24:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8005c26:	06db      	lsls	r3, r3, #27
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLN)    != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
 8005c28:	429a      	cmp	r2, r3
 8005c2a:	d113      	bne.n	8005c54 <HAL_RCC_OscConfig+0x6a8>
#else
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLP)    != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
#endif
#endif
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ)    != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
 8005c2c:	697b      	ldr	r3, [r7, #20]
 8005c2e:	f403 02c0 	and.w	r2, r3, #6291456	@ 0x600000
 8005c32:	687b      	ldr	r3, [r7, #4]
 8005c34:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8005c36:	085b      	lsrs	r3, r3, #1
 8005c38:	3b01      	subs	r3, #1
 8005c3a:	055b      	lsls	r3, r3, #21
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
 8005c3c:	429a      	cmp	r2, r3
 8005c3e:	d109      	bne.n	8005c54 <HAL_RCC_OscConfig+0x6a8>
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLR)    != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
 8005c40:	697b      	ldr	r3, [r7, #20]
 8005c42:	f003 62c0 	and.w	r2, r3, #100663296	@ 0x6000000
 8005c46:	687b      	ldr	r3, [r7, #4]
 8005c48:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8005c4a:	085b      	lsrs	r3, r3, #1
 8005c4c:	3b01      	subs	r3, #1
 8005c4e:	065b      	lsls	r3, r3, #25
         (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ)    != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
 8005c50:	429a      	cmp	r2, r3
 8005c52:	d06b      	beq.n	8005d2c <HAL_RCC_OscConfig+0x780>
      {
        /* Check if the PLL is used as system clock or not */
        if(sysclk_source != RCC_CFGR_SWS_PLL)
 8005c54:	69bb      	ldr	r3, [r7, #24]
 8005c56:	2b0c      	cmp	r3, #12
 8005c58:	d062      	beq.n	8005d20 <HAL_RCC_OscConfig+0x774>
        {
#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT)
          /* Check if main PLL can be updated */
          /* Not possible if the source is shared by other enabled PLLSAIx */
          if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
 8005c5a:	4b32      	ldr	r3, [pc, #200]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005c5c:	681b      	ldr	r3, [r3, #0]
 8005c5e:	f003 6380 	and.w	r3, r3, #67108864	@ 0x4000000
 8005c62:	2b00      	cmp	r3, #0
 8005c64:	d001      	beq.n	8005c6a <HAL_RCC_OscConfig+0x6be>
#if defined(RCC_PLLSAI2_SUPPORT)
             || (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U)
#endif
            )
          {
            return HAL_ERROR;
 8005c66:	2301      	movs	r3, #1
 8005c68:	e0ac      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
          }
          else
#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */
          {
            /* Disable the main PLL. */
            __HAL_RCC_PLL_DISABLE();
 8005c6a:	4b2e      	ldr	r3, [pc, #184]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005c6c:	681b      	ldr	r3, [r3, #0]
 8005c6e:	4a2d      	ldr	r2, [pc, #180]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005c70:	f023 7380 	bic.w	r3, r3, #16777216	@ 0x1000000
 8005c74:	6013      	str	r3, [r2, #0]

            /* Get Start Tick*/
            tickstart = HAL_GetTick();
 8005c76:	f7fe fa51 	bl	800411c <HAL_GetTick>
 8005c7a:	6138      	str	r0, [r7, #16]

            /* Wait till PLL is ready */
            while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8005c7c:	e008      	b.n	8005c90 <HAL_RCC_OscConfig+0x6e4>
            {
              if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8005c7e:	f7fe fa4d 	bl	800411c <HAL_GetTick>
 8005c82:	4602      	mov	r2, r0
 8005c84:	693b      	ldr	r3, [r7, #16]
 8005c86:	1ad3      	subs	r3, r2, r3
 8005c88:	2b02      	cmp	r3, #2
 8005c8a:	d901      	bls.n	8005c90 <HAL_RCC_OscConfig+0x6e4>
              {
                return HAL_TIMEOUT;
 8005c8c:	2303      	movs	r3, #3
 8005c8e:	e099      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
            while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8005c90:	4b24      	ldr	r3, [pc, #144]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005c92:	681b      	ldr	r3, [r3, #0]
 8005c94:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8005c98:	2b00      	cmp	r3, #0
 8005c9a:	d1f0      	bne.n	8005c7e <HAL_RCC_OscConfig+0x6d2>
              }
            }

            /* Configure the main PLL clock source, multiplication and division factors. */
#if defined(RCC_PLLP_SUPPORT)
            __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 8005c9c:	4b21      	ldr	r3, [pc, #132]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005c9e:	68da      	ldr	r2, [r3, #12]
 8005ca0:	4b21      	ldr	r3, [pc, #132]	@ (8005d28 <HAL_RCC_OscConfig+0x77c>)
 8005ca2:	4013      	ands	r3, r2
 8005ca4:	687a      	ldr	r2, [r7, #4]
 8005ca6:	6ad1      	ldr	r1, [r2, #44]	@ 0x2c
 8005ca8:	687a      	ldr	r2, [r7, #4]
 8005caa:	6b12      	ldr	r2, [r2, #48]	@ 0x30
 8005cac:	3a01      	subs	r2, #1
 8005cae:	0112      	lsls	r2, r2, #4
 8005cb0:	4311      	orrs	r1, r2
 8005cb2:	687a      	ldr	r2, [r7, #4]
 8005cb4:	6b52      	ldr	r2, [r2, #52]	@ 0x34
 8005cb6:	0212      	lsls	r2, r2, #8
 8005cb8:	4311      	orrs	r1, r2
 8005cba:	687a      	ldr	r2, [r7, #4]
 8005cbc:	6bd2      	ldr	r2, [r2, #60]	@ 0x3c
 8005cbe:	0852      	lsrs	r2, r2, #1
 8005cc0:	3a01      	subs	r2, #1
 8005cc2:	0552      	lsls	r2, r2, #21
 8005cc4:	4311      	orrs	r1, r2
 8005cc6:	687a      	ldr	r2, [r7, #4]
 8005cc8:	6c12      	ldr	r2, [r2, #64]	@ 0x40
 8005cca:	0852      	lsrs	r2, r2, #1
 8005ccc:	3a01      	subs	r2, #1
 8005cce:	0652      	lsls	r2, r2, #25
 8005cd0:	4311      	orrs	r1, r2
 8005cd2:	687a      	ldr	r2, [r7, #4]
 8005cd4:	6b92      	ldr	r2, [r2, #56]	@ 0x38
 8005cd6:	06d2      	lsls	r2, r2, #27
 8005cd8:	430a      	orrs	r2, r1
 8005cda:	4912      	ldr	r1, [pc, #72]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005cdc:	4313      	orrs	r3, r2
 8005cde:	60cb      	str	r3, [r1, #12]
                                 RCC_OscInitStruct->PLL.PLLQ,
                                 RCC_OscInitStruct->PLL.PLLR);
#endif

            /* Enable the main PLL. */
            __HAL_RCC_PLL_ENABLE();
 8005ce0:	4b10      	ldr	r3, [pc, #64]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005ce2:	681b      	ldr	r3, [r3, #0]
 8005ce4:	4a0f      	ldr	r2, [pc, #60]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005ce6:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 8005cea:	6013      	str	r3, [r2, #0]

            /* Enable PLL System Clock output. */
            __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
 8005cec:	4b0d      	ldr	r3, [pc, #52]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005cee:	68db      	ldr	r3, [r3, #12]
 8005cf0:	4a0c      	ldr	r2, [pc, #48]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005cf2:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 8005cf6:	60d3      	str	r3, [r2, #12]

            /* Get Start Tick*/
            tickstart = HAL_GetTick();
 8005cf8:	f7fe fa10 	bl	800411c <HAL_GetTick>
 8005cfc:	6138      	str	r0, [r7, #16]

            /* Wait till PLL is ready */
            while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8005cfe:	e008      	b.n	8005d12 <HAL_RCC_OscConfig+0x766>
            {
              if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8005d00:	f7fe fa0c 	bl	800411c <HAL_GetTick>
 8005d04:	4602      	mov	r2, r0
 8005d06:	693b      	ldr	r3, [r7, #16]
 8005d08:	1ad3      	subs	r3, r2, r3
 8005d0a:	2b02      	cmp	r3, #2
 8005d0c:	d901      	bls.n	8005d12 <HAL_RCC_OscConfig+0x766>
              {
                return HAL_TIMEOUT;
 8005d0e:	2303      	movs	r3, #3
 8005d10:	e058      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
            while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8005d12:	4b04      	ldr	r3, [pc, #16]	@ (8005d24 <HAL_RCC_OscConfig+0x778>)
 8005d14:	681b      	ldr	r3, [r3, #0]
 8005d16:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8005d1a:	2b00      	cmp	r3, #0
 8005d1c:	d0f0      	beq.n	8005d00 <HAL_RCC_OscConfig+0x754>
        if(sysclk_source != RCC_CFGR_SWS_PLL)
 8005d1e:	e050      	b.n	8005dc2 <HAL_RCC_OscConfig+0x816>
          }
        }
        else
        {
          /* PLL is already used as System core clock */
          return HAL_ERROR;
 8005d20:	2301      	movs	r3, #1
 8005d22:	e04f      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
 8005d24:	40021000 	.word	0x40021000
 8005d28:	019d808c 	.word	0x019d808c
      }
      else
      {
        /* PLL configuration is unchanged */
        /* Re-enable PLL if it was disabled (ie. low power mode) */
        if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8005d2c:	4b27      	ldr	r3, [pc, #156]	@ (8005dcc <HAL_RCC_OscConfig+0x820>)
 8005d2e:	681b      	ldr	r3, [r3, #0]
 8005d30:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8005d34:	2b00      	cmp	r3, #0
 8005d36:	d144      	bne.n	8005dc2 <HAL_RCC_OscConfig+0x816>
        {
          /* Enable the main PLL. */
          __HAL_RCC_PLL_ENABLE();
 8005d38:	4b24      	ldr	r3, [pc, #144]	@ (8005dcc <HAL_RCC_OscConfig+0x820>)
 8005d3a:	681b      	ldr	r3, [r3, #0]
 8005d3c:	4a23      	ldr	r2, [pc, #140]	@ (8005dcc <HAL_RCC_OscConfig+0x820>)
 8005d3e:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 8005d42:	6013      	str	r3, [r2, #0]

          /* Enable PLL System Clock output. */
          __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
 8005d44:	4b21      	ldr	r3, [pc, #132]	@ (8005dcc <HAL_RCC_OscConfig+0x820>)
 8005d46:	68db      	ldr	r3, [r3, #12]
 8005d48:	4a20      	ldr	r2, [pc, #128]	@ (8005dcc <HAL_RCC_OscConfig+0x820>)
 8005d4a:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
 8005d4e:	60d3      	str	r3, [r2, #12]

          /* Get Start Tick*/
          tickstart = HAL_GetTick();
 8005d50:	f7fe f9e4 	bl	800411c <HAL_GetTick>
 8005d54:	6138      	str	r0, [r7, #16]

          /* Wait till PLL is ready */
          while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8005d56:	e008      	b.n	8005d6a <HAL_RCC_OscConfig+0x7be>
          {
            if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8005d58:	f7fe f9e0 	bl	800411c <HAL_GetTick>
 8005d5c:	4602      	mov	r2, r0
 8005d5e:	693b      	ldr	r3, [r7, #16]
 8005d60:	1ad3      	subs	r3, r2, r3
 8005d62:	2b02      	cmp	r3, #2
 8005d64:	d901      	bls.n	8005d6a <HAL_RCC_OscConfig+0x7be>
            {
              return HAL_TIMEOUT;
 8005d66:	2303      	movs	r3, #3
 8005d68:	e02c      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
          while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8005d6a:	4b18      	ldr	r3, [pc, #96]	@ (8005dcc <HAL_RCC_OscConfig+0x820>)
 8005d6c:	681b      	ldr	r3, [r3, #0]
 8005d6e:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8005d72:	2b00      	cmp	r3, #0
 8005d74:	d0f0      	beq.n	8005d58 <HAL_RCC_OscConfig+0x7ac>
 8005d76:	e024      	b.n	8005dc2 <HAL_RCC_OscConfig+0x816>
      }
    }
    else
    {
      /* Check that PLL is not used as system clock or not */
      if(sysclk_source != RCC_CFGR_SWS_PLL)
 8005d78:	69bb      	ldr	r3, [r7, #24]
 8005d7a:	2b0c      	cmp	r3, #12
 8005d7c:	d01f      	beq.n	8005dbe <HAL_RCC_OscConfig+0x812>
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8005d7e:	4b13      	ldr	r3, [pc, #76]	@ (8005dcc <HAL_RCC_OscConfig+0x820>)
 8005d80:	681b      	ldr	r3, [r3, #0]
 8005d82:	4a12      	ldr	r2, [pc, #72]	@ (8005dcc <HAL_RCC_OscConfig+0x820>)
 8005d84:	f023 7380 	bic.w	r3, r3, #16777216	@ 0x1000000
 8005d88:	6013      	str	r3, [r2, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8005d8a:	f7fe f9c7 	bl	800411c <HAL_GetTick>
 8005d8e:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is disabled */
        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8005d90:	e008      	b.n	8005da4 <HAL_RCC_OscConfig+0x7f8>
        {
          if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8005d92:	f7fe f9c3 	bl	800411c <HAL_GetTick>
 8005d96:	4602      	mov	r2, r0
 8005d98:	693b      	ldr	r3, [r7, #16]
 8005d9a:	1ad3      	subs	r3, r2, r3
 8005d9c:	2b02      	cmp	r3, #2
 8005d9e:	d901      	bls.n	8005da4 <HAL_RCC_OscConfig+0x7f8>
          {
            return HAL_TIMEOUT;
 8005da0:	2303      	movs	r3, #3
 8005da2:	e00f      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
        while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
 8005da4:	4b09      	ldr	r3, [pc, #36]	@ (8005dcc <HAL_RCC_OscConfig+0x820>)
 8005da6:	681b      	ldr	r3, [r3, #0]
 8005da8:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8005dac:	2b00      	cmp	r3, #0
 8005dae:	d1f0      	bne.n	8005d92 <HAL_RCC_OscConfig+0x7e6>
        }
        /* Unselect main PLL clock source and disable main PLL outputs to save power */
#if defined(RCC_PLLSAI2_SUPPORT)
        RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
#elif defined(RCC_PLLSAI1_SUPPORT)
        RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI2CLK);
 8005db0:	4b06      	ldr	r3, [pc, #24]	@ (8005dcc <HAL_RCC_OscConfig+0x820>)
 8005db2:	68da      	ldr	r2, [r3, #12]
 8005db4:	4905      	ldr	r1, [pc, #20]	@ (8005dcc <HAL_RCC_OscConfig+0x820>)
 8005db6:	4b06      	ldr	r3, [pc, #24]	@ (8005dd0 <HAL_RCC_OscConfig+0x824>)
 8005db8:	4013      	ands	r3, r2
 8005dba:	60cb      	str	r3, [r1, #12]
 8005dbc:	e001      	b.n	8005dc2 <HAL_RCC_OscConfig+0x816>
#endif /* RCC_PLLSAI2_SUPPORT */
      }
      else
      {
        /* PLL is already used as System core clock */
        return HAL_ERROR;
 8005dbe:	2301      	movs	r3, #1
 8005dc0:	e000      	b.n	8005dc4 <HAL_RCC_OscConfig+0x818>
      }
    }
  }
  return HAL_OK;
 8005dc2:	2300      	movs	r3, #0
}
 8005dc4:	4618      	mov	r0, r3
 8005dc6:	3720      	adds	r7, #32
 8005dc8:	46bd      	mov	sp, r7
 8005dca:	bd80      	pop	{r7, pc}
 8005dcc:	40021000 	.word	0x40021000
 8005dd0:	feeefffc 	.word	0xfeeefffc

08005dd4 <HAL_RCC_ClockConfig>:
  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
  *         (for more details refer to section above "Initialization/de-initialization functions")
  * @retval None
  */
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
{
 8005dd4:	b580      	push	{r7, lr}
 8005dd6:	b084      	sub	sp, #16
 8005dd8:	af00      	add	r7, sp, #0
 8005dda:	6078      	str	r0, [r7, #4]
 8005ddc:	6039      	str	r1, [r7, #0]
  uint32_t hpre = RCC_SYSCLK_DIV1;
#endif
  HAL_StatusTypeDef status;

  /* Check Null pointer */
  if(RCC_ClkInitStruct == NULL)
 8005dde:	687b      	ldr	r3, [r7, #4]
 8005de0:	2b00      	cmp	r3, #0
 8005de2:	d101      	bne.n	8005de8 <HAL_RCC_ClockConfig+0x14>
  {
    return HAL_ERROR;
 8005de4:	2301      	movs	r3, #1
 8005de6:	e0e7      	b.n	8005fb8 <HAL_RCC_ClockConfig+0x1e4>
  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
    must be correctly programmed according to the frequency of the CPU clock
    (HCLK) and the supply voltage of the device. */

  /* Increasing the number of wait states because of higher CPU frequency */
  if(FLatency > __HAL_FLASH_GET_LATENCY())
 8005de8:	4b75      	ldr	r3, [pc, #468]	@ (8005fc0 <HAL_RCC_ClockConfig+0x1ec>)
 8005dea:	681b      	ldr	r3, [r3, #0]
 8005dec:	f003 0307 	and.w	r3, r3, #7
 8005df0:	683a      	ldr	r2, [r7, #0]
 8005df2:	429a      	cmp	r2, r3
 8005df4:	d910      	bls.n	8005e18 <HAL_RCC_ClockConfig+0x44>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8005df6:	4b72      	ldr	r3, [pc, #456]	@ (8005fc0 <HAL_RCC_ClockConfig+0x1ec>)
 8005df8:	681b      	ldr	r3, [r3, #0]
 8005dfa:	f023 0207 	bic.w	r2, r3, #7
 8005dfe:	4970      	ldr	r1, [pc, #448]	@ (8005fc0 <HAL_RCC_ClockConfig+0x1ec>)
 8005e00:	683b      	ldr	r3, [r7, #0]
 8005e02:	4313      	orrs	r3, r2
 8005e04:	600b      	str	r3, [r1, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 8005e06:	4b6e      	ldr	r3, [pc, #440]	@ (8005fc0 <HAL_RCC_ClockConfig+0x1ec>)
 8005e08:	681b      	ldr	r3, [r3, #0]
 8005e0a:	f003 0307 	and.w	r3, r3, #7
 8005e0e:	683a      	ldr	r2, [r7, #0]
 8005e10:	429a      	cmp	r2, r3
 8005e12:	d001      	beq.n	8005e18 <HAL_RCC_ClockConfig+0x44>
    {
      return HAL_ERROR;
 8005e14:	2301      	movs	r3, #1
 8005e16:	e0cf      	b.n	8005fb8 <HAL_RCC_ClockConfig+0x1e4>
    }
  }

  /*----------------- HCLK Configuration prior to SYSCLK----------------------*/
  /* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8005e18:	687b      	ldr	r3, [r7, #4]
 8005e1a:	681b      	ldr	r3, [r3, #0]
 8005e1c:	f003 0302 	and.w	r3, r3, #2
 8005e20:	2b00      	cmp	r3, #0
 8005e22:	d010      	beq.n	8005e46 <HAL_RCC_ClockConfig+0x72>
  {
    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));

    if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
 8005e24:	687b      	ldr	r3, [r7, #4]
 8005e26:	689a      	ldr	r2, [r3, #8]
 8005e28:	4b66      	ldr	r3, [pc, #408]	@ (8005fc4 <HAL_RCC_ClockConfig+0x1f0>)
 8005e2a:	689b      	ldr	r3, [r3, #8]
 8005e2c:	f003 03f0 	and.w	r3, r3, #240	@ 0xf0
 8005e30:	429a      	cmp	r2, r3
 8005e32:	d908      	bls.n	8005e46 <HAL_RCC_ClockConfig+0x72>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8005e34:	4b63      	ldr	r3, [pc, #396]	@ (8005fc4 <HAL_RCC_ClockConfig+0x1f0>)
 8005e36:	689b      	ldr	r3, [r3, #8]
 8005e38:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
 8005e3c:	687b      	ldr	r3, [r7, #4]
 8005e3e:	689b      	ldr	r3, [r3, #8]
 8005e40:	4960      	ldr	r1, [pc, #384]	@ (8005fc4 <HAL_RCC_ClockConfig+0x1f0>)
 8005e42:	4313      	orrs	r3, r2
 8005e44:	608b      	str	r3, [r1, #8]
    }
  }

  /*------------------------- SYSCLK Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8005e46:	687b      	ldr	r3, [r7, #4]
 8005e48:	681b      	ldr	r3, [r3, #0]
 8005e4a:	f003 0301 	and.w	r3, r3, #1
 8005e4e:	2b00      	cmp	r3, #0
 8005e50:	d04c      	beq.n	8005eec <HAL_RCC_ClockConfig+0x118>
  {
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));

    /* PLL is selected as System Clock Source */
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8005e52:	687b      	ldr	r3, [r7, #4]
 8005e54:	685b      	ldr	r3, [r3, #4]
 8005e56:	2b03      	cmp	r3, #3
 8005e58:	d107      	bne.n	8005e6a <HAL_RCC_ClockConfig+0x96>
    {
      /* Check the PLL ready flag */
      if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
 8005e5a:	4b5a      	ldr	r3, [pc, #360]	@ (8005fc4 <HAL_RCC_ClockConfig+0x1f0>)
 8005e5c:	681b      	ldr	r3, [r3, #0]
 8005e5e:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
 8005e62:	2b00      	cmp	r3, #0
 8005e64:	d121      	bne.n	8005eaa <HAL_RCC_ClockConfig+0xd6>
      {
        return HAL_ERROR;
 8005e66:	2301      	movs	r3, #1
 8005e68:	e0a6      	b.n	8005fb8 <HAL_RCC_ClockConfig+0x1e4>
#endif
    }
    else
    {
      /* HSE is selected as System Clock Source */
      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8005e6a:	687b      	ldr	r3, [r7, #4]
 8005e6c:	685b      	ldr	r3, [r3, #4]
 8005e6e:	2b02      	cmp	r3, #2
 8005e70:	d107      	bne.n	8005e82 <HAL_RCC_ClockConfig+0xae>
      {
        /* Check the HSE ready flag */
        if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
 8005e72:	4b54      	ldr	r3, [pc, #336]	@ (8005fc4 <HAL_RCC_ClockConfig+0x1f0>)
 8005e74:	681b      	ldr	r3, [r3, #0]
 8005e76:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8005e7a:	2b00      	cmp	r3, #0
 8005e7c:	d115      	bne.n	8005eaa <HAL_RCC_ClockConfig+0xd6>
        {
          return HAL_ERROR;
 8005e7e:	2301      	movs	r3, #1
 8005e80:	e09a      	b.n	8005fb8 <HAL_RCC_ClockConfig+0x1e4>
        }
      }
      /* MSI is selected as System Clock Source */
      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
 8005e82:	687b      	ldr	r3, [r7, #4]
 8005e84:	685b      	ldr	r3, [r3, #4]
 8005e86:	2b00      	cmp	r3, #0
 8005e88:	d107      	bne.n	8005e9a <HAL_RCC_ClockConfig+0xc6>
      {
        /* Check the MSI ready flag */
        if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
 8005e8a:	4b4e      	ldr	r3, [pc, #312]	@ (8005fc4 <HAL_RCC_ClockConfig+0x1f0>)
 8005e8c:	681b      	ldr	r3, [r3, #0]
 8005e8e:	f003 0302 	and.w	r3, r3, #2
 8005e92:	2b00      	cmp	r3, #0
 8005e94:	d109      	bne.n	8005eaa <HAL_RCC_ClockConfig+0xd6>
        {
          return HAL_ERROR;
 8005e96:	2301      	movs	r3, #1
 8005e98:	e08e      	b.n	8005fb8 <HAL_RCC_ClockConfig+0x1e4>
      }
      /* HSI is selected as System Clock Source */
      else
      {
        /* Check the HSI ready flag */
        if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
 8005e9a:	4b4a      	ldr	r3, [pc, #296]	@ (8005fc4 <HAL_RCC_ClockConfig+0x1f0>)
 8005e9c:	681b      	ldr	r3, [r3, #0]
 8005e9e:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 8005ea2:	2b00      	cmp	r3, #0
 8005ea4:	d101      	bne.n	8005eaa <HAL_RCC_ClockConfig+0xd6>
        {
          return HAL_ERROR;
 8005ea6:	2301      	movs	r3, #1
 8005ea8:	e086      	b.n	8005fb8 <HAL_RCC_ClockConfig+0x1e4>
      }
#endif

    }

    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
 8005eaa:	4b46      	ldr	r3, [pc, #280]	@ (8005fc4 <HAL_RCC_ClockConfig+0x1f0>)
 8005eac:	689b      	ldr	r3, [r3, #8]
 8005eae:	f023 0203 	bic.w	r2, r3, #3
 8005eb2:	687b      	ldr	r3, [r7, #4]
 8005eb4:	685b      	ldr	r3, [r3, #4]
 8005eb6:	4943      	ldr	r1, [pc, #268]	@ (8005fc4 <HAL_RCC_ClockConfig+0x1f0>)
 8005eb8:	4313      	orrs	r3, r2
 8005eba:	608b      	str	r3, [r1, #8]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 8005ebc:	f7fe f92e 	bl	800411c <HAL_GetTick>
 8005ec0:	60f8      	str	r0, [r7, #12]

    while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8005ec2:	e00a      	b.n	8005eda <HAL_RCC_ClockConfig+0x106>
    {
      if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 8005ec4:	f7fe f92a 	bl	800411c <HAL_GetTick>
 8005ec8:	4602      	mov	r2, r0
 8005eca:	68fb      	ldr	r3, [r7, #12]
 8005ecc:	1ad3      	subs	r3, r2, r3
 8005ece:	f241 3288 	movw	r2, #5000	@ 0x1388
 8005ed2:	4293      	cmp	r3, r2
 8005ed4:	d901      	bls.n	8005eda <HAL_RCC_ClockConfig+0x106>
      {
        return HAL_TIMEOUT;
 8005ed6:	2303      	movs	r3, #3
 8005ed8:	e06e      	b.n	8005fb8 <HAL_RCC_ClockConfig+0x1e4>
    while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8005eda:	4b3a      	ldr	r3, [pc, #232]	@ (8005fc4 <HAL_RCC_ClockConfig+0x1f0>)
 8005edc:	689b      	ldr	r3, [r3, #8]
 8005ede:	f003 020c 	and.w	r2, r3, #12
 8005ee2:	687b      	ldr	r3, [r7, #4]
 8005ee4:	685b      	ldr	r3, [r3, #4]
 8005ee6:	009b      	lsls	r3, r3, #2
 8005ee8:	429a      	cmp	r2, r3
 8005eea:	d1eb      	bne.n	8005ec4 <HAL_RCC_ClockConfig+0xf0>
  }
#endif

  /*----------------- HCLK Configuration after SYSCLK-------------------------*/
  /* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8005eec:	687b      	ldr	r3, [r7, #4]
 8005eee:	681b      	ldr	r3, [r3, #0]
 8005ef0:	f003 0302 	and.w	r3, r3, #2
 8005ef4:	2b00      	cmp	r3, #0
 8005ef6:	d010      	beq.n	8005f1a <HAL_RCC_ClockConfig+0x146>
  {
    if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
 8005ef8:	687b      	ldr	r3, [r7, #4]
 8005efa:	689a      	ldr	r2, [r3, #8]
 8005efc:	4b31      	ldr	r3, [pc, #196]	@ (8005fc4 <HAL_RCC_ClockConfig+0x1f0>)
 8005efe:	689b      	ldr	r3, [r3, #8]
 8005f00:	f003 03f0 	and.w	r3, r3, #240	@ 0xf0
 8005f04:	429a      	cmp	r2, r3
 8005f06:	d208      	bcs.n	8005f1a <HAL_RCC_ClockConfig+0x146>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8005f08:	4b2e      	ldr	r3, [pc, #184]	@ (8005fc4 <HAL_RCC_ClockConfig+0x1f0>)
 8005f0a:	689b      	ldr	r3, [r3, #8]
 8005f0c:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
 8005f10:	687b      	ldr	r3, [r7, #4]
 8005f12:	689b      	ldr	r3, [r3, #8]
 8005f14:	492b      	ldr	r1, [pc, #172]	@ (8005fc4 <HAL_RCC_ClockConfig+0x1f0>)
 8005f16:	4313      	orrs	r3, r2
 8005f18:	608b      	str	r3, [r1, #8]
    }
  }

  /* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */
  if(FLatency < __HAL_FLASH_GET_LATENCY())
 8005f1a:	4b29      	ldr	r3, [pc, #164]	@ (8005fc0 <HAL_RCC_ClockConfig+0x1ec>)
 8005f1c:	681b      	ldr	r3, [r3, #0]
 8005f1e:	f003 0307 	and.w	r3, r3, #7
 8005f22:	683a      	ldr	r2, [r7, #0]
 8005f24:	429a      	cmp	r2, r3
 8005f26:	d210      	bcs.n	8005f4a <HAL_RCC_ClockConfig+0x176>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8005f28:	4b25      	ldr	r3, [pc, #148]	@ (8005fc0 <HAL_RCC_ClockConfig+0x1ec>)
 8005f2a:	681b      	ldr	r3, [r3, #0]
 8005f2c:	f023 0207 	bic.w	r2, r3, #7
 8005f30:	4923      	ldr	r1, [pc, #140]	@ (8005fc0 <HAL_RCC_ClockConfig+0x1ec>)
 8005f32:	683b      	ldr	r3, [r7, #0]
 8005f34:	4313      	orrs	r3, r2
 8005f36:	600b      	str	r3, [r1, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 8005f38:	4b21      	ldr	r3, [pc, #132]	@ (8005fc0 <HAL_RCC_ClockConfig+0x1ec>)
 8005f3a:	681b      	ldr	r3, [r3, #0]
 8005f3c:	f003 0307 	and.w	r3, r3, #7
 8005f40:	683a      	ldr	r2, [r7, #0]
 8005f42:	429a      	cmp	r2, r3
 8005f44:	d001      	beq.n	8005f4a <HAL_RCC_ClockConfig+0x176>
    {
      return HAL_ERROR;
 8005f46:	2301      	movs	r3, #1
 8005f48:	e036      	b.n	8005fb8 <HAL_RCC_ClockConfig+0x1e4>
    }
  }

  /*-------------------------- PCLK1 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8005f4a:	687b      	ldr	r3, [r7, #4]
 8005f4c:	681b      	ldr	r3, [r3, #0]
 8005f4e:	f003 0304 	and.w	r3, r3, #4
 8005f52:	2b00      	cmp	r3, #0
 8005f54:	d008      	beq.n	8005f68 <HAL_RCC_ClockConfig+0x194>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 8005f56:	4b1b      	ldr	r3, [pc, #108]	@ (8005fc4 <HAL_RCC_ClockConfig+0x1f0>)
 8005f58:	689b      	ldr	r3, [r3, #8]
 8005f5a:	f423 62e0 	bic.w	r2, r3, #1792	@ 0x700
 8005f5e:	687b      	ldr	r3, [r7, #4]
 8005f60:	68db      	ldr	r3, [r3, #12]
 8005f62:	4918      	ldr	r1, [pc, #96]	@ (8005fc4 <HAL_RCC_ClockConfig+0x1f0>)
 8005f64:	4313      	orrs	r3, r2
 8005f66:	608b      	str	r3, [r1, #8]
  }

  /*-------------------------- PCLK2 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8005f68:	687b      	ldr	r3, [r7, #4]
 8005f6a:	681b      	ldr	r3, [r3, #0]
 8005f6c:	f003 0308 	and.w	r3, r3, #8
 8005f70:	2b00      	cmp	r3, #0
 8005f72:	d009      	beq.n	8005f88 <HAL_RCC_ClockConfig+0x1b4>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
 8005f74:	4b13      	ldr	r3, [pc, #76]	@ (8005fc4 <HAL_RCC_ClockConfig+0x1f0>)
 8005f76:	689b      	ldr	r3, [r3, #8]
 8005f78:	f423 5260 	bic.w	r2, r3, #14336	@ 0x3800
 8005f7c:	687b      	ldr	r3, [r7, #4]
 8005f7e:	691b      	ldr	r3, [r3, #16]
 8005f80:	00db      	lsls	r3, r3, #3
 8005f82:	4910      	ldr	r1, [pc, #64]	@ (8005fc4 <HAL_RCC_ClockConfig+0x1f0>)
 8005f84:	4313      	orrs	r3, r2
 8005f86:	608b      	str	r3, [r1, #8]
  }

  /* Update the SystemCoreClock global variable */
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
 8005f88:	f000 f824 	bl	8005fd4 <HAL_RCC_GetSysClockFreq>
 8005f8c:	4602      	mov	r2, r0
 8005f8e:	4b0d      	ldr	r3, [pc, #52]	@ (8005fc4 <HAL_RCC_ClockConfig+0x1f0>)
 8005f90:	689b      	ldr	r3, [r3, #8]
 8005f92:	091b      	lsrs	r3, r3, #4
 8005f94:	f003 030f 	and.w	r3, r3, #15
 8005f98:	490b      	ldr	r1, [pc, #44]	@ (8005fc8 <HAL_RCC_ClockConfig+0x1f4>)
 8005f9a:	5ccb      	ldrb	r3, [r1, r3]
 8005f9c:	f003 031f 	and.w	r3, r3, #31
 8005fa0:	fa22 f303 	lsr.w	r3, r2, r3
 8005fa4:	4a09      	ldr	r2, [pc, #36]	@ (8005fcc <HAL_RCC_ClockConfig+0x1f8>)
 8005fa6:	6013      	str	r3, [r2, #0]

  /* Configure the source of time base considering new system clocks settings*/
  status = HAL_InitTick(uwTickPrio);
 8005fa8:	4b09      	ldr	r3, [pc, #36]	@ (8005fd0 <HAL_RCC_ClockConfig+0x1fc>)
 8005faa:	681b      	ldr	r3, [r3, #0]
 8005fac:	4618      	mov	r0, r3
 8005fae:	f7fe f865 	bl	800407c <HAL_InitTick>
 8005fb2:	4603      	mov	r3, r0
 8005fb4:	72fb      	strb	r3, [r7, #11]

  return status;
 8005fb6:	7afb      	ldrb	r3, [r7, #11]
}
 8005fb8:	4618      	mov	r0, r3
 8005fba:	3710      	adds	r7, #16
 8005fbc:	46bd      	mov	sp, r7
 8005fbe:	bd80      	pop	{r7, pc}
 8005fc0:	40022000 	.word	0x40022000
 8005fc4:	40021000 	.word	0x40021000
 8005fc8:	0800b8f4 	.word	0x0800b8f4
 8005fcc:	20000000 	.word	0x20000000
 8005fd0:	20000004 	.word	0x20000004

08005fd4 <HAL_RCC_GetSysClockFreq>:
  *
  *
  * @retval SYSCLK frequency
  */
uint32_t HAL_RCC_GetSysClockFreq(void)
{
 8005fd4:	b480      	push	{r7}
 8005fd6:	b089      	sub	sp, #36	@ 0x24
 8005fd8:	af00      	add	r7, sp, #0
  uint32_t msirange = 0U, sysclockfreq = 0U;
 8005fda:	2300      	movs	r3, #0
 8005fdc:	61fb      	str	r3, [r7, #28]
 8005fde:	2300      	movs	r3, #0
 8005fe0:	61bb      	str	r3, [r7, #24]
  uint32_t pllvco, pllsource, pllr, pllm;    /* no init needed */
  uint32_t sysclk_source, pll_oscsource;

  sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
 8005fe2:	4b3e      	ldr	r3, [pc, #248]	@ (80060dc <HAL_RCC_GetSysClockFreq+0x108>)
 8005fe4:	689b      	ldr	r3, [r3, #8]
 8005fe6:	f003 030c 	and.w	r3, r3, #12
 8005fea:	613b      	str	r3, [r7, #16]
  pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
 8005fec:	4b3b      	ldr	r3, [pc, #236]	@ (80060dc <HAL_RCC_GetSysClockFreq+0x108>)
 8005fee:	68db      	ldr	r3, [r3, #12]
 8005ff0:	f003 0303 	and.w	r3, r3, #3
 8005ff4:	60fb      	str	r3, [r7, #12]

  if((sysclk_source == RCC_CFGR_SWS_MSI) ||
 8005ff6:	693b      	ldr	r3, [r7, #16]
 8005ff8:	2b00      	cmp	r3, #0
 8005ffa:	d005      	beq.n	8006008 <HAL_RCC_GetSysClockFreq+0x34>
 8005ffc:	693b      	ldr	r3, [r7, #16]
 8005ffe:	2b0c      	cmp	r3, #12
 8006000:	d121      	bne.n	8006046 <HAL_RCC_GetSysClockFreq+0x72>
     ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
 8006002:	68fb      	ldr	r3, [r7, #12]
 8006004:	2b01      	cmp	r3, #1
 8006006:	d11e      	bne.n	8006046 <HAL_RCC_GetSysClockFreq+0x72>
  {
    /* MSI or PLL with MSI source used as system clock source */

    /* Get SYSCLK source */
    if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
 8006008:	4b34      	ldr	r3, [pc, #208]	@ (80060dc <HAL_RCC_GetSysClockFreq+0x108>)
 800600a:	681b      	ldr	r3, [r3, #0]
 800600c:	f003 0308 	and.w	r3, r3, #8
 8006010:	2b00      	cmp	r3, #0
 8006012:	d107      	bne.n	8006024 <HAL_RCC_GetSysClockFreq+0x50>
    { /* MSISRANGE from RCC_CSR applies */
      msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
 8006014:	4b31      	ldr	r3, [pc, #196]	@ (80060dc <HAL_RCC_GetSysClockFreq+0x108>)
 8006016:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
 800601a:	0a1b      	lsrs	r3, r3, #8
 800601c:	f003 030f 	and.w	r3, r3, #15
 8006020:	61fb      	str	r3, [r7, #28]
 8006022:	e005      	b.n	8006030 <HAL_RCC_GetSysClockFreq+0x5c>
    }
    else
    { /* MSIRANGE from RCC_CR applies */
      msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
 8006024:	4b2d      	ldr	r3, [pc, #180]	@ (80060dc <HAL_RCC_GetSysClockFreq+0x108>)
 8006026:	681b      	ldr	r3, [r3, #0]
 8006028:	091b      	lsrs	r3, r3, #4
 800602a:	f003 030f 	and.w	r3, r3, #15
 800602e:	61fb      	str	r3, [r7, #28]
    }
    /*MSI frequency range in HZ*/
    msirange = MSIRangeTable[msirange];
 8006030:	4a2b      	ldr	r2, [pc, #172]	@ (80060e0 <HAL_RCC_GetSysClockFreq+0x10c>)
 8006032:	69fb      	ldr	r3, [r7, #28]
 8006034:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 8006038:	61fb      	str	r3, [r7, #28]

    if(sysclk_source == RCC_CFGR_SWS_MSI)
 800603a:	693b      	ldr	r3, [r7, #16]
 800603c:	2b00      	cmp	r3, #0
 800603e:	d10d      	bne.n	800605c <HAL_RCC_GetSysClockFreq+0x88>
    {
      /* MSI used as system clock source */
      sysclockfreq = msirange;
 8006040:	69fb      	ldr	r3, [r7, #28]
 8006042:	61bb      	str	r3, [r7, #24]
    if(sysclk_source == RCC_CFGR_SWS_MSI)
 8006044:	e00a      	b.n	800605c <HAL_RCC_GetSysClockFreq+0x88>
    }
  }
  else if(sysclk_source == RCC_CFGR_SWS_HSI)
 8006046:	693b      	ldr	r3, [r7, #16]
 8006048:	2b04      	cmp	r3, #4
 800604a:	d102      	bne.n	8006052 <HAL_RCC_GetSysClockFreq+0x7e>
  {
    /* HSI used as system clock source */
    sysclockfreq = HSI_VALUE;
 800604c:	4b25      	ldr	r3, [pc, #148]	@ (80060e4 <HAL_RCC_GetSysClockFreq+0x110>)
 800604e:	61bb      	str	r3, [r7, #24]
 8006050:	e004      	b.n	800605c <HAL_RCC_GetSysClockFreq+0x88>
  }
  else if(sysclk_source == RCC_CFGR_SWS_HSE)
 8006052:	693b      	ldr	r3, [r7, #16]
 8006054:	2b08      	cmp	r3, #8
 8006056:	d101      	bne.n	800605c <HAL_RCC_GetSysClockFreq+0x88>
  {
    /* HSE used as system clock source */
    sysclockfreq = HSE_VALUE;
 8006058:	4b23      	ldr	r3, [pc, #140]	@ (80060e8 <HAL_RCC_GetSysClockFreq+0x114>)
 800605a:	61bb      	str	r3, [r7, #24]
  else
  {
    /* unexpected case: sysclockfreq at 0 */
  }

  if(sysclk_source == RCC_CFGR_SWS_PLL)
 800605c:	693b      	ldr	r3, [r7, #16]
 800605e:	2b0c      	cmp	r3, #12
 8006060:	d134      	bne.n	80060cc <HAL_RCC_GetSysClockFreq+0xf8>
    /* PLL used as system clock  source */

    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
    SYSCLK = PLL_VCO / PLLR
    */
    pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
 8006062:	4b1e      	ldr	r3, [pc, #120]	@ (80060dc <HAL_RCC_GetSysClockFreq+0x108>)
 8006064:	68db      	ldr	r3, [r3, #12]
 8006066:	f003 0303 	and.w	r3, r3, #3
 800606a:	60bb      	str	r3, [r7, #8]

    switch (pllsource)
 800606c:	68bb      	ldr	r3, [r7, #8]
 800606e:	2b02      	cmp	r3, #2
 8006070:	d003      	beq.n	800607a <HAL_RCC_GetSysClockFreq+0xa6>
 8006072:	68bb      	ldr	r3, [r7, #8]
 8006074:	2b03      	cmp	r3, #3
 8006076:	d003      	beq.n	8006080 <HAL_RCC_GetSysClockFreq+0xac>
 8006078:	e005      	b.n	8006086 <HAL_RCC_GetSysClockFreq+0xb2>
    {
    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
      pllvco = HSI_VALUE;
 800607a:	4b1a      	ldr	r3, [pc, #104]	@ (80060e4 <HAL_RCC_GetSysClockFreq+0x110>)
 800607c:	617b      	str	r3, [r7, #20]
      break;
 800607e:	e005      	b.n	800608c <HAL_RCC_GetSysClockFreq+0xb8>

    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
      pllvco = HSE_VALUE;
 8006080:	4b19      	ldr	r3, [pc, #100]	@ (80060e8 <HAL_RCC_GetSysClockFreq+0x114>)
 8006082:	617b      	str	r3, [r7, #20]
      break;
 8006084:	e002      	b.n	800608c <HAL_RCC_GetSysClockFreq+0xb8>

    case RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */
    default:
      pllvco = msirange;
 8006086:	69fb      	ldr	r3, [r7, #28]
 8006088:	617b      	str	r3, [r7, #20]
      break;
 800608a:	bf00      	nop
    }
    pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
 800608c:	4b13      	ldr	r3, [pc, #76]	@ (80060dc <HAL_RCC_GetSysClockFreq+0x108>)
 800608e:	68db      	ldr	r3, [r3, #12]
 8006090:	091b      	lsrs	r3, r3, #4
 8006092:	f003 0307 	and.w	r3, r3, #7
 8006096:	3301      	adds	r3, #1
 8006098:	607b      	str	r3, [r7, #4]
    pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;
 800609a:	4b10      	ldr	r3, [pc, #64]	@ (80060dc <HAL_RCC_GetSysClockFreq+0x108>)
 800609c:	68db      	ldr	r3, [r3, #12]
 800609e:	0a1b      	lsrs	r3, r3, #8
 80060a0:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
 80060a4:	697a      	ldr	r2, [r7, #20]
 80060a6:	fb03 f202 	mul.w	r2, r3, r2
 80060aa:	687b      	ldr	r3, [r7, #4]
 80060ac:	fbb2 f3f3 	udiv	r3, r2, r3
 80060b0:	617b      	str	r3, [r7, #20]
    pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
 80060b2:	4b0a      	ldr	r3, [pc, #40]	@ (80060dc <HAL_RCC_GetSysClockFreq+0x108>)
 80060b4:	68db      	ldr	r3, [r3, #12]
 80060b6:	0e5b      	lsrs	r3, r3, #25
 80060b8:	f003 0303 	and.w	r3, r3, #3
 80060bc:	3301      	adds	r3, #1
 80060be:	005b      	lsls	r3, r3, #1
 80060c0:	603b      	str	r3, [r7, #0]
    sysclockfreq = pllvco / pllr;
 80060c2:	697a      	ldr	r2, [r7, #20]
 80060c4:	683b      	ldr	r3, [r7, #0]
 80060c6:	fbb2 f3f3 	udiv	r3, r2, r3
 80060ca:	61bb      	str	r3, [r7, #24]
  }

  return sysclockfreq;
 80060cc:	69bb      	ldr	r3, [r7, #24]
}
 80060ce:	4618      	mov	r0, r3
 80060d0:	3724      	adds	r7, #36	@ 0x24
 80060d2:	46bd      	mov	sp, r7
 80060d4:	f85d 7b04 	ldr.w	r7, [sp], #4
 80060d8:	4770      	bx	lr
 80060da:	bf00      	nop
 80060dc:	40021000 	.word	0x40021000
 80060e0:	0800b90c 	.word	0x0800b90c
 80060e4:	00f42400 	.word	0x00f42400
 80060e8:	007a1200 	.word	0x007a1200

080060ec <HAL_RCC_GetHCLKFreq>:
  *
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
  * @retval HCLK frequency in Hz
  */
uint32_t HAL_RCC_GetHCLKFreq(void)
{
 80060ec:	b480      	push	{r7}
 80060ee:	af00      	add	r7, sp, #0
  return SystemCoreClock;
 80060f0:	4b03      	ldr	r3, [pc, #12]	@ (8006100 <HAL_RCC_GetHCLKFreq+0x14>)
 80060f2:	681b      	ldr	r3, [r3, #0]
}
 80060f4:	4618      	mov	r0, r3
 80060f6:	46bd      	mov	sp, r7
 80060f8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80060fc:	4770      	bx	lr
 80060fe:	bf00      	nop
 8006100:	20000000 	.word	0x20000000

08006104 <HAL_RCC_GetPCLK1Freq>:
  * @note   Each time PCLK1 changes, this function must be called to update the
  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK1 frequency in Hz
  */
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
 8006104:	b580      	push	{r7, lr}
 8006106:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
 8006108:	f7ff fff0 	bl	80060ec <HAL_RCC_GetHCLKFreq>
 800610c:	4602      	mov	r2, r0
 800610e:	4b06      	ldr	r3, [pc, #24]	@ (8006128 <HAL_RCC_GetPCLK1Freq+0x24>)
 8006110:	689b      	ldr	r3, [r3, #8]
 8006112:	0a1b      	lsrs	r3, r3, #8
 8006114:	f003 0307 	and.w	r3, r3, #7
 8006118:	4904      	ldr	r1, [pc, #16]	@ (800612c <HAL_RCC_GetPCLK1Freq+0x28>)
 800611a:	5ccb      	ldrb	r3, [r1, r3]
 800611c:	f003 031f 	and.w	r3, r3, #31
 8006120:	fa22 f303 	lsr.w	r3, r2, r3
}
 8006124:	4618      	mov	r0, r3
 8006126:	bd80      	pop	{r7, pc}
 8006128:	40021000 	.word	0x40021000
 800612c:	0800b904 	.word	0x0800b904

08006130 <HAL_RCC_GetPCLK2Freq>:
  * @note   Each time PCLK2 changes, this function must be called to update the
  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK2 frequency in Hz
  */
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
 8006130:	b580      	push	{r7, lr}
 8006132:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
 8006134:	f7ff ffda 	bl	80060ec <HAL_RCC_GetHCLKFreq>
 8006138:	4602      	mov	r2, r0
 800613a:	4b06      	ldr	r3, [pc, #24]	@ (8006154 <HAL_RCC_GetPCLK2Freq+0x24>)
 800613c:	689b      	ldr	r3, [r3, #8]
 800613e:	0adb      	lsrs	r3, r3, #11
 8006140:	f003 0307 	and.w	r3, r3, #7
 8006144:	4904      	ldr	r1, [pc, #16]	@ (8006158 <HAL_RCC_GetPCLK2Freq+0x28>)
 8006146:	5ccb      	ldrb	r3, [r1, r3]
 8006148:	f003 031f 	and.w	r3, r3, #31
 800614c:	fa22 f303 	lsr.w	r3, r2, r3
}
 8006150:	4618      	mov	r0, r3
 8006152:	bd80      	pop	{r7, pc}
 8006154:	40021000 	.word	0x40021000
 8006158:	0800b904 	.word	0x0800b904

0800615c <RCC_SetFlashLatencyFromMSIRange>:
            voltage range.
  * @param  msirange  MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
  * @retval HAL status
  */
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
{
 800615c:	b580      	push	{r7, lr}
 800615e:	b086      	sub	sp, #24
 8006160:	af00      	add	r7, sp, #0
 8006162:	6078      	str	r0, [r7, #4]
  uint32_t vos;
  uint32_t latency = FLASH_LATENCY_0;  /* default value 0WS */
 8006164:	2300      	movs	r3, #0
 8006166:	613b      	str	r3, [r7, #16]

  if(__HAL_RCC_PWR_IS_CLK_ENABLED())
 8006168:	4b2a      	ldr	r3, [pc, #168]	@ (8006214 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 800616a:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800616c:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8006170:	2b00      	cmp	r3, #0
 8006172:	d003      	beq.n	800617c <RCC_SetFlashLatencyFromMSIRange+0x20>
  {
    vos = HAL_PWREx_GetVoltageRange();
 8006174:	f7ff f9b6 	bl	80054e4 <HAL_PWREx_GetVoltageRange>
 8006178:	6178      	str	r0, [r7, #20]
 800617a:	e014      	b.n	80061a6 <RCC_SetFlashLatencyFromMSIRange+0x4a>
  }
  else
  {
    __HAL_RCC_PWR_CLK_ENABLE();
 800617c:	4b25      	ldr	r3, [pc, #148]	@ (8006214 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 800617e:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8006180:	4a24      	ldr	r2, [pc, #144]	@ (8006214 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 8006182:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 8006186:	6593      	str	r3, [r2, #88]	@ 0x58
 8006188:	4b22      	ldr	r3, [pc, #136]	@ (8006214 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 800618a:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800618c:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 8006190:	60fb      	str	r3, [r7, #12]
 8006192:	68fb      	ldr	r3, [r7, #12]
    vos = HAL_PWREx_GetVoltageRange();
 8006194:	f7ff f9a6 	bl	80054e4 <HAL_PWREx_GetVoltageRange>
 8006198:	6178      	str	r0, [r7, #20]
    __HAL_RCC_PWR_CLK_DISABLE();
 800619a:	4b1e      	ldr	r3, [pc, #120]	@ (8006214 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 800619c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800619e:	4a1d      	ldr	r2, [pc, #116]	@ (8006214 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 80061a0:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 80061a4:	6593      	str	r3, [r2, #88]	@ 0x58
  }

  if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
 80061a6:	697b      	ldr	r3, [r7, #20]
 80061a8:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 80061ac:	d10b      	bne.n	80061c6 <RCC_SetFlashLatencyFromMSIRange+0x6a>
  {
    if(msirange > RCC_MSIRANGE_8)
 80061ae:	687b      	ldr	r3, [r7, #4]
 80061b0:	2b80      	cmp	r3, #128	@ 0x80
 80061b2:	d919      	bls.n	80061e8 <RCC_SetFlashLatencyFromMSIRange+0x8c>
    {
      /* MSI > 16Mhz */
      if(msirange > RCC_MSIRANGE_10)
 80061b4:	687b      	ldr	r3, [r7, #4]
 80061b6:	2ba0      	cmp	r3, #160	@ 0xa0
 80061b8:	d902      	bls.n	80061c0 <RCC_SetFlashLatencyFromMSIRange+0x64>
      {
        /* MSI 48Mhz */
        latency = FLASH_LATENCY_2; /* 2WS */
 80061ba:	2302      	movs	r3, #2
 80061bc:	613b      	str	r3, [r7, #16]
 80061be:	e013      	b.n	80061e8 <RCC_SetFlashLatencyFromMSIRange+0x8c>
      }
      else
      {
        /* MSI 24Mhz or 32Mhz */
        latency = FLASH_LATENCY_1; /* 1WS */
 80061c0:	2301      	movs	r3, #1
 80061c2:	613b      	str	r3, [r7, #16]
 80061c4:	e010      	b.n	80061e8 <RCC_SetFlashLatencyFromMSIRange+0x8c>
        latency = FLASH_LATENCY_1; /* 1WS */
      }
      /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
    }
#else
    if(msirange > RCC_MSIRANGE_8)
 80061c6:	687b      	ldr	r3, [r7, #4]
 80061c8:	2b80      	cmp	r3, #128	@ 0x80
 80061ca:	d902      	bls.n	80061d2 <RCC_SetFlashLatencyFromMSIRange+0x76>
    {
      /* MSI > 16Mhz */
      latency = FLASH_LATENCY_3; /* 3WS */
 80061cc:	2303      	movs	r3, #3
 80061ce:	613b      	str	r3, [r7, #16]
 80061d0:	e00a      	b.n	80061e8 <RCC_SetFlashLatencyFromMSIRange+0x8c>
    }
    else
    {
      if(msirange == RCC_MSIRANGE_8)
 80061d2:	687b      	ldr	r3, [r7, #4]
 80061d4:	2b80      	cmp	r3, #128	@ 0x80
 80061d6:	d102      	bne.n	80061de <RCC_SetFlashLatencyFromMSIRange+0x82>
      {
        /* MSI 16Mhz */
        latency = FLASH_LATENCY_2; /* 2WS */
 80061d8:	2302      	movs	r3, #2
 80061da:	613b      	str	r3, [r7, #16]
 80061dc:	e004      	b.n	80061e8 <RCC_SetFlashLatencyFromMSIRange+0x8c>
      }
      else if(msirange == RCC_MSIRANGE_7)
 80061de:	687b      	ldr	r3, [r7, #4]
 80061e0:	2b70      	cmp	r3, #112	@ 0x70
 80061e2:	d101      	bne.n	80061e8 <RCC_SetFlashLatencyFromMSIRange+0x8c>
      {
        /* MSI 8Mhz */
        latency = FLASH_LATENCY_1; /* 1WS */
 80061e4:	2301      	movs	r3, #1
 80061e6:	613b      	str	r3, [r7, #16]
      }
    }
#endif
  }

  __HAL_FLASH_SET_LATENCY(latency);
 80061e8:	4b0b      	ldr	r3, [pc, #44]	@ (8006218 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 80061ea:	681b      	ldr	r3, [r3, #0]
 80061ec:	f023 0207 	bic.w	r2, r3, #7
 80061f0:	4909      	ldr	r1, [pc, #36]	@ (8006218 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 80061f2:	693b      	ldr	r3, [r7, #16]
 80061f4:	4313      	orrs	r3, r2
 80061f6:	600b      	str	r3, [r1, #0]

  /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
  if(__HAL_FLASH_GET_LATENCY() != latency)
 80061f8:	4b07      	ldr	r3, [pc, #28]	@ (8006218 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 80061fa:	681b      	ldr	r3, [r3, #0]
 80061fc:	f003 0307 	and.w	r3, r3, #7
 8006200:	693a      	ldr	r2, [r7, #16]
 8006202:	429a      	cmp	r2, r3
 8006204:	d001      	beq.n	800620a <RCC_SetFlashLatencyFromMSIRange+0xae>
  {
    return HAL_ERROR;
 8006206:	2301      	movs	r3, #1
 8006208:	e000      	b.n	800620c <RCC_SetFlashLatencyFromMSIRange+0xb0>
  }

  return HAL_OK;
 800620a:	2300      	movs	r3, #0
}
 800620c:	4618      	mov	r0, r3
 800620e:	3718      	adds	r7, #24
 8006210:	46bd      	mov	sp, r7
 8006212:	bd80      	pop	{r7, pc}
 8006214:	40021000 	.word	0x40021000
 8006218:	40022000 	.word	0x40022000

0800621c <HAL_RCCEx_PeriphCLKConfig>:
  *         the RTC clock source: in this case the access to Backup domain is enabled.
  *
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
{
 800621c:	b580      	push	{r7, lr}
 800621e:	b086      	sub	sp, #24
 8006220:	af00      	add	r7, sp, #0
 8006222:	6078      	str	r0, [r7, #4]
  uint32_t tmpregister, tickstart;     /* no init needed */
  HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
 8006224:	2300      	movs	r3, #0
 8006226:	74fb      	strb	r3, [r7, #19]
  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
 8006228:	2300      	movs	r3, #0
 800622a:	74bb      	strb	r3, [r7, #18]
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));

#if defined(SAI1)

  /*-------------------------- SAI1 clock source configuration ---------------------*/
  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
 800622c:	687b      	ldr	r3, [r7, #4]
 800622e:	681b      	ldr	r3, [r3, #0]
 8006230:	f403 6300 	and.w	r3, r3, #2048	@ 0x800
 8006234:	2b00      	cmp	r3, #0
 8006236:	d031      	beq.n	800629c <HAL_RCCEx_PeriphCLKConfig+0x80>
  {
    /* Check the parameters */
    assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));

    switch(PeriphClkInit->Sai1ClockSelection)
 8006238:	687b      	ldr	r3, [r7, #4]
 800623a:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800623c:	f5b3 0f40 	cmp.w	r3, #12582912	@ 0xc00000
 8006240:	d01a      	beq.n	8006278 <HAL_RCCEx_PeriphCLKConfig+0x5c>
 8006242:	f5b3 0f40 	cmp.w	r3, #12582912	@ 0xc00000
 8006246:	d814      	bhi.n	8006272 <HAL_RCCEx_PeriphCLKConfig+0x56>
 8006248:	2b00      	cmp	r3, #0
 800624a:	d009      	beq.n	8006260 <HAL_RCCEx_PeriphCLKConfig+0x44>
 800624c:	f5b3 0f00 	cmp.w	r3, #8388608	@ 0x800000
 8006250:	d10f      	bne.n	8006272 <HAL_RCCEx_PeriphCLKConfig+0x56>
    case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
      /* Enable SAI Clock output generated from System PLL . */
#if defined(RCC_PLLSAI2_SUPPORT)
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
#else
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
 8006252:	4b5d      	ldr	r3, [pc, #372]	@ (80063c8 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
 8006254:	68db      	ldr	r3, [r3, #12]
 8006256:	4a5c      	ldr	r2, [pc, #368]	@ (80063c8 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
 8006258:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 800625c:	60d3      	str	r3, [r2, #12]
#endif /* RCC_PLLSAI2_SUPPORT */
      /* SAI1 clock source config set later after clock selection check */
      break;
 800625e:	e00c      	b.n	800627a <HAL_RCCEx_PeriphCLKConfig+0x5e>

    case RCC_SAI1CLKSOURCE_PLLSAI1:  /* PLLSAI1 is used as clock source for SAI1*/
      /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
 8006260:	687b      	ldr	r3, [r7, #4]
 8006262:	3304      	adds	r3, #4
 8006264:	2100      	movs	r1, #0
 8006266:	4618      	mov	r0, r3
 8006268:	f000 fa44 	bl	80066f4 <RCCEx_PLLSAI1_Config>
 800626c:	4603      	mov	r3, r0
 800626e:	74fb      	strb	r3, [r7, #19]
      /* SAI1 clock source config set later after clock selection check */
      break;
 8006270:	e003      	b.n	800627a <HAL_RCCEx_PeriphCLKConfig+0x5e>
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
      /* SAI1 clock source config set later after clock selection check */
      break;

    default:
      ret = HAL_ERROR;
 8006272:	2301      	movs	r3, #1
 8006274:	74fb      	strb	r3, [r7, #19]
      break;
 8006276:	e000      	b.n	800627a <HAL_RCCEx_PeriphCLKConfig+0x5e>
      break;
 8006278:	bf00      	nop
    }

    if(ret == HAL_OK)
 800627a:	7cfb      	ldrb	r3, [r7, #19]
 800627c:	2b00      	cmp	r3, #0
 800627e:	d10b      	bne.n	8006298 <HAL_RCCEx_PeriphCLKConfig+0x7c>
    {
      /* Set the source of SAI1 clock*/
      __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
 8006280:	4b51      	ldr	r3, [pc, #324]	@ (80063c8 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
 8006282:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8006286:	f423 0240 	bic.w	r2, r3, #12582912	@ 0xc00000
 800628a:	687b      	ldr	r3, [r7, #4]
 800628c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
 800628e:	494e      	ldr	r1, [pc, #312]	@ (80063c8 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
 8006290:	4313      	orrs	r3, r2
 8006292:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
 8006296:	e001      	b.n	800629c <HAL_RCCEx_PeriphCLKConfig+0x80>
    }
    else
    {
      /* set overall return value */
      status = ret;
 8006298:	7cfb      	ldrb	r3, [r7, #19]
 800629a:	74bb      	strb	r3, [r7, #18]
    }
  }
#endif /* SAI2 */

  /*-------------------------- RTC clock source configuration ----------------------*/
  if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
 800629c:	687b      	ldr	r3, [r7, #4]
 800629e:	681b      	ldr	r3, [r3, #0]
 80062a0:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 80062a4:	2b00      	cmp	r3, #0
 80062a6:	f000 809e 	beq.w	80063e6 <HAL_RCCEx_PeriphCLKConfig+0x1ca>
  {
    FlagStatus       pwrclkchanged = RESET;
 80062aa:	2300      	movs	r3, #0
 80062ac:	747b      	strb	r3, [r7, #17]

    /* Check for RTC Parameters used to output RTCCLK */
    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));

    /* Enable Power Clock */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
 80062ae:	4b46      	ldr	r3, [pc, #280]	@ (80063c8 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
 80062b0:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80062b2:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 80062b6:	2b00      	cmp	r3, #0
 80062b8:	d101      	bne.n	80062be <HAL_RCCEx_PeriphCLKConfig+0xa2>
 80062ba:	2301      	movs	r3, #1
 80062bc:	e000      	b.n	80062c0 <HAL_RCCEx_PeriphCLKConfig+0xa4>
 80062be:	2300      	movs	r3, #0
 80062c0:	2b00      	cmp	r3, #0
 80062c2:	d00d      	beq.n	80062e0 <HAL_RCCEx_PeriphCLKConfig+0xc4>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 80062c4:	4b40      	ldr	r3, [pc, #256]	@ (80063c8 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
 80062c6:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80062c8:	4a3f      	ldr	r2, [pc, #252]	@ (80063c8 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
 80062ca:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
 80062ce:	6593      	str	r3, [r2, #88]	@ 0x58
 80062d0:	4b3d      	ldr	r3, [pc, #244]	@ (80063c8 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
 80062d2:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80062d4:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
 80062d8:	60bb      	str	r3, [r7, #8]
 80062da:	68bb      	ldr	r3, [r7, #8]
      pwrclkchanged = SET;
 80062dc:	2301      	movs	r3, #1
 80062de:	747b      	strb	r3, [r7, #17]
    }

    /* Enable write access to Backup domain */
    SET_BIT(PWR->CR1, PWR_CR1_DBP);
 80062e0:	4b3a      	ldr	r3, [pc, #232]	@ (80063cc <HAL_RCCEx_PeriphCLKConfig+0x1b0>)
 80062e2:	681b      	ldr	r3, [r3, #0]
 80062e4:	4a39      	ldr	r2, [pc, #228]	@ (80063cc <HAL_RCCEx_PeriphCLKConfig+0x1b0>)
 80062e6:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
 80062ea:	6013      	str	r3, [r2, #0]

    /* Wait for Backup domain Write protection disable */
    tickstart = HAL_GetTick();
 80062ec:	f7fd ff16 	bl	800411c <HAL_GetTick>
 80062f0:	60f8      	str	r0, [r7, #12]

    while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
 80062f2:	e009      	b.n	8006308 <HAL_RCCEx_PeriphCLKConfig+0xec>
    {
      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 80062f4:	f7fd ff12 	bl	800411c <HAL_GetTick>
 80062f8:	4602      	mov	r2, r0
 80062fa:	68fb      	ldr	r3, [r7, #12]
 80062fc:	1ad3      	subs	r3, r2, r3
 80062fe:	2b02      	cmp	r3, #2
 8006300:	d902      	bls.n	8006308 <HAL_RCCEx_PeriphCLKConfig+0xec>
      {
        ret = HAL_TIMEOUT;
 8006302:	2303      	movs	r3, #3
 8006304:	74fb      	strb	r3, [r7, #19]
        break;
 8006306:	e005      	b.n	8006314 <HAL_RCCEx_PeriphCLKConfig+0xf8>
    while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
 8006308:	4b30      	ldr	r3, [pc, #192]	@ (80063cc <HAL_RCCEx_PeriphCLKConfig+0x1b0>)
 800630a:	681b      	ldr	r3, [r3, #0]
 800630c:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8006310:	2b00      	cmp	r3, #0
 8006312:	d0ef      	beq.n	80062f4 <HAL_RCCEx_PeriphCLKConfig+0xd8>
      }
    }

    if(ret == HAL_OK)
 8006314:	7cfb      	ldrb	r3, [r7, #19]
 8006316:	2b00      	cmp	r3, #0
 8006318:	d15a      	bne.n	80063d0 <HAL_RCCEx_PeriphCLKConfig+0x1b4>
    {
      /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
      tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
 800631a:	4b2b      	ldr	r3, [pc, #172]	@ (80063c8 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
 800631c:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8006320:	f403 7340 	and.w	r3, r3, #768	@ 0x300
 8006324:	617b      	str	r3, [r7, #20]

      if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
 8006326:	697b      	ldr	r3, [r7, #20]
 8006328:	2b00      	cmp	r3, #0
 800632a:	d01e      	beq.n	800636a <HAL_RCCEx_PeriphCLKConfig+0x14e>
 800632c:	687b      	ldr	r3, [r7, #4]
 800632e:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 8006330:	697a      	ldr	r2, [r7, #20]
 8006332:	429a      	cmp	r2, r3
 8006334:	d019      	beq.n	800636a <HAL_RCCEx_PeriphCLKConfig+0x14e>
      {
        /* Store the content of BDCR register before the reset of Backup Domain */
        tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
 8006336:	4b24      	ldr	r3, [pc, #144]	@ (80063c8 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
 8006338:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800633c:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
 8006340:	617b      	str	r3, [r7, #20]
        /* RTC Clock selection can be changed only if the Backup Domain is reset */
        __HAL_RCC_BACKUPRESET_FORCE();
 8006342:	4b21      	ldr	r3, [pc, #132]	@ (80063c8 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
 8006344:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8006348:	4a1f      	ldr	r2, [pc, #124]	@ (80063c8 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
 800634a:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
 800634e:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
        __HAL_RCC_BACKUPRESET_RELEASE();
 8006352:	4b1d      	ldr	r3, [pc, #116]	@ (80063c8 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
 8006354:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 8006358:	4a1b      	ldr	r2, [pc, #108]	@ (80063c8 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
 800635a:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
 800635e:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
        /* Restore the Content of BDCR register */
        RCC->BDCR = tmpregister;
 8006362:	4a19      	ldr	r2, [pc, #100]	@ (80063c8 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
 8006364:	697b      	ldr	r3, [r7, #20]
 8006366:	f8c2 3090 	str.w	r3, [r2, #144]	@ 0x90
      }

      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
      if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
 800636a:	697b      	ldr	r3, [r7, #20]
 800636c:	f003 0301 	and.w	r3, r3, #1
 8006370:	2b00      	cmp	r3, #0
 8006372:	d016      	beq.n	80063a2 <HAL_RCCEx_PeriphCLKConfig+0x186>
      {
        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8006374:	f7fd fed2 	bl	800411c <HAL_GetTick>
 8006378:	60f8      	str	r0, [r7, #12]

        /* Wait till LSE is ready */
        while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 800637a:	e00b      	b.n	8006394 <HAL_RCCEx_PeriphCLKConfig+0x178>
        {
          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 800637c:	f7fd fece 	bl	800411c <HAL_GetTick>
 8006380:	4602      	mov	r2, r0
 8006382:	68fb      	ldr	r3, [r7, #12]
 8006384:	1ad3      	subs	r3, r2, r3
 8006386:	f241 3288 	movw	r2, #5000	@ 0x1388
 800638a:	4293      	cmp	r3, r2
 800638c:	d902      	bls.n	8006394 <HAL_RCCEx_PeriphCLKConfig+0x178>
          {
            ret = HAL_TIMEOUT;
 800638e:	2303      	movs	r3, #3
 8006390:	74fb      	strb	r3, [r7, #19]
            break;
 8006392:	e006      	b.n	80063a2 <HAL_RCCEx_PeriphCLKConfig+0x186>
        while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
 8006394:	4b0c      	ldr	r3, [pc, #48]	@ (80063c8 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
 8006396:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 800639a:	f003 0302 	and.w	r3, r3, #2
 800639e:	2b00      	cmp	r3, #0
 80063a0:	d0ec      	beq.n	800637c <HAL_RCCEx_PeriphCLKConfig+0x160>
          }
        }
      }

      if(ret == HAL_OK)
 80063a2:	7cfb      	ldrb	r3, [r7, #19]
 80063a4:	2b00      	cmp	r3, #0
 80063a6:	d10b      	bne.n	80063c0 <HAL_RCCEx_PeriphCLKConfig+0x1a4>
      {
        /* Apply new RTC clock source selection */
        __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
 80063a8:	4b07      	ldr	r3, [pc, #28]	@ (80063c8 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
 80063aa:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
 80063ae:	f423 7240 	bic.w	r2, r3, #768	@ 0x300
 80063b2:	687b      	ldr	r3, [r7, #4]
 80063b4:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
 80063b6:	4904      	ldr	r1, [pc, #16]	@ (80063c8 <HAL_RCCEx_PeriphCLKConfig+0x1ac>)
 80063b8:	4313      	orrs	r3, r2
 80063ba:	f8c1 3090 	str.w	r3, [r1, #144]	@ 0x90
 80063be:	e009      	b.n	80063d4 <HAL_RCCEx_PeriphCLKConfig+0x1b8>
      }
      else
      {
        /* set overall return value */
        status = ret;
 80063c0:	7cfb      	ldrb	r3, [r7, #19]
 80063c2:	74bb      	strb	r3, [r7, #18]
 80063c4:	e006      	b.n	80063d4 <HAL_RCCEx_PeriphCLKConfig+0x1b8>
 80063c6:	bf00      	nop
 80063c8:	40021000 	.word	0x40021000
 80063cc:	40007000 	.word	0x40007000
      }
    }
    else
    {
      /* set overall return value */
      status = ret;
 80063d0:	7cfb      	ldrb	r3, [r7, #19]
 80063d2:	74bb      	strb	r3, [r7, #18]
    }

    /* Restore clock configuration if changed */
    if(pwrclkchanged == SET)
 80063d4:	7c7b      	ldrb	r3, [r7, #17]
 80063d6:	2b01      	cmp	r3, #1
 80063d8:	d105      	bne.n	80063e6 <HAL_RCCEx_PeriphCLKConfig+0x1ca>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 80063da:	4b9e      	ldr	r3, [pc, #632]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 80063dc:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 80063de:	4a9d      	ldr	r2, [pc, #628]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 80063e0:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
 80063e4:	6593      	str	r3, [r2, #88]	@ 0x58
    }
  }

  /*-------------------------- USART1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
 80063e6:	687b      	ldr	r3, [r7, #4]
 80063e8:	681b      	ldr	r3, [r3, #0]
 80063ea:	f003 0301 	and.w	r3, r3, #1
 80063ee:	2b00      	cmp	r3, #0
 80063f0:	d00a      	beq.n	8006408 <HAL_RCCEx_PeriphCLKConfig+0x1ec>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));

    /* Configure the USART1 clock source */
    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
 80063f2:	4b98      	ldr	r3, [pc, #608]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 80063f4:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80063f8:	f023 0203 	bic.w	r2, r3, #3
 80063fc:	687b      	ldr	r3, [r7, #4]
 80063fe:	6a1b      	ldr	r3, [r3, #32]
 8006400:	4994      	ldr	r1, [pc, #592]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 8006402:	4313      	orrs	r3, r2
 8006404:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

  /*-------------------------- USART2 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
 8006408:	687b      	ldr	r3, [r7, #4]
 800640a:	681b      	ldr	r3, [r3, #0]
 800640c:	f003 0302 	and.w	r3, r3, #2
 8006410:	2b00      	cmp	r3, #0
 8006412:	d00a      	beq.n	800642a <HAL_RCCEx_PeriphCLKConfig+0x20e>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));

    /* Configure the USART2 clock source */
    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
 8006414:	4b8f      	ldr	r3, [pc, #572]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 8006416:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800641a:	f023 020c 	bic.w	r2, r3, #12
 800641e:	687b      	ldr	r3, [r7, #4]
 8006420:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8006422:	498c      	ldr	r1, [pc, #560]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 8006424:	4313      	orrs	r3, r2
 8006426:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

#if defined(USART3)

  /*-------------------------- USART3 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
 800642a:	687b      	ldr	r3, [r7, #4]
 800642c:	681b      	ldr	r3, [r3, #0]
 800642e:	f003 0304 	and.w	r3, r3, #4
 8006432:	2b00      	cmp	r3, #0
 8006434:	d00a      	beq.n	800644c <HAL_RCCEx_PeriphCLKConfig+0x230>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));

    /* Configure the USART3 clock source */
    __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
 8006436:	4b87      	ldr	r3, [pc, #540]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 8006438:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800643c:	f023 0230 	bic.w	r2, r3, #48	@ 0x30
 8006440:	687b      	ldr	r3, [r7, #4]
 8006442:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
 8006444:	4983      	ldr	r1, [pc, #524]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 8006446:	4313      	orrs	r3, r2
 8006448:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
#endif /* USART3 */

#if defined(UART4)

  /*-------------------------- UART4 clock source configuration --------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
 800644c:	687b      	ldr	r3, [r7, #4]
 800644e:	681b      	ldr	r3, [r3, #0]
 8006450:	f003 0308 	and.w	r3, r3, #8
 8006454:	2b00      	cmp	r3, #0
 8006456:	d00a      	beq.n	800646e <HAL_RCCEx_PeriphCLKConfig+0x252>
  {
    /* Check the parameters */
    assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));

    /* Configure the UART4 clock source */
    __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
 8006458:	4b7e      	ldr	r3, [pc, #504]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 800645a:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800645e:	f023 02c0 	bic.w	r2, r3, #192	@ 0xc0
 8006462:	687b      	ldr	r3, [r7, #4]
 8006464:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
 8006466:	497b      	ldr	r1, [pc, #492]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 8006468:	4313      	orrs	r3, r2
 800646a:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

#endif /* UART5 */

  /*-------------------------- LPUART1 clock source configuration ------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
 800646e:	687b      	ldr	r3, [r7, #4]
 8006470:	681b      	ldr	r3, [r3, #0]
 8006472:	f003 0320 	and.w	r3, r3, #32
 8006476:	2b00      	cmp	r3, #0
 8006478:	d00a      	beq.n	8006490 <HAL_RCCEx_PeriphCLKConfig+0x274>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));

    /* Configure the LPUART1 clock source */
    __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
 800647a:	4b76      	ldr	r3, [pc, #472]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 800647c:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8006480:	f423 6240 	bic.w	r2, r3, #3072	@ 0xc00
 8006484:	687b      	ldr	r3, [r7, #4]
 8006486:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
 8006488:	4972      	ldr	r1, [pc, #456]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 800648a:	4313      	orrs	r3, r2
 800648c:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

  /*-------------------------- LPTIM1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
 8006490:	687b      	ldr	r3, [r7, #4]
 8006492:	681b      	ldr	r3, [r3, #0]
 8006494:	f403 7300 	and.w	r3, r3, #512	@ 0x200
 8006498:	2b00      	cmp	r3, #0
 800649a:	d00a      	beq.n	80064b2 <HAL_RCCEx_PeriphCLKConfig+0x296>
  {
    assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
 800649c:	4b6d      	ldr	r3, [pc, #436]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 800649e:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80064a2:	f423 2240 	bic.w	r2, r3, #786432	@ 0xc0000
 80064a6:	687b      	ldr	r3, [r7, #4]
 80064a8:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
 80064aa:	496a      	ldr	r1, [pc, #424]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 80064ac:	4313      	orrs	r3, r2
 80064ae:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

  /*-------------------------- LPTIM2 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
 80064b2:	687b      	ldr	r3, [r7, #4]
 80064b4:	681b      	ldr	r3, [r3, #0]
 80064b6:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 80064ba:	2b00      	cmp	r3, #0
 80064bc:	d00a      	beq.n	80064d4 <HAL_RCCEx_PeriphCLKConfig+0x2b8>
  {
    assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
    __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
 80064be:	4b65      	ldr	r3, [pc, #404]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 80064c0:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80064c4:	f423 1240 	bic.w	r2, r3, #3145728	@ 0x300000
 80064c8:	687b      	ldr	r3, [r7, #4]
 80064ca:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
 80064cc:	4961      	ldr	r1, [pc, #388]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 80064ce:	4313      	orrs	r3, r2
 80064d0:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

  /*-------------------------- I2C1 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
 80064d4:	687b      	ldr	r3, [r7, #4]
 80064d6:	681b      	ldr	r3, [r3, #0]
 80064d8:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 80064dc:	2b00      	cmp	r3, #0
 80064de:	d00a      	beq.n	80064f6 <HAL_RCCEx_PeriphCLKConfig+0x2da>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));

    /* Configure the I2C1 clock source */
    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
 80064e0:	4b5c      	ldr	r3, [pc, #368]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 80064e2:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80064e6:	f423 5240 	bic.w	r2, r3, #12288	@ 0x3000
 80064ea:	687b      	ldr	r3, [r7, #4]
 80064ec:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
 80064ee:	4959      	ldr	r1, [pc, #356]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 80064f0:	4313      	orrs	r3, r2
 80064f2:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

#if defined(I2C2)

  /*-------------------------- I2C2 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
 80064f6:	687b      	ldr	r3, [r7, #4]
 80064f8:	681b      	ldr	r3, [r3, #0]
 80064fa:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 80064fe:	2b00      	cmp	r3, #0
 8006500:	d00a      	beq.n	8006518 <HAL_RCCEx_PeriphCLKConfig+0x2fc>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));

    /* Configure the I2C2 clock source */
    __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
 8006502:	4b54      	ldr	r3, [pc, #336]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 8006504:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8006508:	f423 4240 	bic.w	r2, r3, #49152	@ 0xc000
 800650c:	687b      	ldr	r3, [r7, #4]
 800650e:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
 8006510:	4950      	ldr	r1, [pc, #320]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 8006512:	4313      	orrs	r3, r2
 8006514:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

#endif /* I2C2 */

  /*-------------------------- I2C3 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
 8006518:	687b      	ldr	r3, [r7, #4]
 800651a:	681b      	ldr	r3, [r3, #0]
 800651c:	f403 7380 	and.w	r3, r3, #256	@ 0x100
 8006520:	2b00      	cmp	r3, #0
 8006522:	d00a      	beq.n	800653a <HAL_RCCEx_PeriphCLKConfig+0x31e>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));

    /* Configure the I2C3 clock source */
    __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
 8006524:	4b4b      	ldr	r3, [pc, #300]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 8006526:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800652a:	f423 3240 	bic.w	r2, r3, #196608	@ 0x30000
 800652e:	687b      	ldr	r3, [r7, #4]
 8006530:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
 8006532:	4948      	ldr	r1, [pc, #288]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 8006534:	4313      	orrs	r3, r2
 8006536:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
  }

#if defined(I2C4)

  /*-------------------------- I2C4 clock source configuration ---------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
 800653a:	687b      	ldr	r3, [r7, #4]
 800653c:	681b      	ldr	r3, [r3, #0]
 800653e:	f403 1380 	and.w	r3, r3, #1048576	@ 0x100000
 8006542:	2b00      	cmp	r3, #0
 8006544:	d00a      	beq.n	800655c <HAL_RCCEx_PeriphCLKConfig+0x340>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));

    /* Configure the I2C4 clock source */
    __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
 8006546:	4b43      	ldr	r3, [pc, #268]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 8006548:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
 800654c:	f023 0203 	bic.w	r2, r3, #3
 8006550:	687b      	ldr	r3, [r7, #4]
 8006552:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 8006554:	493f      	ldr	r1, [pc, #252]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 8006556:	4313      	orrs	r3, r2
 8006558:	f8c1 309c 	str.w	r3, [r1, #156]	@ 0x9c
#endif /* I2C4 */

#if defined(USB_OTG_FS) || defined(USB)

  /*-------------------------- USB clock source configuration ----------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
 800655c:	687b      	ldr	r3, [r7, #4]
 800655e:	681b      	ldr	r3, [r3, #0]
 8006560:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
 8006564:	2b00      	cmp	r3, #0
 8006566:	d028      	beq.n	80065ba <HAL_RCCEx_PeriphCLKConfig+0x39e>
  {
    assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 8006568:	4b3a      	ldr	r3, [pc, #232]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 800656a:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800656e:	f023 6240 	bic.w	r2, r3, #201326592	@ 0xc000000
 8006572:	687b      	ldr	r3, [r7, #4]
 8006574:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8006576:	4937      	ldr	r1, [pc, #220]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 8006578:	4313      	orrs	r3, r2
 800657a:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88

    if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
 800657e:	687b      	ldr	r3, [r7, #4]
 8006580:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 8006582:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 8006586:	d106      	bne.n	8006596 <HAL_RCCEx_PeriphCLKConfig+0x37a>
    {
      /* Enable PLL48M1CLK output clock */
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
 8006588:	4b32      	ldr	r3, [pc, #200]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 800658a:	68db      	ldr	r3, [r3, #12]
 800658c:	4a31      	ldr	r2, [pc, #196]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 800658e:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
 8006592:	60d3      	str	r3, [r2, #12]
 8006594:	e011      	b.n	80065ba <HAL_RCCEx_PeriphCLKConfig+0x39e>
    }
    else
    {
#if defined(RCC_PLLSAI1_SUPPORT)
      if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
 8006596:	687b      	ldr	r3, [r7, #4]
 8006598:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
 800659a:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
 800659e:	d10c      	bne.n	80065ba <HAL_RCCEx_PeriphCLKConfig+0x39e>
      {
        /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
        ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
 80065a0:	687b      	ldr	r3, [r7, #4]
 80065a2:	3304      	adds	r3, #4
 80065a4:	2101      	movs	r1, #1
 80065a6:	4618      	mov	r0, r3
 80065a8:	f000 f8a4 	bl	80066f4 <RCCEx_PLLSAI1_Config>
 80065ac:	4603      	mov	r3, r0
 80065ae:	74fb      	strb	r3, [r7, #19]

        if(ret != HAL_OK)
 80065b0:	7cfb      	ldrb	r3, [r7, #19]
 80065b2:	2b00      	cmp	r3, #0
 80065b4:	d001      	beq.n	80065ba <HAL_RCCEx_PeriphCLKConfig+0x39e>
        {
          /* set overall return value */
          status = ret;
 80065b6:	7cfb      	ldrb	r3, [r7, #19]
 80065b8:	74bb      	strb	r3, [r7, #18]
#endif /* USB_OTG_FS || USB */

#if defined(SDMMC1)

  /*-------------------------- SDMMC1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
 80065ba:	687b      	ldr	r3, [r7, #4]
 80065bc:	681b      	ldr	r3, [r3, #0]
 80065be:	f403 2300 	and.w	r3, r3, #524288	@ 0x80000
 80065c2:	2b00      	cmp	r3, #0
 80065c4:	d028      	beq.n	8006618 <HAL_RCCEx_PeriphCLKConfig+0x3fc>
  {
    assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
    __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
 80065c6:	4b23      	ldr	r3, [pc, #140]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 80065c8:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80065cc:	f023 6240 	bic.w	r2, r3, #201326592	@ 0xc000000
 80065d0:	687b      	ldr	r3, [r7, #4]
 80065d2:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80065d4:	491f      	ldr	r1, [pc, #124]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 80065d6:	4313      	orrs	r3, r2
 80065d8:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88

    if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL)   /* PLL "Q" ? */
 80065dc:	687b      	ldr	r3, [r7, #4]
 80065de:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80065e0:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 80065e4:	d106      	bne.n	80065f4 <HAL_RCCEx_PeriphCLKConfig+0x3d8>
    {
      /* Enable PLL48M1CLK output clock */
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
 80065e6:	4b1b      	ldr	r3, [pc, #108]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 80065e8:	68db      	ldr	r3, [r3, #12]
 80065ea:	4a1a      	ldr	r2, [pc, #104]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 80065ec:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
 80065f0:	60d3      	str	r3, [r2, #12]
 80065f2:	e011      	b.n	8006618 <HAL_RCCEx_PeriphCLKConfig+0x3fc>
    {
      /* Enable PLLSAI3CLK output */
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
    }
#endif
    else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
 80065f4:	687b      	ldr	r3, [r7, #4]
 80065f6:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
 80065f8:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
 80065fc:	d10c      	bne.n	8006618 <HAL_RCCEx_PeriphCLKConfig+0x3fc>
    {
      /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
 80065fe:	687b      	ldr	r3, [r7, #4]
 8006600:	3304      	adds	r3, #4
 8006602:	2101      	movs	r1, #1
 8006604:	4618      	mov	r0, r3
 8006606:	f000 f875 	bl	80066f4 <RCCEx_PLLSAI1_Config>
 800660a:	4603      	mov	r3, r0
 800660c:	74fb      	strb	r3, [r7, #19]

      if(ret != HAL_OK)
 800660e:	7cfb      	ldrb	r3, [r7, #19]
 8006610:	2b00      	cmp	r3, #0
 8006612:	d001      	beq.n	8006618 <HAL_RCCEx_PeriphCLKConfig+0x3fc>
      {
        /* set overall return value */
        status = ret;
 8006614:	7cfb      	ldrb	r3, [r7, #19]
 8006616:	74bb      	strb	r3, [r7, #18]
  }

#endif /* SDMMC1 */

  /*-------------------------- RNG clock source configuration ----------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
 8006618:	687b      	ldr	r3, [r7, #4]
 800661a:	681b      	ldr	r3, [r3, #0]
 800661c:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
 8006620:	2b00      	cmp	r3, #0
 8006622:	d02b      	beq.n	800667c <HAL_RCCEx_PeriphCLKConfig+0x460>
  {
    assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
    __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
 8006624:	4b0b      	ldr	r3, [pc, #44]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 8006626:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800662a:	f023 6240 	bic.w	r2, r3, #201326592	@ 0xc000000
 800662e:	687b      	ldr	r3, [r7, #4]
 8006630:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 8006632:	4908      	ldr	r1, [pc, #32]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 8006634:	4313      	orrs	r3, r2
 8006636:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88

    if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
 800663a:	687b      	ldr	r3, [r7, #4]
 800663c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800663e:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
 8006642:	d109      	bne.n	8006658 <HAL_RCCEx_PeriphCLKConfig+0x43c>
    {
      /* Enable PLL48M1CLK output clock */
      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
 8006644:	4b03      	ldr	r3, [pc, #12]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 8006646:	68db      	ldr	r3, [r3, #12]
 8006648:	4a02      	ldr	r2, [pc, #8]	@ (8006654 <HAL_RCCEx_PeriphCLKConfig+0x438>)
 800664a:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
 800664e:	60d3      	str	r3, [r2, #12]
 8006650:	e014      	b.n	800667c <HAL_RCCEx_PeriphCLKConfig+0x460>
 8006652:	bf00      	nop
 8006654:	40021000 	.word	0x40021000
    }
#if defined(RCC_PLLSAI1_SUPPORT)
    else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
 8006658:	687b      	ldr	r3, [r7, #4]
 800665a:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
 800665c:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
 8006660:	d10c      	bne.n	800667c <HAL_RCCEx_PeriphCLKConfig+0x460>
    {
      /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
 8006662:	687b      	ldr	r3, [r7, #4]
 8006664:	3304      	adds	r3, #4
 8006666:	2101      	movs	r1, #1
 8006668:	4618      	mov	r0, r3
 800666a:	f000 f843 	bl	80066f4 <RCCEx_PLLSAI1_Config>
 800666e:	4603      	mov	r3, r0
 8006670:	74fb      	strb	r3, [r7, #19]

      if(ret != HAL_OK)
 8006672:	7cfb      	ldrb	r3, [r7, #19]
 8006674:	2b00      	cmp	r3, #0
 8006676:	d001      	beq.n	800667c <HAL_RCCEx_PeriphCLKConfig+0x460>
      {
        /* set overall return value */
        status = ret;
 8006678:	7cfb      	ldrb	r3, [r7, #19]
 800667a:	74bb      	strb	r3, [r7, #18]
    }
  }

  /*-------------------------- ADC clock source configuration ----------------------*/
#if !defined(STM32L412xx) && !defined(STM32L422xx)
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
 800667c:	687b      	ldr	r3, [r7, #4]
 800667e:	681b      	ldr	r3, [r3, #0]
 8006680:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
 8006684:	2b00      	cmp	r3, #0
 8006686:	d01c      	beq.n	80066c2 <HAL_RCCEx_PeriphCLKConfig+0x4a6>
  {
    /* Check the parameters */
    assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));

    /* Configure the ADC interface clock source */
    __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
 8006688:	4b19      	ldr	r3, [pc, #100]	@ (80066f0 <HAL_RCCEx_PeriphCLKConfig+0x4d4>)
 800668a:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 800668e:	f023 5240 	bic.w	r2, r3, #805306368	@ 0x30000000
 8006692:	687b      	ldr	r3, [r7, #4]
 8006694:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 8006696:	4916      	ldr	r1, [pc, #88]	@ (80066f0 <HAL_RCCEx_PeriphCLKConfig+0x4d4>)
 8006698:	4313      	orrs	r3, r2
 800669a:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88

#if defined(RCC_PLLSAI1_SUPPORT)
    if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
 800669e:	687b      	ldr	r3, [r7, #4]
 80066a0:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
 80066a2:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 80066a6:	d10c      	bne.n	80066c2 <HAL_RCCEx_PeriphCLKConfig+0x4a6>
    {
      /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
      ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
 80066a8:	687b      	ldr	r3, [r7, #4]
 80066aa:	3304      	adds	r3, #4
 80066ac:	2102      	movs	r1, #2
 80066ae:	4618      	mov	r0, r3
 80066b0:	f000 f820 	bl	80066f4 <RCCEx_PLLSAI1_Config>
 80066b4:	4603      	mov	r3, r0
 80066b6:	74fb      	strb	r3, [r7, #19]

      if(ret != HAL_OK)
 80066b8:	7cfb      	ldrb	r3, [r7, #19]
 80066ba:	2b00      	cmp	r3, #0
 80066bc:	d001      	beq.n	80066c2 <HAL_RCCEx_PeriphCLKConfig+0x4a6>
      {
        /* set overall return value */
        status = ret;
 80066be:	7cfb      	ldrb	r3, [r7, #19]
 80066c0:	74bb      	strb	r3, [r7, #18]
#endif /* SWPMI1 */

#if defined(DFSDM1_Filter0)

  /*-------------------------- DFSDM1 clock source configuration -------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
 80066c2:	687b      	ldr	r3, [r7, #4]
 80066c4:	681b      	ldr	r3, [r3, #0]
 80066c6:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
 80066ca:	2b00      	cmp	r3, #0
 80066cc:	d00a      	beq.n	80066e4 <HAL_RCCEx_PeriphCLKConfig+0x4c8>
  {
    /* Check the parameters */
    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));

    /* Configure the DFSDM1 interface clock source */
    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
 80066ce:	4b08      	ldr	r3, [pc, #32]	@ (80066f0 <HAL_RCCEx_PeriphCLKConfig+0x4d4>)
 80066d0:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 80066d4:	f023 4200 	bic.w	r2, r3, #2147483648	@ 0x80000000
 80066d8:	687b      	ldr	r3, [r7, #4]
 80066da:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 80066dc:	4904      	ldr	r1, [pc, #16]	@ (80066f0 <HAL_RCCEx_PeriphCLKConfig+0x4d4>)
 80066de:	4313      	orrs	r3, r2
 80066e0:	f8c1 3088 	str.w	r3, [r1, #136]	@ 0x88
    }
  }

#endif /* OCTOSPI1 || OCTOSPI2 */

  return status;
 80066e4:	7cbb      	ldrb	r3, [r7, #18]
}
 80066e6:	4618      	mov	r0, r3
 80066e8:	3718      	adds	r7, #24
 80066ea:	46bd      	mov	sp, r7
 80066ec:	bd80      	pop	{r7, pc}
 80066ee:	bf00      	nop
 80066f0:	40021000 	.word	0x40021000

080066f4 <RCCEx_PLLSAI1_Config>:
  * @note   PLLSAI1 is temporary disable to apply new parameters
  *
  * @retval HAL status
  */
static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
{
 80066f4:	b580      	push	{r7, lr}
 80066f6:	b084      	sub	sp, #16
 80066f8:	af00      	add	r7, sp, #0
 80066fa:	6078      	str	r0, [r7, #4]
 80066fc:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;
  HAL_StatusTypeDef status = HAL_OK;
 80066fe:	2300      	movs	r3, #0
 8006700:	73fb      	strb	r3, [r7, #15]
  assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
  assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
  assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));

  /* Check that PLLSAI1 clock source and divider M can be applied */
  if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
 8006702:	4b74      	ldr	r3, [pc, #464]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 8006704:	68db      	ldr	r3, [r3, #12]
 8006706:	f003 0303 	and.w	r3, r3, #3
 800670a:	2b00      	cmp	r3, #0
 800670c:	d018      	beq.n	8006740 <RCCEx_PLLSAI1_Config+0x4c>
  {
    /* PLL clock source and divider M already set, check that no request for change  */
    if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
 800670e:	4b71      	ldr	r3, [pc, #452]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 8006710:	68db      	ldr	r3, [r3, #12]
 8006712:	f003 0203 	and.w	r2, r3, #3
 8006716:	687b      	ldr	r3, [r7, #4]
 8006718:	681b      	ldr	r3, [r3, #0]
 800671a:	429a      	cmp	r2, r3
 800671c:	d10d      	bne.n	800673a <RCCEx_PLLSAI1_Config+0x46>
       ||
       (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
 800671e:	687b      	ldr	r3, [r7, #4]
 8006720:	681b      	ldr	r3, [r3, #0]
       ||
 8006722:	2b00      	cmp	r3, #0
 8006724:	d009      	beq.n	800673a <RCCEx_PLLSAI1_Config+0x46>
#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
       ||
       (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)
 8006726:	4b6b      	ldr	r3, [pc, #428]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 8006728:	68db      	ldr	r3, [r3, #12]
 800672a:	091b      	lsrs	r3, r3, #4
 800672c:	f003 0307 	and.w	r3, r3, #7
 8006730:	1c5a      	adds	r2, r3, #1
 8006732:	687b      	ldr	r3, [r7, #4]
 8006734:	685b      	ldr	r3, [r3, #4]
       ||
 8006736:	429a      	cmp	r2, r3
 8006738:	d047      	beq.n	80067ca <RCCEx_PLLSAI1_Config+0xd6>
#endif
      )
    {
      status = HAL_ERROR;
 800673a:	2301      	movs	r3, #1
 800673c:	73fb      	strb	r3, [r7, #15]
 800673e:	e044      	b.n	80067ca <RCCEx_PLLSAI1_Config+0xd6>
    }
  }
  else
  {
    /* Check PLLSAI1 clock source availability */
    switch(PllSai1->PLLSAI1Source)
 8006740:	687b      	ldr	r3, [r7, #4]
 8006742:	681b      	ldr	r3, [r3, #0]
 8006744:	2b03      	cmp	r3, #3
 8006746:	d018      	beq.n	800677a <RCCEx_PLLSAI1_Config+0x86>
 8006748:	2b03      	cmp	r3, #3
 800674a:	d825      	bhi.n	8006798 <RCCEx_PLLSAI1_Config+0xa4>
 800674c:	2b01      	cmp	r3, #1
 800674e:	d002      	beq.n	8006756 <RCCEx_PLLSAI1_Config+0x62>
 8006750:	2b02      	cmp	r3, #2
 8006752:	d009      	beq.n	8006768 <RCCEx_PLLSAI1_Config+0x74>
 8006754:	e020      	b.n	8006798 <RCCEx_PLLSAI1_Config+0xa4>
    {
    case RCC_PLLSOURCE_MSI:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
 8006756:	4b5f      	ldr	r3, [pc, #380]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 8006758:	681b      	ldr	r3, [r3, #0]
 800675a:	f003 0302 	and.w	r3, r3, #2
 800675e:	2b00      	cmp	r3, #0
 8006760:	d11d      	bne.n	800679e <RCCEx_PLLSAI1_Config+0xaa>
      {
        status = HAL_ERROR;
 8006762:	2301      	movs	r3, #1
 8006764:	73fb      	strb	r3, [r7, #15]
      }
      break;
 8006766:	e01a      	b.n	800679e <RCCEx_PLLSAI1_Config+0xaa>
    case RCC_PLLSOURCE_HSI:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
 8006768:	4b5a      	ldr	r3, [pc, #360]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 800676a:	681b      	ldr	r3, [r3, #0]
 800676c:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
 8006770:	2b00      	cmp	r3, #0
 8006772:	d116      	bne.n	80067a2 <RCCEx_PLLSAI1_Config+0xae>
      {
        status = HAL_ERROR;
 8006774:	2301      	movs	r3, #1
 8006776:	73fb      	strb	r3, [r7, #15]
      }
      break;
 8006778:	e013      	b.n	80067a2 <RCCEx_PLLSAI1_Config+0xae>
    case RCC_PLLSOURCE_HSE:
      if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
 800677a:	4b56      	ldr	r3, [pc, #344]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 800677c:	681b      	ldr	r3, [r3, #0]
 800677e:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
 8006782:	2b00      	cmp	r3, #0
 8006784:	d10f      	bne.n	80067a6 <RCCEx_PLLSAI1_Config+0xb2>
      {
        if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
 8006786:	4b53      	ldr	r3, [pc, #332]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 8006788:	681b      	ldr	r3, [r3, #0]
 800678a:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
 800678e:	2b00      	cmp	r3, #0
 8006790:	d109      	bne.n	80067a6 <RCCEx_PLLSAI1_Config+0xb2>
        {
          status = HAL_ERROR;
 8006792:	2301      	movs	r3, #1
 8006794:	73fb      	strb	r3, [r7, #15]
        }
      }
      break;
 8006796:	e006      	b.n	80067a6 <RCCEx_PLLSAI1_Config+0xb2>
    default:
      status = HAL_ERROR;
 8006798:	2301      	movs	r3, #1
 800679a:	73fb      	strb	r3, [r7, #15]
      break;
 800679c:	e004      	b.n	80067a8 <RCCEx_PLLSAI1_Config+0xb4>
      break;
 800679e:	bf00      	nop
 80067a0:	e002      	b.n	80067a8 <RCCEx_PLLSAI1_Config+0xb4>
      break;
 80067a2:	bf00      	nop
 80067a4:	e000      	b.n	80067a8 <RCCEx_PLLSAI1_Config+0xb4>
      break;
 80067a6:	bf00      	nop
    }

    if(status == HAL_OK)
 80067a8:	7bfb      	ldrb	r3, [r7, #15]
 80067aa:	2b00      	cmp	r3, #0
 80067ac:	d10d      	bne.n	80067ca <RCCEx_PLLSAI1_Config+0xd6>
#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
      /* Set PLLSAI1 clock source */
      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);
#else
      /* Set PLLSAI1 clock source and divider M */
      MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);
 80067ae:	4b49      	ldr	r3, [pc, #292]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 80067b0:	68db      	ldr	r3, [r3, #12]
 80067b2:	f023 0273 	bic.w	r2, r3, #115	@ 0x73
 80067b6:	687b      	ldr	r3, [r7, #4]
 80067b8:	6819      	ldr	r1, [r3, #0]
 80067ba:	687b      	ldr	r3, [r7, #4]
 80067bc:	685b      	ldr	r3, [r3, #4]
 80067be:	3b01      	subs	r3, #1
 80067c0:	011b      	lsls	r3, r3, #4
 80067c2:	430b      	orrs	r3, r1
 80067c4:	4943      	ldr	r1, [pc, #268]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 80067c6:	4313      	orrs	r3, r2
 80067c8:	60cb      	str	r3, [r1, #12]
#endif
    }
  }

  if(status == HAL_OK)
 80067ca:	7bfb      	ldrb	r3, [r7, #15]
 80067cc:	2b00      	cmp	r3, #0
 80067ce:	d17c      	bne.n	80068ca <RCCEx_PLLSAI1_Config+0x1d6>
  {
    /* Disable the PLLSAI1 */
    __HAL_RCC_PLLSAI1_DISABLE();
 80067d0:	4b40      	ldr	r3, [pc, #256]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 80067d2:	681b      	ldr	r3, [r3, #0]
 80067d4:	4a3f      	ldr	r2, [pc, #252]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 80067d6:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
 80067da:	6013      	str	r3, [r2, #0]

    /* Get Start Tick*/
    tickstart = HAL_GetTick();
 80067dc:	f7fd fc9e 	bl	800411c <HAL_GetTick>
 80067e0:	60b8      	str	r0, [r7, #8]

    /* Wait till PLLSAI1 is ready to be updated */
    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
 80067e2:	e009      	b.n	80067f8 <RCCEx_PLLSAI1_Config+0x104>
    {
      if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
 80067e4:	f7fd fc9a 	bl	800411c <HAL_GetTick>
 80067e8:	4602      	mov	r2, r0
 80067ea:	68bb      	ldr	r3, [r7, #8]
 80067ec:	1ad3      	subs	r3, r2, r3
 80067ee:	2b02      	cmp	r3, #2
 80067f0:	d902      	bls.n	80067f8 <RCCEx_PLLSAI1_Config+0x104>
      {
        status = HAL_TIMEOUT;
 80067f2:	2303      	movs	r3, #3
 80067f4:	73fb      	strb	r3, [r7, #15]
        break;
 80067f6:	e005      	b.n	8006804 <RCCEx_PLLSAI1_Config+0x110>
    while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
 80067f8:	4b36      	ldr	r3, [pc, #216]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 80067fa:	681b      	ldr	r3, [r3, #0]
 80067fc:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 8006800:	2b00      	cmp	r3, #0
 8006802:	d1ef      	bne.n	80067e4 <RCCEx_PLLSAI1_Config+0xf0>
      }
    }

    if(status == HAL_OK)
 8006804:	7bfb      	ldrb	r3, [r7, #15]
 8006806:	2b00      	cmp	r3, #0
 8006808:	d15f      	bne.n	80068ca <RCCEx_PLLSAI1_Config+0x1d6>
    {
      if(Divider == DIVIDER_P_UPDATE)
 800680a:	683b      	ldr	r3, [r7, #0]
 800680c:	2b00      	cmp	r3, #0
 800680e:	d110      	bne.n	8006832 <RCCEx_PLLSAI1_Config+0x13e>
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */

#else
        /* Configure the PLLSAI1 Division factor P and Multiplication factor N*/
#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
        MODIFY_REG(RCC->PLLSAI1CFGR,
 8006810:	4b30      	ldr	r3, [pc, #192]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 8006812:	691b      	ldr	r3, [r3, #16]
 8006814:	f023 4378 	bic.w	r3, r3, #4160749568	@ 0xf8000000
 8006818:	f423 43fe 	bic.w	r3, r3, #32512	@ 0x7f00
 800681c:	687a      	ldr	r2, [r7, #4]
 800681e:	6892      	ldr	r2, [r2, #8]
 8006820:	0211      	lsls	r1, r2, #8
 8006822:	687a      	ldr	r2, [r7, #4]
 8006824:	68d2      	ldr	r2, [r2, #12]
 8006826:	06d2      	lsls	r2, r2, #27
 8006828:	430a      	orrs	r2, r1
 800682a:	492a      	ldr	r1, [pc, #168]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 800682c:	4313      	orrs	r3, r2
 800682e:	610b      	str	r3, [r1, #16]
 8006830:	e027      	b.n	8006882 <RCCEx_PLLSAI1_Config+0x18e>
                   ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */

#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
      }
      else if(Divider == DIVIDER_Q_UPDATE)
 8006832:	683b      	ldr	r3, [r7, #0]
 8006834:	2b01      	cmp	r3, #1
 8006836:	d112      	bne.n	800685e <RCCEx_PLLSAI1_Config+0x16a>
                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
                   (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |
                   ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
#else
        /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
        MODIFY_REG(RCC->PLLSAI1CFGR,
 8006838:	4b26      	ldr	r3, [pc, #152]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 800683a:	691b      	ldr	r3, [r3, #16]
 800683c:	f423 03c0 	bic.w	r3, r3, #6291456	@ 0x600000
 8006840:	f423 43fe 	bic.w	r3, r3, #32512	@ 0x7f00
 8006844:	687a      	ldr	r2, [r7, #4]
 8006846:	6892      	ldr	r2, [r2, #8]
 8006848:	0211      	lsls	r1, r2, #8
 800684a:	687a      	ldr	r2, [r7, #4]
 800684c:	6912      	ldr	r2, [r2, #16]
 800684e:	0852      	lsrs	r2, r2, #1
 8006850:	3a01      	subs	r2, #1
 8006852:	0552      	lsls	r2, r2, #21
 8006854:	430a      	orrs	r2, r1
 8006856:	491f      	ldr	r1, [pc, #124]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 8006858:	4313      	orrs	r3, r2
 800685a:	610b      	str	r3, [r1, #16]
 800685c:	e011      	b.n	8006882 <RCCEx_PLLSAI1_Config+0x18e>
                   (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
                   (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |
                   ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
#else
        /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
        MODIFY_REG(RCC->PLLSAI1CFGR,
 800685e:	4b1d      	ldr	r3, [pc, #116]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 8006860:	691b      	ldr	r3, [r3, #16]
 8006862:	f023 63c0 	bic.w	r3, r3, #100663296	@ 0x6000000
 8006866:	f423 43fe 	bic.w	r3, r3, #32512	@ 0x7f00
 800686a:	687a      	ldr	r2, [r7, #4]
 800686c:	6892      	ldr	r2, [r2, #8]
 800686e:	0211      	lsls	r1, r2, #8
 8006870:	687a      	ldr	r2, [r7, #4]
 8006872:	6952      	ldr	r2, [r2, #20]
 8006874:	0852      	lsrs	r2, r2, #1
 8006876:	3a01      	subs	r2, #1
 8006878:	0652      	lsls	r2, r2, #25
 800687a:	430a      	orrs	r2, r1
 800687c:	4915      	ldr	r1, [pc, #84]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 800687e:	4313      	orrs	r3, r2
 8006880:	610b      	str	r3, [r1, #16]
                   (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
      }

      /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
      __HAL_RCC_PLLSAI1_ENABLE();
 8006882:	4b14      	ldr	r3, [pc, #80]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 8006884:	681b      	ldr	r3, [r3, #0]
 8006886:	4a13      	ldr	r2, [pc, #76]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 8006888:	f043 6380 	orr.w	r3, r3, #67108864	@ 0x4000000
 800688c:	6013      	str	r3, [r2, #0]

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 800688e:	f7fd fc45 	bl	800411c <HAL_GetTick>
 8006892:	60b8      	str	r0, [r7, #8]

      /* Wait till PLLSAI1 is ready */
      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
 8006894:	e009      	b.n	80068aa <RCCEx_PLLSAI1_Config+0x1b6>
      {
        if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
 8006896:	f7fd fc41 	bl	800411c <HAL_GetTick>
 800689a:	4602      	mov	r2, r0
 800689c:	68bb      	ldr	r3, [r7, #8]
 800689e:	1ad3      	subs	r3, r2, r3
 80068a0:	2b02      	cmp	r3, #2
 80068a2:	d902      	bls.n	80068aa <RCCEx_PLLSAI1_Config+0x1b6>
        {
          status = HAL_TIMEOUT;
 80068a4:	2303      	movs	r3, #3
 80068a6:	73fb      	strb	r3, [r7, #15]
          break;
 80068a8:	e005      	b.n	80068b6 <RCCEx_PLLSAI1_Config+0x1c2>
      while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
 80068aa:	4b0a      	ldr	r3, [pc, #40]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 80068ac:	681b      	ldr	r3, [r3, #0]
 80068ae:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
 80068b2:	2b00      	cmp	r3, #0
 80068b4:	d0ef      	beq.n	8006896 <RCCEx_PLLSAI1_Config+0x1a2>
        }
      }

      if(status == HAL_OK)
 80068b6:	7bfb      	ldrb	r3, [r7, #15]
 80068b8:	2b00      	cmp	r3, #0
 80068ba:	d106      	bne.n	80068ca <RCCEx_PLLSAI1_Config+0x1d6>
      {
        /* Configure the PLLSAI1 Clock output(s) */
        __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
 80068bc:	4b05      	ldr	r3, [pc, #20]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 80068be:	691a      	ldr	r2, [r3, #16]
 80068c0:	687b      	ldr	r3, [r7, #4]
 80068c2:	699b      	ldr	r3, [r3, #24]
 80068c4:	4903      	ldr	r1, [pc, #12]	@ (80068d4 <RCCEx_PLLSAI1_Config+0x1e0>)
 80068c6:	4313      	orrs	r3, r2
 80068c8:	610b      	str	r3, [r1, #16]
      }
    }
  }

  return status;
 80068ca:	7bfb      	ldrb	r3, [r7, #15]
}
 80068cc:	4618      	mov	r0, r3
 80068ce:	3710      	adds	r7, #16
 80068d0:	46bd      	mov	sp, r7
 80068d2:	bd80      	pop	{r7, pc}
 80068d4:	40021000 	.word	0x40021000

080068d8 <HAL_UART_Init>:
  *        parameters in the UART_InitTypeDef and initialize the associated handle.
  * @param huart UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
 80068d8:	b580      	push	{r7, lr}
 80068da:	b082      	sub	sp, #8
 80068dc:	af00      	add	r7, sp, #0
 80068de:	6078      	str	r0, [r7, #4]
  /* Check the UART handle allocation */
  if (huart == NULL)
 80068e0:	687b      	ldr	r3, [r7, #4]
 80068e2:	2b00      	cmp	r3, #0
 80068e4:	d101      	bne.n	80068ea <HAL_UART_Init+0x12>
  {
    return HAL_ERROR;
 80068e6:	2301      	movs	r3, #1
 80068e8:	e040      	b.n	800696c <HAL_UART_Init+0x94>
  {
    /* Check the parameters */
    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
  }

  if (huart->gState == HAL_UART_STATE_RESET)
 80068ea:	687b      	ldr	r3, [r7, #4]
 80068ec:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
 80068ee:	2b00      	cmp	r3, #0
 80068f0:	d106      	bne.n	8006900 <HAL_UART_Init+0x28>
  {
    /* Allocate lock resource and initialize it */
    huart->Lock = HAL_UNLOCKED;
 80068f2:	687b      	ldr	r3, [r7, #4]
 80068f4:	2200      	movs	r2, #0
 80068f6:	f883 2078 	strb.w	r2, [r3, #120]	@ 0x78

    /* Init the low level hardware */
    huart->MspInitCallback(huart);
#else
    /* Init the low level hardware : GPIO, CLOCK */
    HAL_UART_MspInit(huart);
 80068fa:	6878      	ldr	r0, [r7, #4]
 80068fc:	f7fd fa10 	bl	8003d20 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
  }

  huart->gState = HAL_UART_STATE_BUSY;
 8006900:	687b      	ldr	r3, [r7, #4]
 8006902:	2224      	movs	r2, #36	@ 0x24
 8006904:	67da      	str	r2, [r3, #124]	@ 0x7c

  __HAL_UART_DISABLE(huart);
 8006906:	687b      	ldr	r3, [r7, #4]
 8006908:	681b      	ldr	r3, [r3, #0]
 800690a:	681a      	ldr	r2, [r3, #0]
 800690c:	687b      	ldr	r3, [r7, #4]
 800690e:	681b      	ldr	r3, [r3, #0]
 8006910:	f022 0201 	bic.w	r2, r2, #1
 8006914:	601a      	str	r2, [r3, #0]

  /* Perform advanced settings configuration */
  /* For some items, configuration requires to be done prior TE and RE bits are set */
  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
 8006916:	687b      	ldr	r3, [r7, #4]
 8006918:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800691a:	2b00      	cmp	r3, #0
 800691c:	d002      	beq.n	8006924 <HAL_UART_Init+0x4c>
  {
    UART_AdvFeatureConfig(huart);
 800691e:	6878      	ldr	r0, [r7, #4]
 8006920:	f000 fb38 	bl	8006f94 <UART_AdvFeatureConfig>
  }

  /* Set the UART Communication parameters */
  if (UART_SetConfig(huart) == HAL_ERROR)
 8006924:	6878      	ldr	r0, [r7, #4]
 8006926:	f000 f8af 	bl	8006a88 <UART_SetConfig>
 800692a:	4603      	mov	r3, r0
 800692c:	2b01      	cmp	r3, #1
 800692e:	d101      	bne.n	8006934 <HAL_UART_Init+0x5c>
  {
    return HAL_ERROR;
 8006930:	2301      	movs	r3, #1
 8006932:	e01b      	b.n	800696c <HAL_UART_Init+0x94>
  }

  /* In asynchronous mode, the following bits must be kept cleared:
  - LINEN and CLKEN bits in the USART_CR2 register,
  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 8006934:	687b      	ldr	r3, [r7, #4]
 8006936:	681b      	ldr	r3, [r3, #0]
 8006938:	685a      	ldr	r2, [r3, #4]
 800693a:	687b      	ldr	r3, [r7, #4]
 800693c:	681b      	ldr	r3, [r3, #0]
 800693e:	f422 4290 	bic.w	r2, r2, #18432	@ 0x4800
 8006942:	605a      	str	r2, [r3, #4]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 8006944:	687b      	ldr	r3, [r7, #4]
 8006946:	681b      	ldr	r3, [r3, #0]
 8006948:	689a      	ldr	r2, [r3, #8]
 800694a:	687b      	ldr	r3, [r7, #4]
 800694c:	681b      	ldr	r3, [r3, #0]
 800694e:	f022 022a 	bic.w	r2, r2, #42	@ 0x2a
 8006952:	609a      	str	r2, [r3, #8]

  __HAL_UART_ENABLE(huart);
 8006954:	687b      	ldr	r3, [r7, #4]
 8006956:	681b      	ldr	r3, [r3, #0]
 8006958:	681a      	ldr	r2, [r3, #0]
 800695a:	687b      	ldr	r3, [r7, #4]
 800695c:	681b      	ldr	r3, [r3, #0]
 800695e:	f042 0201 	orr.w	r2, r2, #1
 8006962:	601a      	str	r2, [r3, #0]

  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
  return (UART_CheckIdleState(huart));
 8006964:	6878      	ldr	r0, [r7, #4]
 8006966:	f000 fbb7 	bl	80070d8 <UART_CheckIdleState>
 800696a:	4603      	mov	r3, r0
}
 800696c:	4618      	mov	r0, r3
 800696e:	3708      	adds	r7, #8
 8006970:	46bd      	mov	sp, r7
 8006972:	bd80      	pop	{r7, pc}

08006974 <HAL_UART_Transmit>:
  * @param Size    Amount of data elements (u8 or u16) to be sent.
  * @param Timeout Timeout duration.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
 8006974:	b580      	push	{r7, lr}
 8006976:	b08a      	sub	sp, #40	@ 0x28
 8006978:	af02      	add	r7, sp, #8
 800697a:	60f8      	str	r0, [r7, #12]
 800697c:	60b9      	str	r1, [r7, #8]
 800697e:	603b      	str	r3, [r7, #0]
 8006980:	4613      	mov	r3, r2
 8006982:	80fb      	strh	r3, [r7, #6]
  const uint8_t  *pdata8bits;
  const uint16_t *pdata16bits;
  uint32_t tickstart;

  /* Check that a Tx process is not already ongoing */
  if (huart->gState == HAL_UART_STATE_READY)
 8006984:	68fb      	ldr	r3, [r7, #12]
 8006986:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
 8006988:	2b20      	cmp	r3, #32
 800698a:	d177      	bne.n	8006a7c <HAL_UART_Transmit+0x108>
  {
    if ((pData == NULL) || (Size == 0U))
 800698c:	68bb      	ldr	r3, [r7, #8]
 800698e:	2b00      	cmp	r3, #0
 8006990:	d002      	beq.n	8006998 <HAL_UART_Transmit+0x24>
 8006992:	88fb      	ldrh	r3, [r7, #6]
 8006994:	2b00      	cmp	r3, #0
 8006996:	d101      	bne.n	800699c <HAL_UART_Transmit+0x28>
    {
      return  HAL_ERROR;
 8006998:	2301      	movs	r3, #1
 800699a:	e070      	b.n	8006a7e <HAL_UART_Transmit+0x10a>
    }

    huart->ErrorCode = HAL_UART_ERROR_NONE;
 800699c:	68fb      	ldr	r3, [r7, #12]
 800699e:	2200      	movs	r2, #0
 80069a0:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
    huart->gState = HAL_UART_STATE_BUSY_TX;
 80069a4:	68fb      	ldr	r3, [r7, #12]
 80069a6:	2221      	movs	r2, #33	@ 0x21
 80069a8:	67da      	str	r2, [r3, #124]	@ 0x7c

    /* Init tickstart for timeout management */
    tickstart = HAL_GetTick();
 80069aa:	f7fd fbb7 	bl	800411c <HAL_GetTick>
 80069ae:	6178      	str	r0, [r7, #20]

    huart->TxXferSize  = Size;
 80069b0:	68fb      	ldr	r3, [r7, #12]
 80069b2:	88fa      	ldrh	r2, [r7, #6]
 80069b4:	f8a3 2050 	strh.w	r2, [r3, #80]	@ 0x50
    huart->TxXferCount = Size;
 80069b8:	68fb      	ldr	r3, [r7, #12]
 80069ba:	88fa      	ldrh	r2, [r7, #6]
 80069bc:	f8a3 2052 	strh.w	r2, [r3, #82]	@ 0x52

    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 80069c0:	68fb      	ldr	r3, [r7, #12]
 80069c2:	689b      	ldr	r3, [r3, #8]
 80069c4:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
 80069c8:	d108      	bne.n	80069dc <HAL_UART_Transmit+0x68>
 80069ca:	68fb      	ldr	r3, [r7, #12]
 80069cc:	691b      	ldr	r3, [r3, #16]
 80069ce:	2b00      	cmp	r3, #0
 80069d0:	d104      	bne.n	80069dc <HAL_UART_Transmit+0x68>
    {
      pdata8bits  = NULL;
 80069d2:	2300      	movs	r3, #0
 80069d4:	61fb      	str	r3, [r7, #28]
      pdata16bits = (const uint16_t *) pData;
 80069d6:	68bb      	ldr	r3, [r7, #8]
 80069d8:	61bb      	str	r3, [r7, #24]
 80069da:	e003      	b.n	80069e4 <HAL_UART_Transmit+0x70>
    }
    else
    {
      pdata8bits  = pData;
 80069dc:	68bb      	ldr	r3, [r7, #8]
 80069de:	61fb      	str	r3, [r7, #28]
      pdata16bits = NULL;
 80069e0:	2300      	movs	r3, #0
 80069e2:	61bb      	str	r3, [r7, #24]
    }

    while (huart->TxXferCount > 0U)
 80069e4:	e02f      	b.n	8006a46 <HAL_UART_Transmit+0xd2>
    {
      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80069e6:	683b      	ldr	r3, [r7, #0]
 80069e8:	9300      	str	r3, [sp, #0]
 80069ea:	697b      	ldr	r3, [r7, #20]
 80069ec:	2200      	movs	r2, #0
 80069ee:	2180      	movs	r1, #128	@ 0x80
 80069f0:	68f8      	ldr	r0, [r7, #12]
 80069f2:	f000 fc19 	bl	8007228 <UART_WaitOnFlagUntilTimeout>
 80069f6:	4603      	mov	r3, r0
 80069f8:	2b00      	cmp	r3, #0
 80069fa:	d004      	beq.n	8006a06 <HAL_UART_Transmit+0x92>
      {

        huart->gState = HAL_UART_STATE_READY;
 80069fc:	68fb      	ldr	r3, [r7, #12]
 80069fe:	2220      	movs	r2, #32
 8006a00:	67da      	str	r2, [r3, #124]	@ 0x7c

        return HAL_TIMEOUT;
 8006a02:	2303      	movs	r3, #3
 8006a04:	e03b      	b.n	8006a7e <HAL_UART_Transmit+0x10a>
      }
      if (pdata8bits == NULL)
 8006a06:	69fb      	ldr	r3, [r7, #28]
 8006a08:	2b00      	cmp	r3, #0
 8006a0a:	d10b      	bne.n	8006a24 <HAL_UART_Transmit+0xb0>
      {
        huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
 8006a0c:	69bb      	ldr	r3, [r7, #24]
 8006a0e:	881a      	ldrh	r2, [r3, #0]
 8006a10:	68fb      	ldr	r3, [r7, #12]
 8006a12:	681b      	ldr	r3, [r3, #0]
 8006a14:	f3c2 0208 	ubfx	r2, r2, #0, #9
 8006a18:	b292      	uxth	r2, r2
 8006a1a:	851a      	strh	r2, [r3, #40]	@ 0x28
        pdata16bits++;
 8006a1c:	69bb      	ldr	r3, [r7, #24]
 8006a1e:	3302      	adds	r3, #2
 8006a20:	61bb      	str	r3, [r7, #24]
 8006a22:	e007      	b.n	8006a34 <HAL_UART_Transmit+0xc0>
      }
      else
      {
        huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
 8006a24:	69fb      	ldr	r3, [r7, #28]
 8006a26:	781a      	ldrb	r2, [r3, #0]
 8006a28:	68fb      	ldr	r3, [r7, #12]
 8006a2a:	681b      	ldr	r3, [r3, #0]
 8006a2c:	851a      	strh	r2, [r3, #40]	@ 0x28
        pdata8bits++;
 8006a2e:	69fb      	ldr	r3, [r7, #28]
 8006a30:	3301      	adds	r3, #1
 8006a32:	61fb      	str	r3, [r7, #28]
      }
      huart->TxXferCount--;
 8006a34:	68fb      	ldr	r3, [r7, #12]
 8006a36:	f8b3 3052 	ldrh.w	r3, [r3, #82]	@ 0x52
 8006a3a:	b29b      	uxth	r3, r3
 8006a3c:	3b01      	subs	r3, #1
 8006a3e:	b29a      	uxth	r2, r3
 8006a40:	68fb      	ldr	r3, [r7, #12]
 8006a42:	f8a3 2052 	strh.w	r2, [r3, #82]	@ 0x52
    while (huart->TxXferCount > 0U)
 8006a46:	68fb      	ldr	r3, [r7, #12]
 8006a48:	f8b3 3052 	ldrh.w	r3, [r3, #82]	@ 0x52
 8006a4c:	b29b      	uxth	r3, r3
 8006a4e:	2b00      	cmp	r3, #0
 8006a50:	d1c9      	bne.n	80069e6 <HAL_UART_Transmit+0x72>
    }

    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
 8006a52:	683b      	ldr	r3, [r7, #0]
 8006a54:	9300      	str	r3, [sp, #0]
 8006a56:	697b      	ldr	r3, [r7, #20]
 8006a58:	2200      	movs	r2, #0
 8006a5a:	2140      	movs	r1, #64	@ 0x40
 8006a5c:	68f8      	ldr	r0, [r7, #12]
 8006a5e:	f000 fbe3 	bl	8007228 <UART_WaitOnFlagUntilTimeout>
 8006a62:	4603      	mov	r3, r0
 8006a64:	2b00      	cmp	r3, #0
 8006a66:	d004      	beq.n	8006a72 <HAL_UART_Transmit+0xfe>
    {
      huart->gState = HAL_UART_STATE_READY;
 8006a68:	68fb      	ldr	r3, [r7, #12]
 8006a6a:	2220      	movs	r2, #32
 8006a6c:	67da      	str	r2, [r3, #124]	@ 0x7c

      return HAL_TIMEOUT;
 8006a6e:	2303      	movs	r3, #3
 8006a70:	e005      	b.n	8006a7e <HAL_UART_Transmit+0x10a>
    }

    /* At end of Tx process, restore huart->gState to Ready */
    huart->gState = HAL_UART_STATE_READY;
 8006a72:	68fb      	ldr	r3, [r7, #12]
 8006a74:	2220      	movs	r2, #32
 8006a76:	67da      	str	r2, [r3, #124]	@ 0x7c

    return HAL_OK;
 8006a78:	2300      	movs	r3, #0
 8006a7a:	e000      	b.n	8006a7e <HAL_UART_Transmit+0x10a>
  }
  else
  {
    return HAL_BUSY;
 8006a7c:	2302      	movs	r3, #2
  }
}
 8006a7e:	4618      	mov	r0, r3
 8006a80:	3720      	adds	r7, #32
 8006a82:	46bd      	mov	sp, r7
 8006a84:	bd80      	pop	{r7, pc}
	...

08006a88 <UART_SetConfig>:
  * @brief Configure the UART peripheral.
  * @param huart UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
 8006a88:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
 8006a8c:	b08a      	sub	sp, #40	@ 0x28
 8006a8e:	af00      	add	r7, sp, #0
 8006a90:	60f8      	str	r0, [r7, #12]
  uint32_t tmpreg;
  uint16_t brrtemp;
  UART_ClockSourceTypeDef clocksource;
  uint32_t usartdiv;
  HAL_StatusTypeDef ret               = HAL_OK;
 8006a92:	2300      	movs	r3, #0
 8006a94:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
  *  the UART Word Length, Parity, Mode and oversampling:
  *  set the M bits according to huart->Init.WordLength value
  *  set PCE and PS bits according to huart->Init.Parity value
  *  set TE and RE bits according to huart->Init.Mode value
  *  set OVER8 bit according to huart->Init.OverSampling value */
  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
 8006a98:	68fb      	ldr	r3, [r7, #12]
 8006a9a:	689a      	ldr	r2, [r3, #8]
 8006a9c:	68fb      	ldr	r3, [r7, #12]
 8006a9e:	691b      	ldr	r3, [r3, #16]
 8006aa0:	431a      	orrs	r2, r3
 8006aa2:	68fb      	ldr	r3, [r7, #12]
 8006aa4:	695b      	ldr	r3, [r3, #20]
 8006aa6:	431a      	orrs	r2, r3
 8006aa8:	68fb      	ldr	r3, [r7, #12]
 8006aaa:	69db      	ldr	r3, [r3, #28]
 8006aac:	4313      	orrs	r3, r2
 8006aae:	627b      	str	r3, [r7, #36]	@ 0x24
  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
 8006ab0:	68fb      	ldr	r3, [r7, #12]
 8006ab2:	681b      	ldr	r3, [r3, #0]
 8006ab4:	681a      	ldr	r2, [r3, #0]
 8006ab6:	4ba5      	ldr	r3, [pc, #660]	@ (8006d4c <UART_SetConfig+0x2c4>)
 8006ab8:	4013      	ands	r3, r2
 8006aba:	68fa      	ldr	r2, [r7, #12]
 8006abc:	6812      	ldr	r2, [r2, #0]
 8006abe:	6a79      	ldr	r1, [r7, #36]	@ 0x24
 8006ac0:	430b      	orrs	r3, r1
 8006ac2:	6013      	str	r3, [r2, #0]

  /*-------------------------- USART CR2 Configuration -----------------------*/
  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
  * to huart->Init.StopBits value */
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 8006ac4:	68fb      	ldr	r3, [r7, #12]
 8006ac6:	681b      	ldr	r3, [r3, #0]
 8006ac8:	685b      	ldr	r3, [r3, #4]
 8006aca:	f423 5140 	bic.w	r1, r3, #12288	@ 0x3000
 8006ace:	68fb      	ldr	r3, [r7, #12]
 8006ad0:	68da      	ldr	r2, [r3, #12]
 8006ad2:	68fb      	ldr	r3, [r7, #12]
 8006ad4:	681b      	ldr	r3, [r3, #0]
 8006ad6:	430a      	orrs	r2, r1
 8006ad8:	605a      	str	r2, [r3, #4]
  /* Configure
  * - UART HardWare Flow Control: set CTSE and RTSE bits according
  *   to huart->Init.HwFlowCtl value
  * - one-bit sampling method versus three samples' majority rule according
  *   to huart->Init.OneBitSampling (not applicable to LPUART) */
  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
 8006ada:	68fb      	ldr	r3, [r7, #12]
 8006adc:	699b      	ldr	r3, [r3, #24]
 8006ade:	627b      	str	r3, [r7, #36]	@ 0x24

  if (!(UART_INSTANCE_LOWPOWER(huart)))
 8006ae0:	68fb      	ldr	r3, [r7, #12]
 8006ae2:	681b      	ldr	r3, [r3, #0]
 8006ae4:	4a9a      	ldr	r2, [pc, #616]	@ (8006d50 <UART_SetConfig+0x2c8>)
 8006ae6:	4293      	cmp	r3, r2
 8006ae8:	d004      	beq.n	8006af4 <UART_SetConfig+0x6c>
  {
    tmpreg |= huart->Init.OneBitSampling;
 8006aea:	68fb      	ldr	r3, [r7, #12]
 8006aec:	6a1b      	ldr	r3, [r3, #32]
 8006aee:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8006af0:	4313      	orrs	r3, r2
 8006af2:	627b      	str	r3, [r7, #36]	@ 0x24
  }
  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
 8006af4:	68fb      	ldr	r3, [r7, #12]
 8006af6:	681b      	ldr	r3, [r3, #0]
 8006af8:	689b      	ldr	r3, [r3, #8]
 8006afa:	f423 6130 	bic.w	r1, r3, #2816	@ 0xb00
 8006afe:	68fb      	ldr	r3, [r7, #12]
 8006b00:	681b      	ldr	r3, [r3, #0]
 8006b02:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
 8006b04:	430a      	orrs	r2, r1
 8006b06:	609a      	str	r2, [r3, #8]
  * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
#endif /* USART_PRESC_PRESCALER */

  /*-------------------------- USART BRR Configuration -----------------------*/
  UART_GETCLOCKSOURCE(huart, clocksource);
 8006b08:	68fb      	ldr	r3, [r7, #12]
 8006b0a:	681b      	ldr	r3, [r3, #0]
 8006b0c:	4a91      	ldr	r2, [pc, #580]	@ (8006d54 <UART_SetConfig+0x2cc>)
 8006b0e:	4293      	cmp	r3, r2
 8006b10:	d126      	bne.n	8006b60 <UART_SetConfig+0xd8>
 8006b12:	4b91      	ldr	r3, [pc, #580]	@ (8006d58 <UART_SetConfig+0x2d0>)
 8006b14:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8006b18:	f003 0303 	and.w	r3, r3, #3
 8006b1c:	2b03      	cmp	r3, #3
 8006b1e:	d81b      	bhi.n	8006b58 <UART_SetConfig+0xd0>
 8006b20:	a201      	add	r2, pc, #4	@ (adr r2, 8006b28 <UART_SetConfig+0xa0>)
 8006b22:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8006b26:	bf00      	nop
 8006b28:	08006b39 	.word	0x08006b39
 8006b2c:	08006b49 	.word	0x08006b49
 8006b30:	08006b41 	.word	0x08006b41
 8006b34:	08006b51 	.word	0x08006b51
 8006b38:	2301      	movs	r3, #1
 8006b3a:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006b3e:	e0d6      	b.n	8006cee <UART_SetConfig+0x266>
 8006b40:	2302      	movs	r3, #2
 8006b42:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006b46:	e0d2      	b.n	8006cee <UART_SetConfig+0x266>
 8006b48:	2304      	movs	r3, #4
 8006b4a:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006b4e:	e0ce      	b.n	8006cee <UART_SetConfig+0x266>
 8006b50:	2308      	movs	r3, #8
 8006b52:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006b56:	e0ca      	b.n	8006cee <UART_SetConfig+0x266>
 8006b58:	2310      	movs	r3, #16
 8006b5a:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006b5e:	e0c6      	b.n	8006cee <UART_SetConfig+0x266>
 8006b60:	68fb      	ldr	r3, [r7, #12]
 8006b62:	681b      	ldr	r3, [r3, #0]
 8006b64:	4a7d      	ldr	r2, [pc, #500]	@ (8006d5c <UART_SetConfig+0x2d4>)
 8006b66:	4293      	cmp	r3, r2
 8006b68:	d138      	bne.n	8006bdc <UART_SetConfig+0x154>
 8006b6a:	4b7b      	ldr	r3, [pc, #492]	@ (8006d58 <UART_SetConfig+0x2d0>)
 8006b6c:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8006b70:	f003 030c 	and.w	r3, r3, #12
 8006b74:	2b0c      	cmp	r3, #12
 8006b76:	d82d      	bhi.n	8006bd4 <UART_SetConfig+0x14c>
 8006b78:	a201      	add	r2, pc, #4	@ (adr r2, 8006b80 <UART_SetConfig+0xf8>)
 8006b7a:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8006b7e:	bf00      	nop
 8006b80:	08006bb5 	.word	0x08006bb5
 8006b84:	08006bd5 	.word	0x08006bd5
 8006b88:	08006bd5 	.word	0x08006bd5
 8006b8c:	08006bd5 	.word	0x08006bd5
 8006b90:	08006bc5 	.word	0x08006bc5
 8006b94:	08006bd5 	.word	0x08006bd5
 8006b98:	08006bd5 	.word	0x08006bd5
 8006b9c:	08006bd5 	.word	0x08006bd5
 8006ba0:	08006bbd 	.word	0x08006bbd
 8006ba4:	08006bd5 	.word	0x08006bd5
 8006ba8:	08006bd5 	.word	0x08006bd5
 8006bac:	08006bd5 	.word	0x08006bd5
 8006bb0:	08006bcd 	.word	0x08006bcd
 8006bb4:	2300      	movs	r3, #0
 8006bb6:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006bba:	e098      	b.n	8006cee <UART_SetConfig+0x266>
 8006bbc:	2302      	movs	r3, #2
 8006bbe:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006bc2:	e094      	b.n	8006cee <UART_SetConfig+0x266>
 8006bc4:	2304      	movs	r3, #4
 8006bc6:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006bca:	e090      	b.n	8006cee <UART_SetConfig+0x266>
 8006bcc:	2308      	movs	r3, #8
 8006bce:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006bd2:	e08c      	b.n	8006cee <UART_SetConfig+0x266>
 8006bd4:	2310      	movs	r3, #16
 8006bd6:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006bda:	e088      	b.n	8006cee <UART_SetConfig+0x266>
 8006bdc:	68fb      	ldr	r3, [r7, #12]
 8006bde:	681b      	ldr	r3, [r3, #0]
 8006be0:	4a5f      	ldr	r2, [pc, #380]	@ (8006d60 <UART_SetConfig+0x2d8>)
 8006be2:	4293      	cmp	r3, r2
 8006be4:	d125      	bne.n	8006c32 <UART_SetConfig+0x1aa>
 8006be6:	4b5c      	ldr	r3, [pc, #368]	@ (8006d58 <UART_SetConfig+0x2d0>)
 8006be8:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8006bec:	f003 0330 	and.w	r3, r3, #48	@ 0x30
 8006bf0:	2b30      	cmp	r3, #48	@ 0x30
 8006bf2:	d016      	beq.n	8006c22 <UART_SetConfig+0x19a>
 8006bf4:	2b30      	cmp	r3, #48	@ 0x30
 8006bf6:	d818      	bhi.n	8006c2a <UART_SetConfig+0x1a2>
 8006bf8:	2b20      	cmp	r3, #32
 8006bfa:	d00a      	beq.n	8006c12 <UART_SetConfig+0x18a>
 8006bfc:	2b20      	cmp	r3, #32
 8006bfe:	d814      	bhi.n	8006c2a <UART_SetConfig+0x1a2>
 8006c00:	2b00      	cmp	r3, #0
 8006c02:	d002      	beq.n	8006c0a <UART_SetConfig+0x182>
 8006c04:	2b10      	cmp	r3, #16
 8006c06:	d008      	beq.n	8006c1a <UART_SetConfig+0x192>
 8006c08:	e00f      	b.n	8006c2a <UART_SetConfig+0x1a2>
 8006c0a:	2300      	movs	r3, #0
 8006c0c:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006c10:	e06d      	b.n	8006cee <UART_SetConfig+0x266>
 8006c12:	2302      	movs	r3, #2
 8006c14:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006c18:	e069      	b.n	8006cee <UART_SetConfig+0x266>
 8006c1a:	2304      	movs	r3, #4
 8006c1c:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006c20:	e065      	b.n	8006cee <UART_SetConfig+0x266>
 8006c22:	2308      	movs	r3, #8
 8006c24:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006c28:	e061      	b.n	8006cee <UART_SetConfig+0x266>
 8006c2a:	2310      	movs	r3, #16
 8006c2c:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006c30:	e05d      	b.n	8006cee <UART_SetConfig+0x266>
 8006c32:	68fb      	ldr	r3, [r7, #12]
 8006c34:	681b      	ldr	r3, [r3, #0]
 8006c36:	4a4b      	ldr	r2, [pc, #300]	@ (8006d64 <UART_SetConfig+0x2dc>)
 8006c38:	4293      	cmp	r3, r2
 8006c3a:	d125      	bne.n	8006c88 <UART_SetConfig+0x200>
 8006c3c:	4b46      	ldr	r3, [pc, #280]	@ (8006d58 <UART_SetConfig+0x2d0>)
 8006c3e:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8006c42:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
 8006c46:	2bc0      	cmp	r3, #192	@ 0xc0
 8006c48:	d016      	beq.n	8006c78 <UART_SetConfig+0x1f0>
 8006c4a:	2bc0      	cmp	r3, #192	@ 0xc0
 8006c4c:	d818      	bhi.n	8006c80 <UART_SetConfig+0x1f8>
 8006c4e:	2b80      	cmp	r3, #128	@ 0x80
 8006c50:	d00a      	beq.n	8006c68 <UART_SetConfig+0x1e0>
 8006c52:	2b80      	cmp	r3, #128	@ 0x80
 8006c54:	d814      	bhi.n	8006c80 <UART_SetConfig+0x1f8>
 8006c56:	2b00      	cmp	r3, #0
 8006c58:	d002      	beq.n	8006c60 <UART_SetConfig+0x1d8>
 8006c5a:	2b40      	cmp	r3, #64	@ 0x40
 8006c5c:	d008      	beq.n	8006c70 <UART_SetConfig+0x1e8>
 8006c5e:	e00f      	b.n	8006c80 <UART_SetConfig+0x1f8>
 8006c60:	2300      	movs	r3, #0
 8006c62:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006c66:	e042      	b.n	8006cee <UART_SetConfig+0x266>
 8006c68:	2302      	movs	r3, #2
 8006c6a:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006c6e:	e03e      	b.n	8006cee <UART_SetConfig+0x266>
 8006c70:	2304      	movs	r3, #4
 8006c72:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006c76:	e03a      	b.n	8006cee <UART_SetConfig+0x266>
 8006c78:	2308      	movs	r3, #8
 8006c7a:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006c7e:	e036      	b.n	8006cee <UART_SetConfig+0x266>
 8006c80:	2310      	movs	r3, #16
 8006c82:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006c86:	e032      	b.n	8006cee <UART_SetConfig+0x266>
 8006c88:	68fb      	ldr	r3, [r7, #12]
 8006c8a:	681b      	ldr	r3, [r3, #0]
 8006c8c:	4a30      	ldr	r2, [pc, #192]	@ (8006d50 <UART_SetConfig+0x2c8>)
 8006c8e:	4293      	cmp	r3, r2
 8006c90:	d12a      	bne.n	8006ce8 <UART_SetConfig+0x260>
 8006c92:	4b31      	ldr	r3, [pc, #196]	@ (8006d58 <UART_SetConfig+0x2d0>)
 8006c94:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
 8006c98:	f403 6340 	and.w	r3, r3, #3072	@ 0xc00
 8006c9c:	f5b3 6f40 	cmp.w	r3, #3072	@ 0xc00
 8006ca0:	d01a      	beq.n	8006cd8 <UART_SetConfig+0x250>
 8006ca2:	f5b3 6f40 	cmp.w	r3, #3072	@ 0xc00
 8006ca6:	d81b      	bhi.n	8006ce0 <UART_SetConfig+0x258>
 8006ca8:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
 8006cac:	d00c      	beq.n	8006cc8 <UART_SetConfig+0x240>
 8006cae:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
 8006cb2:	d815      	bhi.n	8006ce0 <UART_SetConfig+0x258>
 8006cb4:	2b00      	cmp	r3, #0
 8006cb6:	d003      	beq.n	8006cc0 <UART_SetConfig+0x238>
 8006cb8:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
 8006cbc:	d008      	beq.n	8006cd0 <UART_SetConfig+0x248>
 8006cbe:	e00f      	b.n	8006ce0 <UART_SetConfig+0x258>
 8006cc0:	2300      	movs	r3, #0
 8006cc2:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006cc6:	e012      	b.n	8006cee <UART_SetConfig+0x266>
 8006cc8:	2302      	movs	r3, #2
 8006cca:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006cce:	e00e      	b.n	8006cee <UART_SetConfig+0x266>
 8006cd0:	2304      	movs	r3, #4
 8006cd2:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006cd6:	e00a      	b.n	8006cee <UART_SetConfig+0x266>
 8006cd8:	2308      	movs	r3, #8
 8006cda:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006cde:	e006      	b.n	8006cee <UART_SetConfig+0x266>
 8006ce0:	2310      	movs	r3, #16
 8006ce2:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23
 8006ce6:	e002      	b.n	8006cee <UART_SetConfig+0x266>
 8006ce8:	2310      	movs	r3, #16
 8006cea:	f887 3023 	strb.w	r3, [r7, #35]	@ 0x23

  /* Check LPUART instance */
  if (UART_INSTANCE_LOWPOWER(huart))
 8006cee:	68fb      	ldr	r3, [r7, #12]
 8006cf0:	681b      	ldr	r3, [r3, #0]
 8006cf2:	4a17      	ldr	r2, [pc, #92]	@ (8006d50 <UART_SetConfig+0x2c8>)
 8006cf4:	4293      	cmp	r3, r2
 8006cf6:	f040 808b 	bne.w	8006e10 <UART_SetConfig+0x388>
  {
    /* Retrieve frequency clock */
    switch (clocksource)
 8006cfa:	f897 3023 	ldrb.w	r3, [r7, #35]	@ 0x23
 8006cfe:	2b08      	cmp	r3, #8
 8006d00:	d834      	bhi.n	8006d6c <UART_SetConfig+0x2e4>
 8006d02:	a201      	add	r2, pc, #4	@ (adr r2, 8006d08 <UART_SetConfig+0x280>)
 8006d04:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8006d08:	08006d2d 	.word	0x08006d2d
 8006d0c:	08006d6d 	.word	0x08006d6d
 8006d10:	08006d35 	.word	0x08006d35
 8006d14:	08006d6d 	.word	0x08006d6d
 8006d18:	08006d3b 	.word	0x08006d3b
 8006d1c:	08006d6d 	.word	0x08006d6d
 8006d20:	08006d6d 	.word	0x08006d6d
 8006d24:	08006d6d 	.word	0x08006d6d
 8006d28:	08006d43 	.word	0x08006d43
    {
      case UART_CLOCKSOURCE_PCLK1:
        pclk = HAL_RCC_GetPCLK1Freq();
 8006d2c:	f7ff f9ea 	bl	8006104 <HAL_RCC_GetPCLK1Freq>
 8006d30:	61f8      	str	r0, [r7, #28]
        break;
 8006d32:	e021      	b.n	8006d78 <UART_SetConfig+0x2f0>
      case UART_CLOCKSOURCE_HSI:
        pclk = (uint32_t) HSI_VALUE;
 8006d34:	4b0c      	ldr	r3, [pc, #48]	@ (8006d68 <UART_SetConfig+0x2e0>)
 8006d36:	61fb      	str	r3, [r7, #28]
        break;
 8006d38:	e01e      	b.n	8006d78 <UART_SetConfig+0x2f0>
      case UART_CLOCKSOURCE_SYSCLK:
        pclk = HAL_RCC_GetSysClockFreq();
 8006d3a:	f7ff f94b 	bl	8005fd4 <HAL_RCC_GetSysClockFreq>
 8006d3e:	61f8      	str	r0, [r7, #28]
        break;
 8006d40:	e01a      	b.n	8006d78 <UART_SetConfig+0x2f0>
      case UART_CLOCKSOURCE_LSE:
        pclk = (uint32_t) LSE_VALUE;
 8006d42:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
 8006d46:	61fb      	str	r3, [r7, #28]
        break;
 8006d48:	e016      	b.n	8006d78 <UART_SetConfig+0x2f0>
 8006d4a:	bf00      	nop
 8006d4c:	efff69f3 	.word	0xefff69f3
 8006d50:	40008000 	.word	0x40008000
 8006d54:	40013800 	.word	0x40013800
 8006d58:	40021000 	.word	0x40021000
 8006d5c:	40004400 	.word	0x40004400
 8006d60:	40004800 	.word	0x40004800
 8006d64:	40004c00 	.word	0x40004c00
 8006d68:	00f42400 	.word	0x00f42400
      default:
        pclk = 0U;
 8006d6c:	2300      	movs	r3, #0
 8006d6e:	61fb      	str	r3, [r7, #28]
        ret = HAL_ERROR;
 8006d70:	2301      	movs	r3, #1
 8006d72:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
        break;
 8006d76:	bf00      	nop
    }

    /* If proper clock source reported */
    if (pclk != 0U)
 8006d78:	69fb      	ldr	r3, [r7, #28]
 8006d7a:	2b00      	cmp	r3, #0
 8006d7c:	f000 80fa 	beq.w	8006f74 <UART_SetConfig+0x4ec>
      } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
                (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
#else
      /* No Prescaler applicable */
      /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
      if ((pclk < (3U * huart->Init.BaudRate)) ||
 8006d80:	68fb      	ldr	r3, [r7, #12]
 8006d82:	685a      	ldr	r2, [r3, #4]
 8006d84:	4613      	mov	r3, r2
 8006d86:	005b      	lsls	r3, r3, #1
 8006d88:	4413      	add	r3, r2
 8006d8a:	69fa      	ldr	r2, [r7, #28]
 8006d8c:	429a      	cmp	r2, r3
 8006d8e:	d305      	bcc.n	8006d9c <UART_SetConfig+0x314>
          (pclk > (4096U * huart->Init.BaudRate)))
 8006d90:	68fb      	ldr	r3, [r7, #12]
 8006d92:	685b      	ldr	r3, [r3, #4]
 8006d94:	031b      	lsls	r3, r3, #12
      if ((pclk < (3U * huart->Init.BaudRate)) ||
 8006d96:	69fa      	ldr	r2, [r7, #28]
 8006d98:	429a      	cmp	r2, r3
 8006d9a:	d903      	bls.n	8006da4 <UART_SetConfig+0x31c>
      {
        ret = HAL_ERROR;
 8006d9c:	2301      	movs	r3, #1
 8006d9e:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
 8006da2:	e0e7      	b.n	8006f74 <UART_SetConfig+0x4ec>
      }
      else
      {
        usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
 8006da4:	69fb      	ldr	r3, [r7, #28]
 8006da6:	2200      	movs	r2, #0
 8006da8:	461c      	mov	r4, r3
 8006daa:	4615      	mov	r5, r2
 8006dac:	f04f 0200 	mov.w	r2, #0
 8006db0:	f04f 0300 	mov.w	r3, #0
 8006db4:	022b      	lsls	r3, r5, #8
 8006db6:	ea43 6314 	orr.w	r3, r3, r4, lsr #24
 8006dba:	0222      	lsls	r2, r4, #8
 8006dbc:	68f9      	ldr	r1, [r7, #12]
 8006dbe:	6849      	ldr	r1, [r1, #4]
 8006dc0:	0849      	lsrs	r1, r1, #1
 8006dc2:	2000      	movs	r0, #0
 8006dc4:	4688      	mov	r8, r1
 8006dc6:	4681      	mov	r9, r0
 8006dc8:	eb12 0a08 	adds.w	sl, r2, r8
 8006dcc:	eb43 0b09 	adc.w	fp, r3, r9
 8006dd0:	68fb      	ldr	r3, [r7, #12]
 8006dd2:	685b      	ldr	r3, [r3, #4]
 8006dd4:	2200      	movs	r2, #0
 8006dd6:	603b      	str	r3, [r7, #0]
 8006dd8:	607a      	str	r2, [r7, #4]
 8006dda:	e9d7 2300 	ldrd	r2, r3, [r7]
 8006dde:	4650      	mov	r0, sl
 8006de0:	4659      	mov	r1, fp
 8006de2:	f7f9 fee9 	bl	8000bb8 <__aeabi_uldivmod>
 8006de6:	4602      	mov	r2, r0
 8006de8:	460b      	mov	r3, r1
 8006dea:	4613      	mov	r3, r2
 8006dec:	61bb      	str	r3, [r7, #24]
        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
 8006dee:	69bb      	ldr	r3, [r7, #24]
 8006df0:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
 8006df4:	d308      	bcc.n	8006e08 <UART_SetConfig+0x380>
 8006df6:	69bb      	ldr	r3, [r7, #24]
 8006df8:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 8006dfc:	d204      	bcs.n	8006e08 <UART_SetConfig+0x380>
        {
          huart->Instance->BRR = usartdiv;
 8006dfe:	68fb      	ldr	r3, [r7, #12]
 8006e00:	681b      	ldr	r3, [r3, #0]
 8006e02:	69ba      	ldr	r2, [r7, #24]
 8006e04:	60da      	str	r2, [r3, #12]
 8006e06:	e0b5      	b.n	8006f74 <UART_SetConfig+0x4ec>
        }
        else
        {
          ret = HAL_ERROR;
 8006e08:	2301      	movs	r3, #1
 8006e0a:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
 8006e0e:	e0b1      	b.n	8006f74 <UART_SetConfig+0x4ec>
      } /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
#endif /* USART_PRESC_PRESCALER */
    } /* if (pclk != 0) */
  }
  /* Check UART Over Sampling to set Baud Rate Register */
  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
 8006e10:	68fb      	ldr	r3, [r7, #12]
 8006e12:	69db      	ldr	r3, [r3, #28]
 8006e14:	f5b3 4f00 	cmp.w	r3, #32768	@ 0x8000
 8006e18:	d15d      	bne.n	8006ed6 <UART_SetConfig+0x44e>
  {
    switch (clocksource)
 8006e1a:	f897 3023 	ldrb.w	r3, [r7, #35]	@ 0x23
 8006e1e:	2b08      	cmp	r3, #8
 8006e20:	d827      	bhi.n	8006e72 <UART_SetConfig+0x3ea>
 8006e22:	a201      	add	r2, pc, #4	@ (adr r2, 8006e28 <UART_SetConfig+0x3a0>)
 8006e24:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8006e28:	08006e4d 	.word	0x08006e4d
 8006e2c:	08006e55 	.word	0x08006e55
 8006e30:	08006e5d 	.word	0x08006e5d
 8006e34:	08006e73 	.word	0x08006e73
 8006e38:	08006e63 	.word	0x08006e63
 8006e3c:	08006e73 	.word	0x08006e73
 8006e40:	08006e73 	.word	0x08006e73
 8006e44:	08006e73 	.word	0x08006e73
 8006e48:	08006e6b 	.word	0x08006e6b
    {
      case UART_CLOCKSOURCE_PCLK1:
        pclk = HAL_RCC_GetPCLK1Freq();
 8006e4c:	f7ff f95a 	bl	8006104 <HAL_RCC_GetPCLK1Freq>
 8006e50:	61f8      	str	r0, [r7, #28]
        break;
 8006e52:	e014      	b.n	8006e7e <UART_SetConfig+0x3f6>
      case UART_CLOCKSOURCE_PCLK2:
        pclk = HAL_RCC_GetPCLK2Freq();
 8006e54:	f7ff f96c 	bl	8006130 <HAL_RCC_GetPCLK2Freq>
 8006e58:	61f8      	str	r0, [r7, #28]
        break;
 8006e5a:	e010      	b.n	8006e7e <UART_SetConfig+0x3f6>
      case UART_CLOCKSOURCE_HSI:
        pclk = (uint32_t) HSI_VALUE;
 8006e5c:	4b4c      	ldr	r3, [pc, #304]	@ (8006f90 <UART_SetConfig+0x508>)
 8006e5e:	61fb      	str	r3, [r7, #28]
        break;
 8006e60:	e00d      	b.n	8006e7e <UART_SetConfig+0x3f6>
      case UART_CLOCKSOURCE_SYSCLK:
        pclk = HAL_RCC_GetSysClockFreq();
 8006e62:	f7ff f8b7 	bl	8005fd4 <HAL_RCC_GetSysClockFreq>
 8006e66:	61f8      	str	r0, [r7, #28]
        break;
 8006e68:	e009      	b.n	8006e7e <UART_SetConfig+0x3f6>
      case UART_CLOCKSOURCE_LSE:
        pclk = (uint32_t) LSE_VALUE;
 8006e6a:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
 8006e6e:	61fb      	str	r3, [r7, #28]
        break;
 8006e70:	e005      	b.n	8006e7e <UART_SetConfig+0x3f6>
      default:
        pclk = 0U;
 8006e72:	2300      	movs	r3, #0
 8006e74:	61fb      	str	r3, [r7, #28]
        ret = HAL_ERROR;
 8006e76:	2301      	movs	r3, #1
 8006e78:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
        break;
 8006e7c:	bf00      	nop
    }

    /* USARTDIV must be greater than or equal to 0d16 */
    if (pclk != 0U)
 8006e7e:	69fb      	ldr	r3, [r7, #28]
 8006e80:	2b00      	cmp	r3, #0
 8006e82:	d077      	beq.n	8006f74 <UART_SetConfig+0x4ec>
    {
#if defined(USART_PRESC_PRESCALER)
      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
#else
      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
 8006e84:	69fb      	ldr	r3, [r7, #28]
 8006e86:	005a      	lsls	r2, r3, #1
 8006e88:	68fb      	ldr	r3, [r7, #12]
 8006e8a:	685b      	ldr	r3, [r3, #4]
 8006e8c:	085b      	lsrs	r3, r3, #1
 8006e8e:	441a      	add	r2, r3
 8006e90:	68fb      	ldr	r3, [r7, #12]
 8006e92:	685b      	ldr	r3, [r3, #4]
 8006e94:	fbb2 f3f3 	udiv	r3, r2, r3
 8006e98:	61bb      	str	r3, [r7, #24]
#endif /* USART_PRESC_PRESCALER */
      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
 8006e9a:	69bb      	ldr	r3, [r7, #24]
 8006e9c:	2b0f      	cmp	r3, #15
 8006e9e:	d916      	bls.n	8006ece <UART_SetConfig+0x446>
 8006ea0:	69bb      	ldr	r3, [r7, #24]
 8006ea2:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 8006ea6:	d212      	bcs.n	8006ece <UART_SetConfig+0x446>
      {
        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
 8006ea8:	69bb      	ldr	r3, [r7, #24]
 8006eaa:	b29b      	uxth	r3, r3
 8006eac:	f023 030f 	bic.w	r3, r3, #15
 8006eb0:	82fb      	strh	r3, [r7, #22]
        brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
 8006eb2:	69bb      	ldr	r3, [r7, #24]
 8006eb4:	085b      	lsrs	r3, r3, #1
 8006eb6:	b29b      	uxth	r3, r3
 8006eb8:	f003 0307 	and.w	r3, r3, #7
 8006ebc:	b29a      	uxth	r2, r3
 8006ebe:	8afb      	ldrh	r3, [r7, #22]
 8006ec0:	4313      	orrs	r3, r2
 8006ec2:	82fb      	strh	r3, [r7, #22]
        huart->Instance->BRR = brrtemp;
 8006ec4:	68fb      	ldr	r3, [r7, #12]
 8006ec6:	681b      	ldr	r3, [r3, #0]
 8006ec8:	8afa      	ldrh	r2, [r7, #22]
 8006eca:	60da      	str	r2, [r3, #12]
 8006ecc:	e052      	b.n	8006f74 <UART_SetConfig+0x4ec>
      }
      else
      {
        ret = HAL_ERROR;
 8006ece:	2301      	movs	r3, #1
 8006ed0:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
 8006ed4:	e04e      	b.n	8006f74 <UART_SetConfig+0x4ec>
      }
    }
  }
  else
  {
    switch (clocksource)
 8006ed6:	f897 3023 	ldrb.w	r3, [r7, #35]	@ 0x23
 8006eda:	2b08      	cmp	r3, #8
 8006edc:	d827      	bhi.n	8006f2e <UART_SetConfig+0x4a6>
 8006ede:	a201      	add	r2, pc, #4	@ (adr r2, 8006ee4 <UART_SetConfig+0x45c>)
 8006ee0:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8006ee4:	08006f09 	.word	0x08006f09
 8006ee8:	08006f11 	.word	0x08006f11
 8006eec:	08006f19 	.word	0x08006f19
 8006ef0:	08006f2f 	.word	0x08006f2f
 8006ef4:	08006f1f 	.word	0x08006f1f
 8006ef8:	08006f2f 	.word	0x08006f2f
 8006efc:	08006f2f 	.word	0x08006f2f
 8006f00:	08006f2f 	.word	0x08006f2f
 8006f04:	08006f27 	.word	0x08006f27
    {
      case UART_CLOCKSOURCE_PCLK1:
        pclk = HAL_RCC_GetPCLK1Freq();
 8006f08:	f7ff f8fc 	bl	8006104 <HAL_RCC_GetPCLK1Freq>
 8006f0c:	61f8      	str	r0, [r7, #28]
        break;
 8006f0e:	e014      	b.n	8006f3a <UART_SetConfig+0x4b2>
      case UART_CLOCKSOURCE_PCLK2:
        pclk = HAL_RCC_GetPCLK2Freq();
 8006f10:	f7ff f90e 	bl	8006130 <HAL_RCC_GetPCLK2Freq>
 8006f14:	61f8      	str	r0, [r7, #28]
        break;
 8006f16:	e010      	b.n	8006f3a <UART_SetConfig+0x4b2>
      case UART_CLOCKSOURCE_HSI:
        pclk = (uint32_t) HSI_VALUE;
 8006f18:	4b1d      	ldr	r3, [pc, #116]	@ (8006f90 <UART_SetConfig+0x508>)
 8006f1a:	61fb      	str	r3, [r7, #28]
        break;
 8006f1c:	e00d      	b.n	8006f3a <UART_SetConfig+0x4b2>
      case UART_CLOCKSOURCE_SYSCLK:
        pclk = HAL_RCC_GetSysClockFreq();
 8006f1e:	f7ff f859 	bl	8005fd4 <HAL_RCC_GetSysClockFreq>
 8006f22:	61f8      	str	r0, [r7, #28]
        break;
 8006f24:	e009      	b.n	8006f3a <UART_SetConfig+0x4b2>
      case UART_CLOCKSOURCE_LSE:
        pclk = (uint32_t) LSE_VALUE;
 8006f26:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
 8006f2a:	61fb      	str	r3, [r7, #28]
        break;
 8006f2c:	e005      	b.n	8006f3a <UART_SetConfig+0x4b2>
      default:
        pclk = 0U;
 8006f2e:	2300      	movs	r3, #0
 8006f30:	61fb      	str	r3, [r7, #28]
        ret = HAL_ERROR;
 8006f32:	2301      	movs	r3, #1
 8006f34:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
        break;
 8006f38:	bf00      	nop
    }

    if (pclk != 0U)
 8006f3a:	69fb      	ldr	r3, [r7, #28]
 8006f3c:	2b00      	cmp	r3, #0
 8006f3e:	d019      	beq.n	8006f74 <UART_SetConfig+0x4ec>
    {
      /* USARTDIV must be greater than or equal to 0d16 */
#if defined(USART_PRESC_PRESCALER)
      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
#else
      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
 8006f40:	68fb      	ldr	r3, [r7, #12]
 8006f42:	685b      	ldr	r3, [r3, #4]
 8006f44:	085a      	lsrs	r2, r3, #1
 8006f46:	69fb      	ldr	r3, [r7, #28]
 8006f48:	441a      	add	r2, r3
 8006f4a:	68fb      	ldr	r3, [r7, #12]
 8006f4c:	685b      	ldr	r3, [r3, #4]
 8006f4e:	fbb2 f3f3 	udiv	r3, r2, r3
 8006f52:	61bb      	str	r3, [r7, #24]
#endif /* USART_PRESC_PRESCALER */
      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
 8006f54:	69bb      	ldr	r3, [r7, #24]
 8006f56:	2b0f      	cmp	r3, #15
 8006f58:	d909      	bls.n	8006f6e <UART_SetConfig+0x4e6>
 8006f5a:	69bb      	ldr	r3, [r7, #24]
 8006f5c:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
 8006f60:	d205      	bcs.n	8006f6e <UART_SetConfig+0x4e6>
      {
        huart->Instance->BRR = (uint16_t)usartdiv;
 8006f62:	69bb      	ldr	r3, [r7, #24]
 8006f64:	b29a      	uxth	r2, r3
 8006f66:	68fb      	ldr	r3, [r7, #12]
 8006f68:	681b      	ldr	r3, [r3, #0]
 8006f6a:	60da      	str	r2, [r3, #12]
 8006f6c:	e002      	b.n	8006f74 <UART_SetConfig+0x4ec>
      }
      else
      {
        ret = HAL_ERROR;
 8006f6e:	2301      	movs	r3, #1
 8006f70:	f887 3022 	strb.w	r3, [r7, #34]	@ 0x22
  huart->NbTxDataToProcess = 1;
  huart->NbRxDataToProcess = 1;
#endif /* USART_CR1_FIFOEN */

  /* Clear ISR function pointers */
  huart->RxISR = NULL;
 8006f74:	68fb      	ldr	r3, [r7, #12]
 8006f76:	2200      	movs	r2, #0
 8006f78:	669a      	str	r2, [r3, #104]	@ 0x68
  huart->TxISR = NULL;
 8006f7a:	68fb      	ldr	r3, [r7, #12]
 8006f7c:	2200      	movs	r2, #0
 8006f7e:	66da      	str	r2, [r3, #108]	@ 0x6c

  return ret;
 8006f80:	f897 3022 	ldrb.w	r3, [r7, #34]	@ 0x22
}
 8006f84:	4618      	mov	r0, r3
 8006f86:	3728      	adds	r7, #40	@ 0x28
 8006f88:	46bd      	mov	sp, r7
 8006f8a:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
 8006f8e:	bf00      	nop
 8006f90:	00f42400 	.word	0x00f42400

08006f94 <UART_AdvFeatureConfig>:
  * @brief Configure the UART peripheral advanced features.
  * @param huart UART handle.
  * @retval None
  */
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
 8006f94:	b480      	push	{r7}
 8006f96:	b083      	sub	sp, #12
 8006f98:	af00      	add	r7, sp, #0
 8006f9a:	6078      	str	r0, [r7, #4]
  /* Check whether the set of advanced features to configure is properly set */
  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));

  /* if required, configure RX/TX pins swap */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
 8006f9c:	687b      	ldr	r3, [r7, #4]
 8006f9e:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8006fa0:	f003 0308 	and.w	r3, r3, #8
 8006fa4:	2b00      	cmp	r3, #0
 8006fa6:	d00a      	beq.n	8006fbe <UART_AdvFeatureConfig+0x2a>
  {
    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
 8006fa8:	687b      	ldr	r3, [r7, #4]
 8006faa:	681b      	ldr	r3, [r3, #0]
 8006fac:	685b      	ldr	r3, [r3, #4]
 8006fae:	f423 4100 	bic.w	r1, r3, #32768	@ 0x8000
 8006fb2:	687b      	ldr	r3, [r7, #4]
 8006fb4:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
 8006fb6:	687b      	ldr	r3, [r7, #4]
 8006fb8:	681b      	ldr	r3, [r3, #0]
 8006fba:	430a      	orrs	r2, r1
 8006fbc:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure TX pin active level inversion */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
 8006fbe:	687b      	ldr	r3, [r7, #4]
 8006fc0:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8006fc2:	f003 0301 	and.w	r3, r3, #1
 8006fc6:	2b00      	cmp	r3, #0
 8006fc8:	d00a      	beq.n	8006fe0 <UART_AdvFeatureConfig+0x4c>
  {
    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
 8006fca:	687b      	ldr	r3, [r7, #4]
 8006fcc:	681b      	ldr	r3, [r3, #0]
 8006fce:	685b      	ldr	r3, [r3, #4]
 8006fd0:	f423 3100 	bic.w	r1, r3, #131072	@ 0x20000
 8006fd4:	687b      	ldr	r3, [r7, #4]
 8006fd6:	6a9a      	ldr	r2, [r3, #40]	@ 0x28
 8006fd8:	687b      	ldr	r3, [r7, #4]
 8006fda:	681b      	ldr	r3, [r3, #0]
 8006fdc:	430a      	orrs	r2, r1
 8006fde:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure RX pin active level inversion */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
 8006fe0:	687b      	ldr	r3, [r7, #4]
 8006fe2:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8006fe4:	f003 0302 	and.w	r3, r3, #2
 8006fe8:	2b00      	cmp	r3, #0
 8006fea:	d00a      	beq.n	8007002 <UART_AdvFeatureConfig+0x6e>
  {
    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
 8006fec:	687b      	ldr	r3, [r7, #4]
 8006fee:	681b      	ldr	r3, [r3, #0]
 8006ff0:	685b      	ldr	r3, [r3, #4]
 8006ff2:	f423 3180 	bic.w	r1, r3, #65536	@ 0x10000
 8006ff6:	687b      	ldr	r3, [r7, #4]
 8006ff8:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
 8006ffa:	687b      	ldr	r3, [r7, #4]
 8006ffc:	681b      	ldr	r3, [r3, #0]
 8006ffe:	430a      	orrs	r2, r1
 8007000:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure data inversion */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
 8007002:	687b      	ldr	r3, [r7, #4]
 8007004:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8007006:	f003 0304 	and.w	r3, r3, #4
 800700a:	2b00      	cmp	r3, #0
 800700c:	d00a      	beq.n	8007024 <UART_AdvFeatureConfig+0x90>
  {
    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
 800700e:	687b      	ldr	r3, [r7, #4]
 8007010:	681b      	ldr	r3, [r3, #0]
 8007012:	685b      	ldr	r3, [r3, #4]
 8007014:	f423 2180 	bic.w	r1, r3, #262144	@ 0x40000
 8007018:	687b      	ldr	r3, [r7, #4]
 800701a:	6b1a      	ldr	r2, [r3, #48]	@ 0x30
 800701c:	687b      	ldr	r3, [r7, #4]
 800701e:	681b      	ldr	r3, [r3, #0]
 8007020:	430a      	orrs	r2, r1
 8007022:	605a      	str	r2, [r3, #4]
  }

  /* if required, configure RX overrun detection disabling */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
 8007024:	687b      	ldr	r3, [r7, #4]
 8007026:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 8007028:	f003 0310 	and.w	r3, r3, #16
 800702c:	2b00      	cmp	r3, #0
 800702e:	d00a      	beq.n	8007046 <UART_AdvFeatureConfig+0xb2>
  {
    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
 8007030:	687b      	ldr	r3, [r7, #4]
 8007032:	681b      	ldr	r3, [r3, #0]
 8007034:	689b      	ldr	r3, [r3, #8]
 8007036:	f423 5180 	bic.w	r1, r3, #4096	@ 0x1000
 800703a:	687b      	ldr	r3, [r7, #4]
 800703c:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
 800703e:	687b      	ldr	r3, [r7, #4]
 8007040:	681b      	ldr	r3, [r3, #0]
 8007042:	430a      	orrs	r2, r1
 8007044:	609a      	str	r2, [r3, #8]
  }

  /* if required, configure DMA disabling on reception error */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
 8007046:	687b      	ldr	r3, [r7, #4]
 8007048:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800704a:	f003 0320 	and.w	r3, r3, #32
 800704e:	2b00      	cmp	r3, #0
 8007050:	d00a      	beq.n	8007068 <UART_AdvFeatureConfig+0xd4>
  {
    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
 8007052:	687b      	ldr	r3, [r7, #4]
 8007054:	681b      	ldr	r3, [r3, #0]
 8007056:	689b      	ldr	r3, [r3, #8]
 8007058:	f423 5100 	bic.w	r1, r3, #8192	@ 0x2000
 800705c:	687b      	ldr	r3, [r7, #4]
 800705e:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
 8007060:	687b      	ldr	r3, [r7, #4]
 8007062:	681b      	ldr	r3, [r3, #0]
 8007064:	430a      	orrs	r2, r1
 8007066:	609a      	str	r2, [r3, #8]
  }

  /* if required, configure auto Baud rate detection scheme */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
 8007068:	687b      	ldr	r3, [r7, #4]
 800706a:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 800706c:	f003 0340 	and.w	r3, r3, #64	@ 0x40
 8007070:	2b00      	cmp	r3, #0
 8007072:	d01a      	beq.n	80070aa <UART_AdvFeatureConfig+0x116>
  {
    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
 8007074:	687b      	ldr	r3, [r7, #4]
 8007076:	681b      	ldr	r3, [r3, #0]
 8007078:	685b      	ldr	r3, [r3, #4]
 800707a:	f423 1180 	bic.w	r1, r3, #1048576	@ 0x100000
 800707e:	687b      	ldr	r3, [r7, #4]
 8007080:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
 8007082:	687b      	ldr	r3, [r7, #4]
 8007084:	681b      	ldr	r3, [r3, #0]
 8007086:	430a      	orrs	r2, r1
 8007088:	605a      	str	r2, [r3, #4]
    /* set auto Baudrate detection parameters if detection is enabled */
    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
 800708a:	687b      	ldr	r3, [r7, #4]
 800708c:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
 800708e:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
 8007092:	d10a      	bne.n	80070aa <UART_AdvFeatureConfig+0x116>
    {
      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
 8007094:	687b      	ldr	r3, [r7, #4]
 8007096:	681b      	ldr	r3, [r3, #0]
 8007098:	685b      	ldr	r3, [r3, #4]
 800709a:	f423 01c0 	bic.w	r1, r3, #6291456	@ 0x600000
 800709e:	687b      	ldr	r3, [r7, #4]
 80070a0:	6c5a      	ldr	r2, [r3, #68]	@ 0x44
 80070a2:	687b      	ldr	r3, [r7, #4]
 80070a4:	681b      	ldr	r3, [r3, #0]
 80070a6:	430a      	orrs	r2, r1
 80070a8:	605a      	str	r2, [r3, #4]
    }
  }

  /* if required, configure MSB first on communication line */
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
 80070aa:	687b      	ldr	r3, [r7, #4]
 80070ac:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
 80070ae:	f003 0380 	and.w	r3, r3, #128	@ 0x80
 80070b2:	2b00      	cmp	r3, #0
 80070b4:	d00a      	beq.n	80070cc <UART_AdvFeatureConfig+0x138>
  {
    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
 80070b6:	687b      	ldr	r3, [r7, #4]
 80070b8:	681b      	ldr	r3, [r3, #0]
 80070ba:	685b      	ldr	r3, [r3, #4]
 80070bc:	f423 2100 	bic.w	r1, r3, #524288	@ 0x80000
 80070c0:	687b      	ldr	r3, [r7, #4]
 80070c2:	6c9a      	ldr	r2, [r3, #72]	@ 0x48
 80070c4:	687b      	ldr	r3, [r7, #4]
 80070c6:	681b      	ldr	r3, [r3, #0]
 80070c8:	430a      	orrs	r2, r1
 80070ca:	605a      	str	r2, [r3, #4]
  }
}
 80070cc:	bf00      	nop
 80070ce:	370c      	adds	r7, #12
 80070d0:	46bd      	mov	sp, r7
 80070d2:	f85d 7b04 	ldr.w	r7, [sp], #4
 80070d6:	4770      	bx	lr

080070d8 <UART_CheckIdleState>:
  * @brief Check the UART Idle State.
  * @param huart UART handle.
  * @retval HAL status
  */
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
 80070d8:	b580      	push	{r7, lr}
 80070da:	b098      	sub	sp, #96	@ 0x60
 80070dc:	af02      	add	r7, sp, #8
 80070de:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;

  /* Initialize the UART ErrorCode */
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 80070e0:	687b      	ldr	r3, [r7, #4]
 80070e2:	2200      	movs	r2, #0
 80070e4:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84

  /* Init tickstart for timeout management */
  tickstart = HAL_GetTick();
 80070e8:	f7fd f818 	bl	800411c <HAL_GetTick>
 80070ec:	6578      	str	r0, [r7, #84]	@ 0x54

  /* Check if the Transmitter is enabled */
  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
 80070ee:	687b      	ldr	r3, [r7, #4]
 80070f0:	681b      	ldr	r3, [r3, #0]
 80070f2:	681b      	ldr	r3, [r3, #0]
 80070f4:	f003 0308 	and.w	r3, r3, #8
 80070f8:	2b08      	cmp	r3, #8
 80070fa:	d12e      	bne.n	800715a <UART_CheckIdleState+0x82>
  {
    /* Wait until TEACK flag is set */
    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
 80070fc:	f06f 437e 	mvn.w	r3, #4261412864	@ 0xfe000000
 8007100:	9300      	str	r3, [sp, #0]
 8007102:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 8007104:	2200      	movs	r2, #0
 8007106:	f44f 1100 	mov.w	r1, #2097152	@ 0x200000
 800710a:	6878      	ldr	r0, [r7, #4]
 800710c:	f000 f88c 	bl	8007228 <UART_WaitOnFlagUntilTimeout>
 8007110:	4603      	mov	r3, r0
 8007112:	2b00      	cmp	r3, #0
 8007114:	d021      	beq.n	800715a <UART_CheckIdleState+0x82>
    {
      /* Disable TXE interrupt for the interrupt process */
#if defined(USART_CR1_FIFOEN)
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
#else
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
 8007116:	687b      	ldr	r3, [r7, #4]
 8007118:	681b      	ldr	r3, [r3, #0]
 800711a:	63bb      	str	r3, [r7, #56]	@ 0x38
 */
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
    uint32_t result;

   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800711c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 800711e:	e853 3f00 	ldrex	r3, [r3]
 8007122:	637b      	str	r3, [r7, #52]	@ 0x34
   return(result);
 8007124:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8007126:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
 800712a:	653b      	str	r3, [r7, #80]	@ 0x50
 800712c:	687b      	ldr	r3, [r7, #4]
 800712e:	681b      	ldr	r3, [r3, #0]
 8007130:	461a      	mov	r2, r3
 8007132:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
 8007134:	647b      	str	r3, [r7, #68]	@ 0x44
 8007136:	643a      	str	r2, [r7, #64]	@ 0x40
 */
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
   uint32_t result;

   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8007138:	6c39      	ldr	r1, [r7, #64]	@ 0x40
 800713a:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
 800713c:	e841 2300 	strex	r3, r2, [r1]
 8007140:	63fb      	str	r3, [r7, #60]	@ 0x3c
   return(result);
 8007142:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
 8007144:	2b00      	cmp	r3, #0
 8007146:	d1e6      	bne.n	8007116 <UART_CheckIdleState+0x3e>
#endif /* USART_CR1_FIFOEN */

      huart->gState = HAL_UART_STATE_READY;
 8007148:	687b      	ldr	r3, [r7, #4]
 800714a:	2220      	movs	r2, #32
 800714c:	67da      	str	r2, [r3, #124]	@ 0x7c

      __HAL_UNLOCK(huart);
 800714e:	687b      	ldr	r3, [r7, #4]
 8007150:	2200      	movs	r2, #0
 8007152:	f883 2078 	strb.w	r2, [r3, #120]	@ 0x78

      /* Timeout occurred */
      return HAL_TIMEOUT;
 8007156:	2303      	movs	r3, #3
 8007158:	e062      	b.n	8007220 <UART_CheckIdleState+0x148>
    }
  }

  /* Check if the Receiver is enabled */
  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
 800715a:	687b      	ldr	r3, [r7, #4]
 800715c:	681b      	ldr	r3, [r3, #0]
 800715e:	681b      	ldr	r3, [r3, #0]
 8007160:	f003 0304 	and.w	r3, r3, #4
 8007164:	2b04      	cmp	r3, #4
 8007166:	d149      	bne.n	80071fc <UART_CheckIdleState+0x124>
  {
    /* Wait until REACK flag is set */
    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
 8007168:	f06f 437e 	mvn.w	r3, #4261412864	@ 0xfe000000
 800716c:	9300      	str	r3, [sp, #0]
 800716e:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
 8007170:	2200      	movs	r2, #0
 8007172:	f44f 0180 	mov.w	r1, #4194304	@ 0x400000
 8007176:	6878      	ldr	r0, [r7, #4]
 8007178:	f000 f856 	bl	8007228 <UART_WaitOnFlagUntilTimeout>
 800717c:	4603      	mov	r3, r0
 800717e:	2b00      	cmp	r3, #0
 8007180:	d03c      	beq.n	80071fc <UART_CheckIdleState+0x124>
      /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
      interrupts for the interrupt process */
#if defined(USART_CR1_FIFOEN)
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
#else
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 8007182:	687b      	ldr	r3, [r7, #4]
 8007184:	681b      	ldr	r3, [r3, #0]
 8007186:	627b      	str	r3, [r7, #36]	@ 0x24
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8007188:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800718a:	e853 3f00 	ldrex	r3, [r3]
 800718e:	623b      	str	r3, [r7, #32]
   return(result);
 8007190:	6a3b      	ldr	r3, [r7, #32]
 8007192:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
 8007196:	64fb      	str	r3, [r7, #76]	@ 0x4c
 8007198:	687b      	ldr	r3, [r7, #4]
 800719a:	681b      	ldr	r3, [r3, #0]
 800719c:	461a      	mov	r2, r3
 800719e:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 80071a0:	633b      	str	r3, [r7, #48]	@ 0x30
 80071a2:	62fa      	str	r2, [r7, #44]	@ 0x2c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80071a4:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
 80071a6:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
 80071a8:	e841 2300 	strex	r3, r2, [r1]
 80071ac:	62bb      	str	r3, [r7, #40]	@ 0x28
   return(result);
 80071ae:	6abb      	ldr	r3, [r7, #40]	@ 0x28
 80071b0:	2b00      	cmp	r3, #0
 80071b2:	d1e6      	bne.n	8007182 <UART_CheckIdleState+0xaa>
#endif /* USART_CR1_FIFOEN */
      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 80071b4:	687b      	ldr	r3, [r7, #4]
 80071b6:	681b      	ldr	r3, [r3, #0]
 80071b8:	3308      	adds	r3, #8
 80071ba:	613b      	str	r3, [r7, #16]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80071bc:	693b      	ldr	r3, [r7, #16]
 80071be:	e853 3f00 	ldrex	r3, [r3]
 80071c2:	60fb      	str	r3, [r7, #12]
   return(result);
 80071c4:	68fb      	ldr	r3, [r7, #12]
 80071c6:	f023 0301 	bic.w	r3, r3, #1
 80071ca:	64bb      	str	r3, [r7, #72]	@ 0x48
 80071cc:	687b      	ldr	r3, [r7, #4]
 80071ce:	681b      	ldr	r3, [r3, #0]
 80071d0:	3308      	adds	r3, #8
 80071d2:	6cba      	ldr	r2, [r7, #72]	@ 0x48
 80071d4:	61fa      	str	r2, [r7, #28]
 80071d6:	61bb      	str	r3, [r7, #24]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 80071d8:	69b9      	ldr	r1, [r7, #24]
 80071da:	69fa      	ldr	r2, [r7, #28]
 80071dc:	e841 2300 	strex	r3, r2, [r1]
 80071e0:	617b      	str	r3, [r7, #20]
   return(result);
 80071e2:	697b      	ldr	r3, [r7, #20]
 80071e4:	2b00      	cmp	r3, #0
 80071e6:	d1e5      	bne.n	80071b4 <UART_CheckIdleState+0xdc>

      huart->RxState = HAL_UART_STATE_READY;
 80071e8:	687b      	ldr	r3, [r7, #4]
 80071ea:	2220      	movs	r2, #32
 80071ec:	f8c3 2080 	str.w	r2, [r3, #128]	@ 0x80

      __HAL_UNLOCK(huart);
 80071f0:	687b      	ldr	r3, [r7, #4]
 80071f2:	2200      	movs	r2, #0
 80071f4:	f883 2078 	strb.w	r2, [r3, #120]	@ 0x78

      /* Timeout occurred */
      return HAL_TIMEOUT;
 80071f8:	2303      	movs	r3, #3
 80071fa:	e011      	b.n	8007220 <UART_CheckIdleState+0x148>
    }
  }

  /* Initialize the UART State */
  huart->gState = HAL_UART_STATE_READY;
 80071fc:	687b      	ldr	r3, [r7, #4]
 80071fe:	2220      	movs	r2, #32
 8007200:	67da      	str	r2, [r3, #124]	@ 0x7c
  huart->RxState = HAL_UART_STATE_READY;
 8007202:	687b      	ldr	r3, [r7, #4]
 8007204:	2220      	movs	r2, #32
 8007206:	f8c3 2080 	str.w	r2, [r3, #128]	@ 0x80
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 800720a:	687b      	ldr	r3, [r7, #4]
 800720c:	2200      	movs	r2, #0
 800720e:	661a      	str	r2, [r3, #96]	@ 0x60
  huart->RxEventType = HAL_UART_RXEVENT_TC;
 8007210:	687b      	ldr	r3, [r7, #4]
 8007212:	2200      	movs	r2, #0
 8007214:	665a      	str	r2, [r3, #100]	@ 0x64

  __HAL_UNLOCK(huart);
 8007216:	687b      	ldr	r3, [r7, #4]
 8007218:	2200      	movs	r2, #0
 800721a:	f883 2078 	strb.w	r2, [r3, #120]	@ 0x78

  return HAL_OK;
 800721e:	2300      	movs	r3, #0
}
 8007220:	4618      	mov	r0, r3
 8007222:	3758      	adds	r7, #88	@ 0x58
 8007224:	46bd      	mov	sp, r7
 8007226:	bd80      	pop	{r7, pc}

08007228 <UART_WaitOnFlagUntilTimeout>:
  * @param Timeout   Timeout duration
  * @retval HAL status
  */
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
                                              uint32_t Tickstart, uint32_t Timeout)
{
 8007228:	b580      	push	{r7, lr}
 800722a:	b084      	sub	sp, #16
 800722c:	af00      	add	r7, sp, #0
 800722e:	60f8      	str	r0, [r7, #12]
 8007230:	60b9      	str	r1, [r7, #8]
 8007232:	603b      	str	r3, [r7, #0]
 8007234:	4613      	mov	r3, r2
 8007236:	71fb      	strb	r3, [r7, #7]
  /* Wait until flag is set */
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 8007238:	e04f      	b.n	80072da <UART_WaitOnFlagUntilTimeout+0xb2>
  {
    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 800723a:	69bb      	ldr	r3, [r7, #24]
 800723c:	f1b3 3fff 	cmp.w	r3, #4294967295
 8007240:	d04b      	beq.n	80072da <UART_WaitOnFlagUntilTimeout+0xb2>
    {
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 8007242:	f7fc ff6b 	bl	800411c <HAL_GetTick>
 8007246:	4602      	mov	r2, r0
 8007248:	683b      	ldr	r3, [r7, #0]
 800724a:	1ad3      	subs	r3, r2, r3
 800724c:	69ba      	ldr	r2, [r7, #24]
 800724e:	429a      	cmp	r2, r3
 8007250:	d302      	bcc.n	8007258 <UART_WaitOnFlagUntilTimeout+0x30>
 8007252:	69bb      	ldr	r3, [r7, #24]
 8007254:	2b00      	cmp	r3, #0
 8007256:	d101      	bne.n	800725c <UART_WaitOnFlagUntilTimeout+0x34>
      {

        return HAL_TIMEOUT;
 8007258:	2303      	movs	r3, #3
 800725a:	e04e      	b.n	80072fa <UART_WaitOnFlagUntilTimeout+0xd2>
      }

      if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
 800725c:	68fb      	ldr	r3, [r7, #12]
 800725e:	681b      	ldr	r3, [r3, #0]
 8007260:	681b      	ldr	r3, [r3, #0]
 8007262:	f003 0304 	and.w	r3, r3, #4
 8007266:	2b00      	cmp	r3, #0
 8007268:	d037      	beq.n	80072da <UART_WaitOnFlagUntilTimeout+0xb2>
 800726a:	68bb      	ldr	r3, [r7, #8]
 800726c:	2b80      	cmp	r3, #128	@ 0x80
 800726e:	d034      	beq.n	80072da <UART_WaitOnFlagUntilTimeout+0xb2>
 8007270:	68bb      	ldr	r3, [r7, #8]
 8007272:	2b40      	cmp	r3, #64	@ 0x40
 8007274:	d031      	beq.n	80072da <UART_WaitOnFlagUntilTimeout+0xb2>
      {
        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
 8007276:	68fb      	ldr	r3, [r7, #12]
 8007278:	681b      	ldr	r3, [r3, #0]
 800727a:	69db      	ldr	r3, [r3, #28]
 800727c:	f003 0308 	and.w	r3, r3, #8
 8007280:	2b08      	cmp	r3, #8
 8007282:	d110      	bne.n	80072a6 <UART_WaitOnFlagUntilTimeout+0x7e>
        {
          /* Clear Overrun Error flag*/
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
 8007284:	68fb      	ldr	r3, [r7, #12]
 8007286:	681b      	ldr	r3, [r3, #0]
 8007288:	2208      	movs	r2, #8
 800728a:	621a      	str	r2, [r3, #32]

          /* Blocking error : transfer is aborted
          Set the UART state ready to be able to start again the process,
          Disable Rx Interrupts if ongoing */
          UART_EndRxTransfer(huart);
 800728c:	68f8      	ldr	r0, [r7, #12]
 800728e:	f000 f838 	bl	8007302 <UART_EndRxTransfer>

          huart->ErrorCode = HAL_UART_ERROR_ORE;
 8007292:	68fb      	ldr	r3, [r7, #12]
 8007294:	2208      	movs	r2, #8
 8007296:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84

          /* Process Unlocked */
          __HAL_UNLOCK(huart);
 800729a:	68fb      	ldr	r3, [r7, #12]
 800729c:	2200      	movs	r2, #0
 800729e:	f883 2078 	strb.w	r2, [r3, #120]	@ 0x78

          return HAL_ERROR;
 80072a2:	2301      	movs	r3, #1
 80072a4:	e029      	b.n	80072fa <UART_WaitOnFlagUntilTimeout+0xd2>
        }
        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
 80072a6:	68fb      	ldr	r3, [r7, #12]
 80072a8:	681b      	ldr	r3, [r3, #0]
 80072aa:	69db      	ldr	r3, [r3, #28]
 80072ac:	f403 6300 	and.w	r3, r3, #2048	@ 0x800
 80072b0:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
 80072b4:	d111      	bne.n	80072da <UART_WaitOnFlagUntilTimeout+0xb2>
        {
          /* Clear Receiver Timeout flag*/
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
 80072b6:	68fb      	ldr	r3, [r7, #12]
 80072b8:	681b      	ldr	r3, [r3, #0]
 80072ba:	f44f 6200 	mov.w	r2, #2048	@ 0x800
 80072be:	621a      	str	r2, [r3, #32]

          /* Blocking error : transfer is aborted
          Set the UART state ready to be able to start again the process,
          Disable Rx Interrupts if ongoing */
          UART_EndRxTransfer(huart);
 80072c0:	68f8      	ldr	r0, [r7, #12]
 80072c2:	f000 f81e 	bl	8007302 <UART_EndRxTransfer>

          huart->ErrorCode = HAL_UART_ERROR_RTO;
 80072c6:	68fb      	ldr	r3, [r7, #12]
 80072c8:	2220      	movs	r2, #32
 80072ca:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84

          /* Process Unlocked */
          __HAL_UNLOCK(huart);
 80072ce:	68fb      	ldr	r3, [r7, #12]
 80072d0:	2200      	movs	r2, #0
 80072d2:	f883 2078 	strb.w	r2, [r3, #120]	@ 0x78

          return HAL_TIMEOUT;
 80072d6:	2303      	movs	r3, #3
 80072d8:	e00f      	b.n	80072fa <UART_WaitOnFlagUntilTimeout+0xd2>
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 80072da:	68fb      	ldr	r3, [r7, #12]
 80072dc:	681b      	ldr	r3, [r3, #0]
 80072de:	69da      	ldr	r2, [r3, #28]
 80072e0:	68bb      	ldr	r3, [r7, #8]
 80072e2:	4013      	ands	r3, r2
 80072e4:	68ba      	ldr	r2, [r7, #8]
 80072e6:	429a      	cmp	r2, r3
 80072e8:	bf0c      	ite	eq
 80072ea:	2301      	moveq	r3, #1
 80072ec:	2300      	movne	r3, #0
 80072ee:	b2db      	uxtb	r3, r3
 80072f0:	461a      	mov	r2, r3
 80072f2:	79fb      	ldrb	r3, [r7, #7]
 80072f4:	429a      	cmp	r2, r3
 80072f6:	d0a0      	beq.n	800723a <UART_WaitOnFlagUntilTimeout+0x12>
        }
      }
    }
  }
  return HAL_OK;
 80072f8:	2300      	movs	r3, #0
}
 80072fa:	4618      	mov	r0, r3
 80072fc:	3710      	adds	r7, #16
 80072fe:	46bd      	mov	sp, r7
 8007300:	bd80      	pop	{r7, pc}

08007302 <UART_EndRxTransfer>:
  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
  * @param  huart UART handle.
  * @retval None
  */
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
 8007302:	b480      	push	{r7}
 8007304:	b095      	sub	sp, #84	@ 0x54
 8007306:	af00      	add	r7, sp, #0
 8007308:	6078      	str	r0, [r7, #4]
  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
#if defined(USART_CR1_FIFOEN)
  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
#else
  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 800730a:	687b      	ldr	r3, [r7, #4]
 800730c:	681b      	ldr	r3, [r3, #0]
 800730e:	637b      	str	r3, [r7, #52]	@ 0x34
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8007310:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
 8007312:	e853 3f00 	ldrex	r3, [r3]
 8007316:	633b      	str	r3, [r7, #48]	@ 0x30
   return(result);
 8007318:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
 800731a:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
 800731e:	64fb      	str	r3, [r7, #76]	@ 0x4c
 8007320:	687b      	ldr	r3, [r7, #4]
 8007322:	681b      	ldr	r3, [r3, #0]
 8007324:	461a      	mov	r2, r3
 8007326:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
 8007328:	643b      	str	r3, [r7, #64]	@ 0x40
 800732a:	63fa      	str	r2, [r7, #60]	@ 0x3c
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800732c:	6bf9      	ldr	r1, [r7, #60]	@ 0x3c
 800732e:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
 8007330:	e841 2300 	strex	r3, r2, [r1]
 8007334:	63bb      	str	r3, [r7, #56]	@ 0x38
   return(result);
 8007336:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
 8007338:	2b00      	cmp	r3, #0
 800733a:	d1e6      	bne.n	800730a <UART_EndRxTransfer+0x8>
  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 800733c:	687b      	ldr	r3, [r7, #4]
 800733e:	681b      	ldr	r3, [r3, #0]
 8007340:	3308      	adds	r3, #8
 8007342:	623b      	str	r3, [r7, #32]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8007344:	6a3b      	ldr	r3, [r7, #32]
 8007346:	e853 3f00 	ldrex	r3, [r3]
 800734a:	61fb      	str	r3, [r7, #28]
   return(result);
 800734c:	69fb      	ldr	r3, [r7, #28]
 800734e:	f023 0301 	bic.w	r3, r3, #1
 8007352:	64bb      	str	r3, [r7, #72]	@ 0x48
 8007354:	687b      	ldr	r3, [r7, #4]
 8007356:	681b      	ldr	r3, [r3, #0]
 8007358:	3308      	adds	r3, #8
 800735a:	6cba      	ldr	r2, [r7, #72]	@ 0x48
 800735c:	62fa      	str	r2, [r7, #44]	@ 0x2c
 800735e:	62bb      	str	r3, [r7, #40]	@ 0x28
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8007360:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
 8007362:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
 8007364:	e841 2300 	strex	r3, r2, [r1]
 8007368:	627b      	str	r3, [r7, #36]	@ 0x24
   return(result);
 800736a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
 800736c:	2b00      	cmp	r3, #0
 800736e:	d1e5      	bne.n	800733c <UART_EndRxTransfer+0x3a>
#endif /* USART_CR1_FIFOEN */

  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 8007370:	687b      	ldr	r3, [r7, #4]
 8007372:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
 8007374:	2b01      	cmp	r3, #1
 8007376:	d118      	bne.n	80073aa <UART_EndRxTransfer+0xa8>
  {
    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 8007378:	687b      	ldr	r3, [r7, #4]
 800737a:	681b      	ldr	r3, [r3, #0]
 800737c:	60fb      	str	r3, [r7, #12]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 800737e:	68fb      	ldr	r3, [r7, #12]
 8007380:	e853 3f00 	ldrex	r3, [r3]
 8007384:	60bb      	str	r3, [r7, #8]
   return(result);
 8007386:	68bb      	ldr	r3, [r7, #8]
 8007388:	f023 0310 	bic.w	r3, r3, #16
 800738c:	647b      	str	r3, [r7, #68]	@ 0x44
 800738e:	687b      	ldr	r3, [r7, #4]
 8007390:	681b      	ldr	r3, [r3, #0]
 8007392:	461a      	mov	r2, r3
 8007394:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
 8007396:	61bb      	str	r3, [r7, #24]
 8007398:	617a      	str	r2, [r7, #20]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 800739a:	6979      	ldr	r1, [r7, #20]
 800739c:	69ba      	ldr	r2, [r7, #24]
 800739e:	e841 2300 	strex	r3, r2, [r1]
 80073a2:	613b      	str	r3, [r7, #16]
   return(result);
 80073a4:	693b      	ldr	r3, [r7, #16]
 80073a6:	2b00      	cmp	r3, #0
 80073a8:	d1e6      	bne.n	8007378 <UART_EndRxTransfer+0x76>
  }

  /* At end of Rx process, restore huart->RxState to Ready */
  huart->RxState = HAL_UART_STATE_READY;
 80073aa:	687b      	ldr	r3, [r7, #4]
 80073ac:	2220      	movs	r2, #32
 80073ae:	f8c3 2080 	str.w	r2, [r3, #128]	@ 0x80
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 80073b2:	687b      	ldr	r3, [r7, #4]
 80073b4:	2200      	movs	r2, #0
 80073b6:	661a      	str	r2, [r3, #96]	@ 0x60

  /* Reset RxIsr function pointer */
  huart->RxISR = NULL;
 80073b8:	687b      	ldr	r3, [r7, #4]
 80073ba:	2200      	movs	r2, #0
 80073bc:	669a      	str	r2, [r3, #104]	@ 0x68
}
 80073be:	bf00      	nop
 80073c0:	3754      	adds	r7, #84	@ 0x54
 80073c2:	46bd      	mov	sp, r7
 80073c4:	f85d 7b04 	ldr.w	r7, [sp], #4
 80073c8:	4770      	bx	lr

080073ca <__cvt>:
 80073ca:	e92d 47ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
 80073ce:	ec57 6b10 	vmov	r6, r7, d0
 80073d2:	2f00      	cmp	r7, #0
 80073d4:	460c      	mov	r4, r1
 80073d6:	4619      	mov	r1, r3
 80073d8:	463b      	mov	r3, r7
 80073da:	bfbb      	ittet	lt
 80073dc:	f107 4300 	addlt.w	r3, r7, #2147483648	@ 0x80000000
 80073e0:	461f      	movlt	r7, r3
 80073e2:	2300      	movge	r3, #0
 80073e4:	232d      	movlt	r3, #45	@ 0x2d
 80073e6:	700b      	strb	r3, [r1, #0]
 80073e8:	9b0d      	ldr	r3, [sp, #52]	@ 0x34
 80073ea:	f8dd a030 	ldr.w	sl, [sp, #48]	@ 0x30
 80073ee:	4691      	mov	r9, r2
 80073f0:	f023 0820 	bic.w	r8, r3, #32
 80073f4:	bfbc      	itt	lt
 80073f6:	4632      	movlt	r2, r6
 80073f8:	4616      	movlt	r6, r2
 80073fa:	f1b8 0f46 	cmp.w	r8, #70	@ 0x46
 80073fe:	d005      	beq.n	800740c <__cvt+0x42>
 8007400:	f1b8 0f45 	cmp.w	r8, #69	@ 0x45
 8007404:	d100      	bne.n	8007408 <__cvt+0x3e>
 8007406:	3401      	adds	r4, #1
 8007408:	2102      	movs	r1, #2
 800740a:	e000      	b.n	800740e <__cvt+0x44>
 800740c:	2103      	movs	r1, #3
 800740e:	ab03      	add	r3, sp, #12
 8007410:	9301      	str	r3, [sp, #4]
 8007412:	ab02      	add	r3, sp, #8
 8007414:	9300      	str	r3, [sp, #0]
 8007416:	ec47 6b10 	vmov	d0, r6, r7
 800741a:	4653      	mov	r3, sl
 800741c:	4622      	mov	r2, r4
 800741e:	f000 fe7f 	bl	8008120 <_dtoa_r>
 8007422:	f1b8 0f47 	cmp.w	r8, #71	@ 0x47
 8007426:	4605      	mov	r5, r0
 8007428:	d119      	bne.n	800745e <__cvt+0x94>
 800742a:	f019 0f01 	tst.w	r9, #1
 800742e:	d00e      	beq.n	800744e <__cvt+0x84>
 8007430:	eb00 0904 	add.w	r9, r0, r4
 8007434:	2200      	movs	r2, #0
 8007436:	2300      	movs	r3, #0
 8007438:	4630      	mov	r0, r6
 800743a:	4639      	mov	r1, r7
 800743c:	f7f9 fb4c 	bl	8000ad8 <__aeabi_dcmpeq>
 8007440:	b108      	cbz	r0, 8007446 <__cvt+0x7c>
 8007442:	f8cd 900c 	str.w	r9, [sp, #12]
 8007446:	2230      	movs	r2, #48	@ 0x30
 8007448:	9b03      	ldr	r3, [sp, #12]
 800744a:	454b      	cmp	r3, r9
 800744c:	d31e      	bcc.n	800748c <__cvt+0xc2>
 800744e:	9b03      	ldr	r3, [sp, #12]
 8007450:	9a0e      	ldr	r2, [sp, #56]	@ 0x38
 8007452:	1b5b      	subs	r3, r3, r5
 8007454:	4628      	mov	r0, r5
 8007456:	6013      	str	r3, [r2, #0]
 8007458:	b004      	add	sp, #16
 800745a:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 800745e:	f1b8 0f46 	cmp.w	r8, #70	@ 0x46
 8007462:	eb00 0904 	add.w	r9, r0, r4
 8007466:	d1e5      	bne.n	8007434 <__cvt+0x6a>
 8007468:	7803      	ldrb	r3, [r0, #0]
 800746a:	2b30      	cmp	r3, #48	@ 0x30
 800746c:	d10a      	bne.n	8007484 <__cvt+0xba>
 800746e:	2200      	movs	r2, #0
 8007470:	2300      	movs	r3, #0
 8007472:	4630      	mov	r0, r6
 8007474:	4639      	mov	r1, r7
 8007476:	f7f9 fb2f 	bl	8000ad8 <__aeabi_dcmpeq>
 800747a:	b918      	cbnz	r0, 8007484 <__cvt+0xba>
 800747c:	f1c4 0401 	rsb	r4, r4, #1
 8007480:	f8ca 4000 	str.w	r4, [sl]
 8007484:	f8da 3000 	ldr.w	r3, [sl]
 8007488:	4499      	add	r9, r3
 800748a:	e7d3      	b.n	8007434 <__cvt+0x6a>
 800748c:	1c59      	adds	r1, r3, #1
 800748e:	9103      	str	r1, [sp, #12]
 8007490:	701a      	strb	r2, [r3, #0]
 8007492:	e7d9      	b.n	8007448 <__cvt+0x7e>

08007494 <__exponent>:
 8007494:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
 8007496:	2900      	cmp	r1, #0
 8007498:	bfba      	itte	lt
 800749a:	4249      	neglt	r1, r1
 800749c:	232d      	movlt	r3, #45	@ 0x2d
 800749e:	232b      	movge	r3, #43	@ 0x2b
 80074a0:	2909      	cmp	r1, #9
 80074a2:	7002      	strb	r2, [r0, #0]
 80074a4:	7043      	strb	r3, [r0, #1]
 80074a6:	dd29      	ble.n	80074fc <__exponent+0x68>
 80074a8:	f10d 0307 	add.w	r3, sp, #7
 80074ac:	461d      	mov	r5, r3
 80074ae:	270a      	movs	r7, #10
 80074b0:	461a      	mov	r2, r3
 80074b2:	fbb1 f6f7 	udiv	r6, r1, r7
 80074b6:	fb07 1416 	mls	r4, r7, r6, r1
 80074ba:	3430      	adds	r4, #48	@ 0x30
 80074bc:	f802 4c01 	strb.w	r4, [r2, #-1]
 80074c0:	460c      	mov	r4, r1
 80074c2:	2c63      	cmp	r4, #99	@ 0x63
 80074c4:	f103 33ff 	add.w	r3, r3, #4294967295
 80074c8:	4631      	mov	r1, r6
 80074ca:	dcf1      	bgt.n	80074b0 <__exponent+0x1c>
 80074cc:	3130      	adds	r1, #48	@ 0x30
 80074ce:	1e94      	subs	r4, r2, #2
 80074d0:	f803 1c01 	strb.w	r1, [r3, #-1]
 80074d4:	1c41      	adds	r1, r0, #1
 80074d6:	4623      	mov	r3, r4
 80074d8:	42ab      	cmp	r3, r5
 80074da:	d30a      	bcc.n	80074f2 <__exponent+0x5e>
 80074dc:	f10d 0309 	add.w	r3, sp, #9
 80074e0:	1a9b      	subs	r3, r3, r2
 80074e2:	42ac      	cmp	r4, r5
 80074e4:	bf88      	it	hi
 80074e6:	2300      	movhi	r3, #0
 80074e8:	3302      	adds	r3, #2
 80074ea:	4403      	add	r3, r0
 80074ec:	1a18      	subs	r0, r3, r0
 80074ee:	b003      	add	sp, #12
 80074f0:	bdf0      	pop	{r4, r5, r6, r7, pc}
 80074f2:	f813 6b01 	ldrb.w	r6, [r3], #1
 80074f6:	f801 6f01 	strb.w	r6, [r1, #1]!
 80074fa:	e7ed      	b.n	80074d8 <__exponent+0x44>
 80074fc:	2330      	movs	r3, #48	@ 0x30
 80074fe:	3130      	adds	r1, #48	@ 0x30
 8007500:	7083      	strb	r3, [r0, #2]
 8007502:	70c1      	strb	r1, [r0, #3]
 8007504:	1d03      	adds	r3, r0, #4
 8007506:	e7f1      	b.n	80074ec <__exponent+0x58>

08007508 <_printf_float>:
 8007508:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 800750c:	b08d      	sub	sp, #52	@ 0x34
 800750e:	460c      	mov	r4, r1
 8007510:	f8dd 8058 	ldr.w	r8, [sp, #88]	@ 0x58
 8007514:	4616      	mov	r6, r2
 8007516:	461f      	mov	r7, r3
 8007518:	4605      	mov	r5, r0
 800751a:	f000 fd01 	bl	8007f20 <_localeconv_r>
 800751e:	6803      	ldr	r3, [r0, #0]
 8007520:	9304      	str	r3, [sp, #16]
 8007522:	4618      	mov	r0, r3
 8007524:	f7f8 feac 	bl	8000280 <strlen>
 8007528:	2300      	movs	r3, #0
 800752a:	930a      	str	r3, [sp, #40]	@ 0x28
 800752c:	f8d8 3000 	ldr.w	r3, [r8]
 8007530:	9005      	str	r0, [sp, #20]
 8007532:	3307      	adds	r3, #7
 8007534:	f023 0307 	bic.w	r3, r3, #7
 8007538:	f103 0208 	add.w	r2, r3, #8
 800753c:	f894 a018 	ldrb.w	sl, [r4, #24]
 8007540:	f8d4 b000 	ldr.w	fp, [r4]
 8007544:	f8c8 2000 	str.w	r2, [r8]
 8007548:	e9d3 8900 	ldrd	r8, r9, [r3]
 800754c:	f029 4300 	bic.w	r3, r9, #2147483648	@ 0x80000000
 8007550:	9307      	str	r3, [sp, #28]
 8007552:	f8cd 8018 	str.w	r8, [sp, #24]
 8007556:	e9c4 8912 	strd	r8, r9, [r4, #72]	@ 0x48
 800755a:	e9dd 0106 	ldrd	r0, r1, [sp, #24]
 800755e:	4b9c      	ldr	r3, [pc, #624]	@ (80077d0 <_printf_float+0x2c8>)
 8007560:	f04f 32ff 	mov.w	r2, #4294967295
 8007564:	f7f9 faea 	bl	8000b3c <__aeabi_dcmpun>
 8007568:	bb70      	cbnz	r0, 80075c8 <_printf_float+0xc0>
 800756a:	e9dd 0106 	ldrd	r0, r1, [sp, #24]
 800756e:	4b98      	ldr	r3, [pc, #608]	@ (80077d0 <_printf_float+0x2c8>)
 8007570:	f04f 32ff 	mov.w	r2, #4294967295
 8007574:	f7f9 fac4 	bl	8000b00 <__aeabi_dcmple>
 8007578:	bb30      	cbnz	r0, 80075c8 <_printf_float+0xc0>
 800757a:	2200      	movs	r2, #0
 800757c:	2300      	movs	r3, #0
 800757e:	4640      	mov	r0, r8
 8007580:	4649      	mov	r1, r9
 8007582:	f7f9 fab3 	bl	8000aec <__aeabi_dcmplt>
 8007586:	b110      	cbz	r0, 800758e <_printf_float+0x86>
 8007588:	232d      	movs	r3, #45	@ 0x2d
 800758a:	f884 3043 	strb.w	r3, [r4, #67]	@ 0x43
 800758e:	4a91      	ldr	r2, [pc, #580]	@ (80077d4 <_printf_float+0x2cc>)
 8007590:	4b91      	ldr	r3, [pc, #580]	@ (80077d8 <_printf_float+0x2d0>)
 8007592:	f1ba 0f47 	cmp.w	sl, #71	@ 0x47
 8007596:	bf8c      	ite	hi
 8007598:	4690      	movhi	r8, r2
 800759a:	4698      	movls	r8, r3
 800759c:	2303      	movs	r3, #3
 800759e:	6123      	str	r3, [r4, #16]
 80075a0:	f02b 0304 	bic.w	r3, fp, #4
 80075a4:	6023      	str	r3, [r4, #0]
 80075a6:	f04f 0900 	mov.w	r9, #0
 80075aa:	9700      	str	r7, [sp, #0]
 80075ac:	4633      	mov	r3, r6
 80075ae:	aa0b      	add	r2, sp, #44	@ 0x2c
 80075b0:	4621      	mov	r1, r4
 80075b2:	4628      	mov	r0, r5
 80075b4:	f000 f9d2 	bl	800795c <_printf_common>
 80075b8:	3001      	adds	r0, #1
 80075ba:	f040 808d 	bne.w	80076d8 <_printf_float+0x1d0>
 80075be:	f04f 30ff 	mov.w	r0, #4294967295
 80075c2:	b00d      	add	sp, #52	@ 0x34
 80075c4:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 80075c8:	4642      	mov	r2, r8
 80075ca:	464b      	mov	r3, r9
 80075cc:	4640      	mov	r0, r8
 80075ce:	4649      	mov	r1, r9
 80075d0:	f7f9 fab4 	bl	8000b3c <__aeabi_dcmpun>
 80075d4:	b140      	cbz	r0, 80075e8 <_printf_float+0xe0>
 80075d6:	464b      	mov	r3, r9
 80075d8:	2b00      	cmp	r3, #0
 80075da:	bfbc      	itt	lt
 80075dc:	232d      	movlt	r3, #45	@ 0x2d
 80075de:	f884 3043 	strblt.w	r3, [r4, #67]	@ 0x43
 80075e2:	4a7e      	ldr	r2, [pc, #504]	@ (80077dc <_printf_float+0x2d4>)
 80075e4:	4b7e      	ldr	r3, [pc, #504]	@ (80077e0 <_printf_float+0x2d8>)
 80075e6:	e7d4      	b.n	8007592 <_printf_float+0x8a>
 80075e8:	6863      	ldr	r3, [r4, #4]
 80075ea:	f00a 02df 	and.w	r2, sl, #223	@ 0xdf
 80075ee:	9206      	str	r2, [sp, #24]
 80075f0:	1c5a      	adds	r2, r3, #1
 80075f2:	d13b      	bne.n	800766c <_printf_float+0x164>
 80075f4:	2306      	movs	r3, #6
 80075f6:	6063      	str	r3, [r4, #4]
 80075f8:	f44b 6280 	orr.w	r2, fp, #1024	@ 0x400
 80075fc:	2300      	movs	r3, #0
 80075fe:	6022      	str	r2, [r4, #0]
 8007600:	9303      	str	r3, [sp, #12]
 8007602:	ab0a      	add	r3, sp, #40	@ 0x28
 8007604:	e9cd a301 	strd	sl, r3, [sp, #4]
 8007608:	ab09      	add	r3, sp, #36	@ 0x24
 800760a:	9300      	str	r3, [sp, #0]
 800760c:	6861      	ldr	r1, [r4, #4]
 800760e:	ec49 8b10 	vmov	d0, r8, r9
 8007612:	f10d 0323 	add.w	r3, sp, #35	@ 0x23
 8007616:	4628      	mov	r0, r5
 8007618:	f7ff fed7 	bl	80073ca <__cvt>
 800761c:	9b06      	ldr	r3, [sp, #24]
 800761e:	9909      	ldr	r1, [sp, #36]	@ 0x24
 8007620:	2b47      	cmp	r3, #71	@ 0x47
 8007622:	4680      	mov	r8, r0
 8007624:	d129      	bne.n	800767a <_printf_float+0x172>
 8007626:	1cc8      	adds	r0, r1, #3
 8007628:	db02      	blt.n	8007630 <_printf_float+0x128>
 800762a:	6863      	ldr	r3, [r4, #4]
 800762c:	4299      	cmp	r1, r3
 800762e:	dd41      	ble.n	80076b4 <_printf_float+0x1ac>
 8007630:	f1aa 0a02 	sub.w	sl, sl, #2
 8007634:	fa5f fa8a 	uxtb.w	sl, sl
 8007638:	3901      	subs	r1, #1
 800763a:	4652      	mov	r2, sl
 800763c:	f104 0050 	add.w	r0, r4, #80	@ 0x50
 8007640:	9109      	str	r1, [sp, #36]	@ 0x24
 8007642:	f7ff ff27 	bl	8007494 <__exponent>
 8007646:	9a0a      	ldr	r2, [sp, #40]	@ 0x28
 8007648:	1813      	adds	r3, r2, r0
 800764a:	2a01      	cmp	r2, #1
 800764c:	4681      	mov	r9, r0
 800764e:	6123      	str	r3, [r4, #16]
 8007650:	dc02      	bgt.n	8007658 <_printf_float+0x150>
 8007652:	6822      	ldr	r2, [r4, #0]
 8007654:	07d2      	lsls	r2, r2, #31
 8007656:	d501      	bpl.n	800765c <_printf_float+0x154>
 8007658:	3301      	adds	r3, #1
 800765a:	6123      	str	r3, [r4, #16]
 800765c:	f89d 3023 	ldrb.w	r3, [sp, #35]	@ 0x23
 8007660:	2b00      	cmp	r3, #0
 8007662:	d0a2      	beq.n	80075aa <_printf_float+0xa2>
 8007664:	232d      	movs	r3, #45	@ 0x2d
 8007666:	f884 3043 	strb.w	r3, [r4, #67]	@ 0x43
 800766a:	e79e      	b.n	80075aa <_printf_float+0xa2>
 800766c:	9a06      	ldr	r2, [sp, #24]
 800766e:	2a47      	cmp	r2, #71	@ 0x47
 8007670:	d1c2      	bne.n	80075f8 <_printf_float+0xf0>
 8007672:	2b00      	cmp	r3, #0
 8007674:	d1c0      	bne.n	80075f8 <_printf_float+0xf0>
 8007676:	2301      	movs	r3, #1
 8007678:	e7bd      	b.n	80075f6 <_printf_float+0xee>
 800767a:	f1ba 0f65 	cmp.w	sl, #101	@ 0x65
 800767e:	d9db      	bls.n	8007638 <_printf_float+0x130>
 8007680:	f1ba 0f66 	cmp.w	sl, #102	@ 0x66
 8007684:	d118      	bne.n	80076b8 <_printf_float+0x1b0>
 8007686:	2900      	cmp	r1, #0
 8007688:	6863      	ldr	r3, [r4, #4]
 800768a:	dd0b      	ble.n	80076a4 <_printf_float+0x19c>
 800768c:	6121      	str	r1, [r4, #16]
 800768e:	b913      	cbnz	r3, 8007696 <_printf_float+0x18e>
 8007690:	6822      	ldr	r2, [r4, #0]
 8007692:	07d0      	lsls	r0, r2, #31
 8007694:	d502      	bpl.n	800769c <_printf_float+0x194>
 8007696:	3301      	adds	r3, #1
 8007698:	440b      	add	r3, r1
 800769a:	6123      	str	r3, [r4, #16]
 800769c:	65a1      	str	r1, [r4, #88]	@ 0x58
 800769e:	f04f 0900 	mov.w	r9, #0
 80076a2:	e7db      	b.n	800765c <_printf_float+0x154>
 80076a4:	b913      	cbnz	r3, 80076ac <_printf_float+0x1a4>
 80076a6:	6822      	ldr	r2, [r4, #0]
 80076a8:	07d2      	lsls	r2, r2, #31
 80076aa:	d501      	bpl.n	80076b0 <_printf_float+0x1a8>
 80076ac:	3302      	adds	r3, #2
 80076ae:	e7f4      	b.n	800769a <_printf_float+0x192>
 80076b0:	2301      	movs	r3, #1
 80076b2:	e7f2      	b.n	800769a <_printf_float+0x192>
 80076b4:	f04f 0a67 	mov.w	sl, #103	@ 0x67
 80076b8:	9b0a      	ldr	r3, [sp, #40]	@ 0x28
 80076ba:	4299      	cmp	r1, r3
 80076bc:	db05      	blt.n	80076ca <_printf_float+0x1c2>
 80076be:	6823      	ldr	r3, [r4, #0]
 80076c0:	6121      	str	r1, [r4, #16]
 80076c2:	07d8      	lsls	r0, r3, #31
 80076c4:	d5ea      	bpl.n	800769c <_printf_float+0x194>
 80076c6:	1c4b      	adds	r3, r1, #1
 80076c8:	e7e7      	b.n	800769a <_printf_float+0x192>
 80076ca:	2900      	cmp	r1, #0
 80076cc:	bfd4      	ite	le
 80076ce:	f1c1 0202 	rsble	r2, r1, #2
 80076d2:	2201      	movgt	r2, #1
 80076d4:	4413      	add	r3, r2
 80076d6:	e7e0      	b.n	800769a <_printf_float+0x192>
 80076d8:	6823      	ldr	r3, [r4, #0]
 80076da:	055a      	lsls	r2, r3, #21
 80076dc:	d407      	bmi.n	80076ee <_printf_float+0x1e6>
 80076de:	6923      	ldr	r3, [r4, #16]
 80076e0:	4642      	mov	r2, r8
 80076e2:	4631      	mov	r1, r6
 80076e4:	4628      	mov	r0, r5
 80076e6:	47b8      	blx	r7
 80076e8:	3001      	adds	r0, #1
 80076ea:	d12b      	bne.n	8007744 <_printf_float+0x23c>
 80076ec:	e767      	b.n	80075be <_printf_float+0xb6>
 80076ee:	f1ba 0f65 	cmp.w	sl, #101	@ 0x65
 80076f2:	f240 80dd 	bls.w	80078b0 <_printf_float+0x3a8>
 80076f6:	e9d4 0112 	ldrd	r0, r1, [r4, #72]	@ 0x48
 80076fa:	2200      	movs	r2, #0
 80076fc:	2300      	movs	r3, #0
 80076fe:	f7f9 f9eb 	bl	8000ad8 <__aeabi_dcmpeq>
 8007702:	2800      	cmp	r0, #0
 8007704:	d033      	beq.n	800776e <_printf_float+0x266>
 8007706:	4a37      	ldr	r2, [pc, #220]	@ (80077e4 <_printf_float+0x2dc>)
 8007708:	2301      	movs	r3, #1
 800770a:	4631      	mov	r1, r6
 800770c:	4628      	mov	r0, r5
 800770e:	47b8      	blx	r7
 8007710:	3001      	adds	r0, #1
 8007712:	f43f af54 	beq.w	80075be <_printf_float+0xb6>
 8007716:	e9dd 3809 	ldrd	r3, r8, [sp, #36]	@ 0x24
 800771a:	4543      	cmp	r3, r8
 800771c:	db02      	blt.n	8007724 <_printf_float+0x21c>
 800771e:	6823      	ldr	r3, [r4, #0]
 8007720:	07d8      	lsls	r0, r3, #31
 8007722:	d50f      	bpl.n	8007744 <_printf_float+0x23c>
 8007724:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
 8007728:	4631      	mov	r1, r6
 800772a:	4628      	mov	r0, r5
 800772c:	47b8      	blx	r7
 800772e:	3001      	adds	r0, #1
 8007730:	f43f af45 	beq.w	80075be <_printf_float+0xb6>
 8007734:	f04f 0900 	mov.w	r9, #0
 8007738:	f108 38ff 	add.w	r8, r8, #4294967295
 800773c:	f104 0a1a 	add.w	sl, r4, #26
 8007740:	45c8      	cmp	r8, r9
 8007742:	dc09      	bgt.n	8007758 <_printf_float+0x250>
 8007744:	6823      	ldr	r3, [r4, #0]
 8007746:	079b      	lsls	r3, r3, #30
 8007748:	f100 8103 	bmi.w	8007952 <_printf_float+0x44a>
 800774c:	68e0      	ldr	r0, [r4, #12]
 800774e:	9b0b      	ldr	r3, [sp, #44]	@ 0x2c
 8007750:	4298      	cmp	r0, r3
 8007752:	bfb8      	it	lt
 8007754:	4618      	movlt	r0, r3
 8007756:	e734      	b.n	80075c2 <_printf_float+0xba>
 8007758:	2301      	movs	r3, #1
 800775a:	4652      	mov	r2, sl
 800775c:	4631      	mov	r1, r6
 800775e:	4628      	mov	r0, r5
 8007760:	47b8      	blx	r7
 8007762:	3001      	adds	r0, #1
 8007764:	f43f af2b 	beq.w	80075be <_printf_float+0xb6>
 8007768:	f109 0901 	add.w	r9, r9, #1
 800776c:	e7e8      	b.n	8007740 <_printf_float+0x238>
 800776e:	9b09      	ldr	r3, [sp, #36]	@ 0x24
 8007770:	2b00      	cmp	r3, #0
 8007772:	dc39      	bgt.n	80077e8 <_printf_float+0x2e0>
 8007774:	4a1b      	ldr	r2, [pc, #108]	@ (80077e4 <_printf_float+0x2dc>)
 8007776:	2301      	movs	r3, #1
 8007778:	4631      	mov	r1, r6
 800777a:	4628      	mov	r0, r5
 800777c:	47b8      	blx	r7
 800777e:	3001      	adds	r0, #1
 8007780:	f43f af1d 	beq.w	80075be <_printf_float+0xb6>
 8007784:	e9dd 3909 	ldrd	r3, r9, [sp, #36]	@ 0x24
 8007788:	ea59 0303 	orrs.w	r3, r9, r3
 800778c:	d102      	bne.n	8007794 <_printf_float+0x28c>
 800778e:	6823      	ldr	r3, [r4, #0]
 8007790:	07d9      	lsls	r1, r3, #31
 8007792:	d5d7      	bpl.n	8007744 <_printf_float+0x23c>
 8007794:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
 8007798:	4631      	mov	r1, r6
 800779a:	4628      	mov	r0, r5
 800779c:	47b8      	blx	r7
 800779e:	3001      	adds	r0, #1
 80077a0:	f43f af0d 	beq.w	80075be <_printf_float+0xb6>
 80077a4:	f04f 0a00 	mov.w	sl, #0
 80077a8:	f104 0b1a 	add.w	fp, r4, #26
 80077ac:	9b09      	ldr	r3, [sp, #36]	@ 0x24
 80077ae:	425b      	negs	r3, r3
 80077b0:	4553      	cmp	r3, sl
 80077b2:	dc01      	bgt.n	80077b8 <_printf_float+0x2b0>
 80077b4:	464b      	mov	r3, r9
 80077b6:	e793      	b.n	80076e0 <_printf_float+0x1d8>
 80077b8:	2301      	movs	r3, #1
 80077ba:	465a      	mov	r2, fp
 80077bc:	4631      	mov	r1, r6
 80077be:	4628      	mov	r0, r5
 80077c0:	47b8      	blx	r7
 80077c2:	3001      	adds	r0, #1
 80077c4:	f43f aefb 	beq.w	80075be <_printf_float+0xb6>
 80077c8:	f10a 0a01 	add.w	sl, sl, #1
 80077cc:	e7ee      	b.n	80077ac <_printf_float+0x2a4>
 80077ce:	bf00      	nop
 80077d0:	7fefffff 	.word	0x7fefffff
 80077d4:	0800b940 	.word	0x0800b940
 80077d8:	0800b93c 	.word	0x0800b93c
 80077dc:	0800b948 	.word	0x0800b948
 80077e0:	0800b944 	.word	0x0800b944
 80077e4:	0800b94c 	.word	0x0800b94c
 80077e8:	6da3      	ldr	r3, [r4, #88]	@ 0x58
 80077ea:	f8dd a028 	ldr.w	sl, [sp, #40]	@ 0x28
 80077ee:	4553      	cmp	r3, sl
 80077f0:	bfa8      	it	ge
 80077f2:	4653      	movge	r3, sl
 80077f4:	2b00      	cmp	r3, #0
 80077f6:	4699      	mov	r9, r3
 80077f8:	dc36      	bgt.n	8007868 <_printf_float+0x360>
 80077fa:	f04f 0b00 	mov.w	fp, #0
 80077fe:	ea29 79e9 	bic.w	r9, r9, r9, asr #31
 8007802:	f104 021a 	add.w	r2, r4, #26
 8007806:	6da3      	ldr	r3, [r4, #88]	@ 0x58
 8007808:	9306      	str	r3, [sp, #24]
 800780a:	eba3 0309 	sub.w	r3, r3, r9
 800780e:	455b      	cmp	r3, fp
 8007810:	dc31      	bgt.n	8007876 <_printf_float+0x36e>
 8007812:	9b09      	ldr	r3, [sp, #36]	@ 0x24
 8007814:	459a      	cmp	sl, r3
 8007816:	dc3a      	bgt.n	800788e <_printf_float+0x386>
 8007818:	6823      	ldr	r3, [r4, #0]
 800781a:	07da      	lsls	r2, r3, #31
 800781c:	d437      	bmi.n	800788e <_printf_float+0x386>
 800781e:	9b09      	ldr	r3, [sp, #36]	@ 0x24
 8007820:	ebaa 0903 	sub.w	r9, sl, r3
 8007824:	9b06      	ldr	r3, [sp, #24]
 8007826:	ebaa 0303 	sub.w	r3, sl, r3
 800782a:	4599      	cmp	r9, r3
 800782c:	bfa8      	it	ge
 800782e:	4699      	movge	r9, r3
 8007830:	f1b9 0f00 	cmp.w	r9, #0
 8007834:	dc33      	bgt.n	800789e <_printf_float+0x396>
 8007836:	f04f 0800 	mov.w	r8, #0
 800783a:	ea29 79e9 	bic.w	r9, r9, r9, asr #31
 800783e:	f104 0b1a 	add.w	fp, r4, #26
 8007842:	9b09      	ldr	r3, [sp, #36]	@ 0x24
 8007844:	ebaa 0303 	sub.w	r3, sl, r3
 8007848:	eba3 0309 	sub.w	r3, r3, r9
 800784c:	4543      	cmp	r3, r8
 800784e:	f77f af79 	ble.w	8007744 <_printf_float+0x23c>
 8007852:	2301      	movs	r3, #1
 8007854:	465a      	mov	r2, fp
 8007856:	4631      	mov	r1, r6
 8007858:	4628      	mov	r0, r5
 800785a:	47b8      	blx	r7
 800785c:	3001      	adds	r0, #1
 800785e:	f43f aeae 	beq.w	80075be <_printf_float+0xb6>
 8007862:	f108 0801 	add.w	r8, r8, #1
 8007866:	e7ec      	b.n	8007842 <_printf_float+0x33a>
 8007868:	4642      	mov	r2, r8
 800786a:	4631      	mov	r1, r6
 800786c:	4628      	mov	r0, r5
 800786e:	47b8      	blx	r7
 8007870:	3001      	adds	r0, #1
 8007872:	d1c2      	bne.n	80077fa <_printf_float+0x2f2>
 8007874:	e6a3      	b.n	80075be <_printf_float+0xb6>
 8007876:	2301      	movs	r3, #1
 8007878:	4631      	mov	r1, r6
 800787a:	4628      	mov	r0, r5
 800787c:	9206      	str	r2, [sp, #24]
 800787e:	47b8      	blx	r7
 8007880:	3001      	adds	r0, #1
 8007882:	f43f ae9c 	beq.w	80075be <_printf_float+0xb6>
 8007886:	9a06      	ldr	r2, [sp, #24]
 8007888:	f10b 0b01 	add.w	fp, fp, #1
 800788c:	e7bb      	b.n	8007806 <_printf_float+0x2fe>
 800788e:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
 8007892:	4631      	mov	r1, r6
 8007894:	4628      	mov	r0, r5
 8007896:	47b8      	blx	r7
 8007898:	3001      	adds	r0, #1
 800789a:	d1c0      	bne.n	800781e <_printf_float+0x316>
 800789c:	e68f      	b.n	80075be <_printf_float+0xb6>
 800789e:	9a06      	ldr	r2, [sp, #24]
 80078a0:	464b      	mov	r3, r9
 80078a2:	4442      	add	r2, r8
 80078a4:	4631      	mov	r1, r6
 80078a6:	4628      	mov	r0, r5
 80078a8:	47b8      	blx	r7
 80078aa:	3001      	adds	r0, #1
 80078ac:	d1c3      	bne.n	8007836 <_printf_float+0x32e>
 80078ae:	e686      	b.n	80075be <_printf_float+0xb6>
 80078b0:	f8dd a028 	ldr.w	sl, [sp, #40]	@ 0x28
 80078b4:	f1ba 0f01 	cmp.w	sl, #1
 80078b8:	dc01      	bgt.n	80078be <_printf_float+0x3b6>
 80078ba:	07db      	lsls	r3, r3, #31
 80078bc:	d536      	bpl.n	800792c <_printf_float+0x424>
 80078be:	2301      	movs	r3, #1
 80078c0:	4642      	mov	r2, r8
 80078c2:	4631      	mov	r1, r6
 80078c4:	4628      	mov	r0, r5
 80078c6:	47b8      	blx	r7
 80078c8:	3001      	adds	r0, #1
 80078ca:	f43f ae78 	beq.w	80075be <_printf_float+0xb6>
 80078ce:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
 80078d2:	4631      	mov	r1, r6
 80078d4:	4628      	mov	r0, r5
 80078d6:	47b8      	blx	r7
 80078d8:	3001      	adds	r0, #1
 80078da:	f43f ae70 	beq.w	80075be <_printf_float+0xb6>
 80078de:	e9d4 0112 	ldrd	r0, r1, [r4, #72]	@ 0x48
 80078e2:	2200      	movs	r2, #0
 80078e4:	2300      	movs	r3, #0
 80078e6:	f10a 3aff 	add.w	sl, sl, #4294967295
 80078ea:	f7f9 f8f5 	bl	8000ad8 <__aeabi_dcmpeq>
 80078ee:	b9c0      	cbnz	r0, 8007922 <_printf_float+0x41a>
 80078f0:	4653      	mov	r3, sl
 80078f2:	f108 0201 	add.w	r2, r8, #1
 80078f6:	4631      	mov	r1, r6
 80078f8:	4628      	mov	r0, r5
 80078fa:	47b8      	blx	r7
 80078fc:	3001      	adds	r0, #1
 80078fe:	d10c      	bne.n	800791a <_printf_float+0x412>
 8007900:	e65d      	b.n	80075be <_printf_float+0xb6>
 8007902:	2301      	movs	r3, #1
 8007904:	465a      	mov	r2, fp
 8007906:	4631      	mov	r1, r6
 8007908:	4628      	mov	r0, r5
 800790a:	47b8      	blx	r7
 800790c:	3001      	adds	r0, #1
 800790e:	f43f ae56 	beq.w	80075be <_printf_float+0xb6>
 8007912:	f108 0801 	add.w	r8, r8, #1
 8007916:	45d0      	cmp	r8, sl
 8007918:	dbf3      	blt.n	8007902 <_printf_float+0x3fa>
 800791a:	464b      	mov	r3, r9
 800791c:	f104 0250 	add.w	r2, r4, #80	@ 0x50
 8007920:	e6df      	b.n	80076e2 <_printf_float+0x1da>
 8007922:	f04f 0800 	mov.w	r8, #0
 8007926:	f104 0b1a 	add.w	fp, r4, #26
 800792a:	e7f4      	b.n	8007916 <_printf_float+0x40e>
 800792c:	2301      	movs	r3, #1
 800792e:	4642      	mov	r2, r8
 8007930:	e7e1      	b.n	80078f6 <_printf_float+0x3ee>
 8007932:	2301      	movs	r3, #1
 8007934:	464a      	mov	r2, r9
 8007936:	4631      	mov	r1, r6
 8007938:	4628      	mov	r0, r5
 800793a:	47b8      	blx	r7
 800793c:	3001      	adds	r0, #1
 800793e:	f43f ae3e 	beq.w	80075be <_printf_float+0xb6>
 8007942:	f108 0801 	add.w	r8, r8, #1
 8007946:	68e3      	ldr	r3, [r4, #12]
 8007948:	990b      	ldr	r1, [sp, #44]	@ 0x2c
 800794a:	1a5b      	subs	r3, r3, r1
 800794c:	4543      	cmp	r3, r8
 800794e:	dcf0      	bgt.n	8007932 <_printf_float+0x42a>
 8007950:	e6fc      	b.n	800774c <_printf_float+0x244>
 8007952:	f04f 0800 	mov.w	r8, #0
 8007956:	f104 0919 	add.w	r9, r4, #25
 800795a:	e7f4      	b.n	8007946 <_printf_float+0x43e>

0800795c <_printf_common>:
 800795c:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8007960:	4616      	mov	r6, r2
 8007962:	4698      	mov	r8, r3
 8007964:	688a      	ldr	r2, [r1, #8]
 8007966:	690b      	ldr	r3, [r1, #16]
 8007968:	f8dd 9020 	ldr.w	r9, [sp, #32]
 800796c:	4293      	cmp	r3, r2
 800796e:	bfb8      	it	lt
 8007970:	4613      	movlt	r3, r2
 8007972:	6033      	str	r3, [r6, #0]
 8007974:	f891 2043 	ldrb.w	r2, [r1, #67]	@ 0x43
 8007978:	4607      	mov	r7, r0
 800797a:	460c      	mov	r4, r1
 800797c:	b10a      	cbz	r2, 8007982 <_printf_common+0x26>
 800797e:	3301      	adds	r3, #1
 8007980:	6033      	str	r3, [r6, #0]
 8007982:	6823      	ldr	r3, [r4, #0]
 8007984:	0699      	lsls	r1, r3, #26
 8007986:	bf42      	ittt	mi
 8007988:	6833      	ldrmi	r3, [r6, #0]
 800798a:	3302      	addmi	r3, #2
 800798c:	6033      	strmi	r3, [r6, #0]
 800798e:	6825      	ldr	r5, [r4, #0]
 8007990:	f015 0506 	ands.w	r5, r5, #6
 8007994:	d106      	bne.n	80079a4 <_printf_common+0x48>
 8007996:	f104 0a19 	add.w	sl, r4, #25
 800799a:	68e3      	ldr	r3, [r4, #12]
 800799c:	6832      	ldr	r2, [r6, #0]
 800799e:	1a9b      	subs	r3, r3, r2
 80079a0:	42ab      	cmp	r3, r5
 80079a2:	dc26      	bgt.n	80079f2 <_printf_common+0x96>
 80079a4:	f894 3043 	ldrb.w	r3, [r4, #67]	@ 0x43
 80079a8:	6822      	ldr	r2, [r4, #0]
 80079aa:	3b00      	subs	r3, #0
 80079ac:	bf18      	it	ne
 80079ae:	2301      	movne	r3, #1
 80079b0:	0692      	lsls	r2, r2, #26
 80079b2:	d42b      	bmi.n	8007a0c <_printf_common+0xb0>
 80079b4:	f104 0243 	add.w	r2, r4, #67	@ 0x43
 80079b8:	4641      	mov	r1, r8
 80079ba:	4638      	mov	r0, r7
 80079bc:	47c8      	blx	r9
 80079be:	3001      	adds	r0, #1
 80079c0:	d01e      	beq.n	8007a00 <_printf_common+0xa4>
 80079c2:	6823      	ldr	r3, [r4, #0]
 80079c4:	6922      	ldr	r2, [r4, #16]
 80079c6:	f003 0306 	and.w	r3, r3, #6
 80079ca:	2b04      	cmp	r3, #4
 80079cc:	bf02      	ittt	eq
 80079ce:	68e5      	ldreq	r5, [r4, #12]
 80079d0:	6833      	ldreq	r3, [r6, #0]
 80079d2:	1aed      	subeq	r5, r5, r3
 80079d4:	68a3      	ldr	r3, [r4, #8]
 80079d6:	bf0c      	ite	eq
 80079d8:	ea25 75e5 	biceq.w	r5, r5, r5, asr #31
 80079dc:	2500      	movne	r5, #0
 80079de:	4293      	cmp	r3, r2
 80079e0:	bfc4      	itt	gt
 80079e2:	1a9b      	subgt	r3, r3, r2
 80079e4:	18ed      	addgt	r5, r5, r3
 80079e6:	2600      	movs	r6, #0
 80079e8:	341a      	adds	r4, #26
 80079ea:	42b5      	cmp	r5, r6
 80079ec:	d11a      	bne.n	8007a24 <_printf_common+0xc8>
 80079ee:	2000      	movs	r0, #0
 80079f0:	e008      	b.n	8007a04 <_printf_common+0xa8>
 80079f2:	2301      	movs	r3, #1
 80079f4:	4652      	mov	r2, sl
 80079f6:	4641      	mov	r1, r8
 80079f8:	4638      	mov	r0, r7
 80079fa:	47c8      	blx	r9
 80079fc:	3001      	adds	r0, #1
 80079fe:	d103      	bne.n	8007a08 <_printf_common+0xac>
 8007a00:	f04f 30ff 	mov.w	r0, #4294967295
 8007a04:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8007a08:	3501      	adds	r5, #1
 8007a0a:	e7c6      	b.n	800799a <_printf_common+0x3e>
 8007a0c:	18e1      	adds	r1, r4, r3
 8007a0e:	1c5a      	adds	r2, r3, #1
 8007a10:	2030      	movs	r0, #48	@ 0x30
 8007a12:	f881 0043 	strb.w	r0, [r1, #67]	@ 0x43
 8007a16:	4422      	add	r2, r4
 8007a18:	f894 1045 	ldrb.w	r1, [r4, #69]	@ 0x45
 8007a1c:	f882 1043 	strb.w	r1, [r2, #67]	@ 0x43
 8007a20:	3302      	adds	r3, #2
 8007a22:	e7c7      	b.n	80079b4 <_printf_common+0x58>
 8007a24:	2301      	movs	r3, #1
 8007a26:	4622      	mov	r2, r4
 8007a28:	4641      	mov	r1, r8
 8007a2a:	4638      	mov	r0, r7
 8007a2c:	47c8      	blx	r9
 8007a2e:	3001      	adds	r0, #1
 8007a30:	d0e6      	beq.n	8007a00 <_printf_common+0xa4>
 8007a32:	3601      	adds	r6, #1
 8007a34:	e7d9      	b.n	80079ea <_printf_common+0x8e>
	...

08007a38 <_printf_i>:
 8007a38:	e92d 47ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
 8007a3c:	7e0f      	ldrb	r7, [r1, #24]
 8007a3e:	9e0c      	ldr	r6, [sp, #48]	@ 0x30
 8007a40:	2f78      	cmp	r7, #120	@ 0x78
 8007a42:	4691      	mov	r9, r2
 8007a44:	4680      	mov	r8, r0
 8007a46:	460c      	mov	r4, r1
 8007a48:	469a      	mov	sl, r3
 8007a4a:	f101 0243 	add.w	r2, r1, #67	@ 0x43
 8007a4e:	d807      	bhi.n	8007a60 <_printf_i+0x28>
 8007a50:	2f62      	cmp	r7, #98	@ 0x62
 8007a52:	d80a      	bhi.n	8007a6a <_printf_i+0x32>
 8007a54:	2f00      	cmp	r7, #0
 8007a56:	f000 80d1 	beq.w	8007bfc <_printf_i+0x1c4>
 8007a5a:	2f58      	cmp	r7, #88	@ 0x58
 8007a5c:	f000 80b8 	beq.w	8007bd0 <_printf_i+0x198>
 8007a60:	f104 0642 	add.w	r6, r4, #66	@ 0x42
 8007a64:	f884 7042 	strb.w	r7, [r4, #66]	@ 0x42
 8007a68:	e03a      	b.n	8007ae0 <_printf_i+0xa8>
 8007a6a:	f1a7 0363 	sub.w	r3, r7, #99	@ 0x63
 8007a6e:	2b15      	cmp	r3, #21
 8007a70:	d8f6      	bhi.n	8007a60 <_printf_i+0x28>
 8007a72:	a101      	add	r1, pc, #4	@ (adr r1, 8007a78 <_printf_i+0x40>)
 8007a74:	f851 f023 	ldr.w	pc, [r1, r3, lsl #2]
 8007a78:	08007ad1 	.word	0x08007ad1
 8007a7c:	08007ae5 	.word	0x08007ae5
 8007a80:	08007a61 	.word	0x08007a61
 8007a84:	08007a61 	.word	0x08007a61
 8007a88:	08007a61 	.word	0x08007a61
 8007a8c:	08007a61 	.word	0x08007a61
 8007a90:	08007ae5 	.word	0x08007ae5
 8007a94:	08007a61 	.word	0x08007a61
 8007a98:	08007a61 	.word	0x08007a61
 8007a9c:	08007a61 	.word	0x08007a61
 8007aa0:	08007a61 	.word	0x08007a61
 8007aa4:	08007be3 	.word	0x08007be3
 8007aa8:	08007b0f 	.word	0x08007b0f
 8007aac:	08007b9d 	.word	0x08007b9d
 8007ab0:	08007a61 	.word	0x08007a61
 8007ab4:	08007a61 	.word	0x08007a61
 8007ab8:	08007c05 	.word	0x08007c05
 8007abc:	08007a61 	.word	0x08007a61
 8007ac0:	08007b0f 	.word	0x08007b0f
 8007ac4:	08007a61 	.word	0x08007a61
 8007ac8:	08007a61 	.word	0x08007a61
 8007acc:	08007ba5 	.word	0x08007ba5
 8007ad0:	6833      	ldr	r3, [r6, #0]
 8007ad2:	1d1a      	adds	r2, r3, #4
 8007ad4:	681b      	ldr	r3, [r3, #0]
 8007ad6:	6032      	str	r2, [r6, #0]
 8007ad8:	f104 0642 	add.w	r6, r4, #66	@ 0x42
 8007adc:	f884 3042 	strb.w	r3, [r4, #66]	@ 0x42
 8007ae0:	2301      	movs	r3, #1
 8007ae2:	e09c      	b.n	8007c1e <_printf_i+0x1e6>
 8007ae4:	6833      	ldr	r3, [r6, #0]
 8007ae6:	6820      	ldr	r0, [r4, #0]
 8007ae8:	1d19      	adds	r1, r3, #4
 8007aea:	6031      	str	r1, [r6, #0]
 8007aec:	0606      	lsls	r6, r0, #24
 8007aee:	d501      	bpl.n	8007af4 <_printf_i+0xbc>
 8007af0:	681d      	ldr	r5, [r3, #0]
 8007af2:	e003      	b.n	8007afc <_printf_i+0xc4>
 8007af4:	0645      	lsls	r5, r0, #25
 8007af6:	d5fb      	bpl.n	8007af0 <_printf_i+0xb8>
 8007af8:	f9b3 5000 	ldrsh.w	r5, [r3]
 8007afc:	2d00      	cmp	r5, #0
 8007afe:	da03      	bge.n	8007b08 <_printf_i+0xd0>
 8007b00:	232d      	movs	r3, #45	@ 0x2d
 8007b02:	426d      	negs	r5, r5
 8007b04:	f884 3043 	strb.w	r3, [r4, #67]	@ 0x43
 8007b08:	4858      	ldr	r0, [pc, #352]	@ (8007c6c <_printf_i+0x234>)
 8007b0a:	230a      	movs	r3, #10
 8007b0c:	e011      	b.n	8007b32 <_printf_i+0xfa>
 8007b0e:	6821      	ldr	r1, [r4, #0]
 8007b10:	6833      	ldr	r3, [r6, #0]
 8007b12:	0608      	lsls	r0, r1, #24
 8007b14:	f853 5b04 	ldr.w	r5, [r3], #4
 8007b18:	d402      	bmi.n	8007b20 <_printf_i+0xe8>
 8007b1a:	0649      	lsls	r1, r1, #25
 8007b1c:	bf48      	it	mi
 8007b1e:	b2ad      	uxthmi	r5, r5
 8007b20:	2f6f      	cmp	r7, #111	@ 0x6f
 8007b22:	4852      	ldr	r0, [pc, #328]	@ (8007c6c <_printf_i+0x234>)
 8007b24:	6033      	str	r3, [r6, #0]
 8007b26:	bf14      	ite	ne
 8007b28:	230a      	movne	r3, #10
 8007b2a:	2308      	moveq	r3, #8
 8007b2c:	2100      	movs	r1, #0
 8007b2e:	f884 1043 	strb.w	r1, [r4, #67]	@ 0x43
 8007b32:	6866      	ldr	r6, [r4, #4]
 8007b34:	60a6      	str	r6, [r4, #8]
 8007b36:	2e00      	cmp	r6, #0
 8007b38:	db05      	blt.n	8007b46 <_printf_i+0x10e>
 8007b3a:	6821      	ldr	r1, [r4, #0]
 8007b3c:	432e      	orrs	r6, r5
 8007b3e:	f021 0104 	bic.w	r1, r1, #4
 8007b42:	6021      	str	r1, [r4, #0]
 8007b44:	d04b      	beq.n	8007bde <_printf_i+0x1a6>
 8007b46:	4616      	mov	r6, r2
 8007b48:	fbb5 f1f3 	udiv	r1, r5, r3
 8007b4c:	fb03 5711 	mls	r7, r3, r1, r5
 8007b50:	5dc7      	ldrb	r7, [r0, r7]
 8007b52:	f806 7d01 	strb.w	r7, [r6, #-1]!
 8007b56:	462f      	mov	r7, r5
 8007b58:	42bb      	cmp	r3, r7
 8007b5a:	460d      	mov	r5, r1
 8007b5c:	d9f4      	bls.n	8007b48 <_printf_i+0x110>
 8007b5e:	2b08      	cmp	r3, #8
 8007b60:	d10b      	bne.n	8007b7a <_printf_i+0x142>
 8007b62:	6823      	ldr	r3, [r4, #0]
 8007b64:	07df      	lsls	r7, r3, #31
 8007b66:	d508      	bpl.n	8007b7a <_printf_i+0x142>
 8007b68:	6923      	ldr	r3, [r4, #16]
 8007b6a:	6861      	ldr	r1, [r4, #4]
 8007b6c:	4299      	cmp	r1, r3
 8007b6e:	bfde      	ittt	le
 8007b70:	2330      	movle	r3, #48	@ 0x30
 8007b72:	f806 3c01 	strble.w	r3, [r6, #-1]
 8007b76:	f106 36ff 	addle.w	r6, r6, #4294967295
 8007b7a:	1b92      	subs	r2, r2, r6
 8007b7c:	6122      	str	r2, [r4, #16]
 8007b7e:	f8cd a000 	str.w	sl, [sp]
 8007b82:	464b      	mov	r3, r9
 8007b84:	aa03      	add	r2, sp, #12
 8007b86:	4621      	mov	r1, r4
 8007b88:	4640      	mov	r0, r8
 8007b8a:	f7ff fee7 	bl	800795c <_printf_common>
 8007b8e:	3001      	adds	r0, #1
 8007b90:	d14a      	bne.n	8007c28 <_printf_i+0x1f0>
 8007b92:	f04f 30ff 	mov.w	r0, #4294967295
 8007b96:	b004      	add	sp, #16
 8007b98:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8007b9c:	6823      	ldr	r3, [r4, #0]
 8007b9e:	f043 0320 	orr.w	r3, r3, #32
 8007ba2:	6023      	str	r3, [r4, #0]
 8007ba4:	4832      	ldr	r0, [pc, #200]	@ (8007c70 <_printf_i+0x238>)
 8007ba6:	2778      	movs	r7, #120	@ 0x78
 8007ba8:	f884 7045 	strb.w	r7, [r4, #69]	@ 0x45
 8007bac:	6823      	ldr	r3, [r4, #0]
 8007bae:	6831      	ldr	r1, [r6, #0]
 8007bb0:	061f      	lsls	r7, r3, #24
 8007bb2:	f851 5b04 	ldr.w	r5, [r1], #4
 8007bb6:	d402      	bmi.n	8007bbe <_printf_i+0x186>
 8007bb8:	065f      	lsls	r7, r3, #25
 8007bba:	bf48      	it	mi
 8007bbc:	b2ad      	uxthmi	r5, r5
 8007bbe:	6031      	str	r1, [r6, #0]
 8007bc0:	07d9      	lsls	r1, r3, #31
 8007bc2:	bf44      	itt	mi
 8007bc4:	f043 0320 	orrmi.w	r3, r3, #32
 8007bc8:	6023      	strmi	r3, [r4, #0]
 8007bca:	b11d      	cbz	r5, 8007bd4 <_printf_i+0x19c>
 8007bcc:	2310      	movs	r3, #16
 8007bce:	e7ad      	b.n	8007b2c <_printf_i+0xf4>
 8007bd0:	4826      	ldr	r0, [pc, #152]	@ (8007c6c <_printf_i+0x234>)
 8007bd2:	e7e9      	b.n	8007ba8 <_printf_i+0x170>
 8007bd4:	6823      	ldr	r3, [r4, #0]
 8007bd6:	f023 0320 	bic.w	r3, r3, #32
 8007bda:	6023      	str	r3, [r4, #0]
 8007bdc:	e7f6      	b.n	8007bcc <_printf_i+0x194>
 8007bde:	4616      	mov	r6, r2
 8007be0:	e7bd      	b.n	8007b5e <_printf_i+0x126>
 8007be2:	6833      	ldr	r3, [r6, #0]
 8007be4:	6825      	ldr	r5, [r4, #0]
 8007be6:	6961      	ldr	r1, [r4, #20]
 8007be8:	1d18      	adds	r0, r3, #4
 8007bea:	6030      	str	r0, [r6, #0]
 8007bec:	062e      	lsls	r6, r5, #24
 8007bee:	681b      	ldr	r3, [r3, #0]
 8007bf0:	d501      	bpl.n	8007bf6 <_printf_i+0x1be>
 8007bf2:	6019      	str	r1, [r3, #0]
 8007bf4:	e002      	b.n	8007bfc <_printf_i+0x1c4>
 8007bf6:	0668      	lsls	r0, r5, #25
 8007bf8:	d5fb      	bpl.n	8007bf2 <_printf_i+0x1ba>
 8007bfa:	8019      	strh	r1, [r3, #0]
 8007bfc:	2300      	movs	r3, #0
 8007bfe:	6123      	str	r3, [r4, #16]
 8007c00:	4616      	mov	r6, r2
 8007c02:	e7bc      	b.n	8007b7e <_printf_i+0x146>
 8007c04:	6833      	ldr	r3, [r6, #0]
 8007c06:	1d1a      	adds	r2, r3, #4
 8007c08:	6032      	str	r2, [r6, #0]
 8007c0a:	681e      	ldr	r6, [r3, #0]
 8007c0c:	6862      	ldr	r2, [r4, #4]
 8007c0e:	2100      	movs	r1, #0
 8007c10:	4630      	mov	r0, r6
 8007c12:	f7f8 fae5 	bl	80001e0 <memchr>
 8007c16:	b108      	cbz	r0, 8007c1c <_printf_i+0x1e4>
 8007c18:	1b80      	subs	r0, r0, r6
 8007c1a:	6060      	str	r0, [r4, #4]
 8007c1c:	6863      	ldr	r3, [r4, #4]
 8007c1e:	6123      	str	r3, [r4, #16]
 8007c20:	2300      	movs	r3, #0
 8007c22:	f884 3043 	strb.w	r3, [r4, #67]	@ 0x43
 8007c26:	e7aa      	b.n	8007b7e <_printf_i+0x146>
 8007c28:	6923      	ldr	r3, [r4, #16]
 8007c2a:	4632      	mov	r2, r6
 8007c2c:	4649      	mov	r1, r9
 8007c2e:	4640      	mov	r0, r8
 8007c30:	47d0      	blx	sl
 8007c32:	3001      	adds	r0, #1
 8007c34:	d0ad      	beq.n	8007b92 <_printf_i+0x15a>
 8007c36:	6823      	ldr	r3, [r4, #0]
 8007c38:	079b      	lsls	r3, r3, #30
 8007c3a:	d413      	bmi.n	8007c64 <_printf_i+0x22c>
 8007c3c:	68e0      	ldr	r0, [r4, #12]
 8007c3e:	9b03      	ldr	r3, [sp, #12]
 8007c40:	4298      	cmp	r0, r3
 8007c42:	bfb8      	it	lt
 8007c44:	4618      	movlt	r0, r3
 8007c46:	e7a6      	b.n	8007b96 <_printf_i+0x15e>
 8007c48:	2301      	movs	r3, #1
 8007c4a:	4632      	mov	r2, r6
 8007c4c:	4649      	mov	r1, r9
 8007c4e:	4640      	mov	r0, r8
 8007c50:	47d0      	blx	sl
 8007c52:	3001      	adds	r0, #1
 8007c54:	d09d      	beq.n	8007b92 <_printf_i+0x15a>
 8007c56:	3501      	adds	r5, #1
 8007c58:	68e3      	ldr	r3, [r4, #12]
 8007c5a:	9903      	ldr	r1, [sp, #12]
 8007c5c:	1a5b      	subs	r3, r3, r1
 8007c5e:	42ab      	cmp	r3, r5
 8007c60:	dcf2      	bgt.n	8007c48 <_printf_i+0x210>
 8007c62:	e7eb      	b.n	8007c3c <_printf_i+0x204>
 8007c64:	2500      	movs	r5, #0
 8007c66:	f104 0619 	add.w	r6, r4, #25
 8007c6a:	e7f5      	b.n	8007c58 <_printf_i+0x220>
 8007c6c:	0800b94e 	.word	0x0800b94e
 8007c70:	0800b95f 	.word	0x0800b95f

08007c74 <std>:
 8007c74:	2300      	movs	r3, #0
 8007c76:	b510      	push	{r4, lr}
 8007c78:	4604      	mov	r4, r0
 8007c7a:	e9c0 3300 	strd	r3, r3, [r0]
 8007c7e:	e9c0 3304 	strd	r3, r3, [r0, #16]
 8007c82:	6083      	str	r3, [r0, #8]
 8007c84:	8181      	strh	r1, [r0, #12]
 8007c86:	6643      	str	r3, [r0, #100]	@ 0x64
 8007c88:	81c2      	strh	r2, [r0, #14]
 8007c8a:	6183      	str	r3, [r0, #24]
 8007c8c:	4619      	mov	r1, r3
 8007c8e:	2208      	movs	r2, #8
 8007c90:	305c      	adds	r0, #92	@ 0x5c
 8007c92:	f000 f93c 	bl	8007f0e <memset>
 8007c96:	4b0d      	ldr	r3, [pc, #52]	@ (8007ccc <std+0x58>)
 8007c98:	6263      	str	r3, [r4, #36]	@ 0x24
 8007c9a:	4b0d      	ldr	r3, [pc, #52]	@ (8007cd0 <std+0x5c>)
 8007c9c:	62a3      	str	r3, [r4, #40]	@ 0x28
 8007c9e:	4b0d      	ldr	r3, [pc, #52]	@ (8007cd4 <std+0x60>)
 8007ca0:	62e3      	str	r3, [r4, #44]	@ 0x2c
 8007ca2:	4b0d      	ldr	r3, [pc, #52]	@ (8007cd8 <std+0x64>)
 8007ca4:	6323      	str	r3, [r4, #48]	@ 0x30
 8007ca6:	4b0d      	ldr	r3, [pc, #52]	@ (8007cdc <std+0x68>)
 8007ca8:	6224      	str	r4, [r4, #32]
 8007caa:	429c      	cmp	r4, r3
 8007cac:	d006      	beq.n	8007cbc <std+0x48>
 8007cae:	f103 0268 	add.w	r2, r3, #104	@ 0x68
 8007cb2:	4294      	cmp	r4, r2
 8007cb4:	d002      	beq.n	8007cbc <std+0x48>
 8007cb6:	33d0      	adds	r3, #208	@ 0xd0
 8007cb8:	429c      	cmp	r4, r3
 8007cba:	d105      	bne.n	8007cc8 <std+0x54>
 8007cbc:	f104 0058 	add.w	r0, r4, #88	@ 0x58
 8007cc0:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
 8007cc4:	f000 b9a0 	b.w	8008008 <__retarget_lock_init_recursive>
 8007cc8:	bd10      	pop	{r4, pc}
 8007cca:	bf00      	nop
 8007ccc:	08007e89 	.word	0x08007e89
 8007cd0:	08007eab 	.word	0x08007eab
 8007cd4:	08007ee3 	.word	0x08007ee3
 8007cd8:	08007f07 	.word	0x08007f07
 8007cdc:	200003a4 	.word	0x200003a4

08007ce0 <stdio_exit_handler>:
 8007ce0:	4a02      	ldr	r2, [pc, #8]	@ (8007cec <stdio_exit_handler+0xc>)
 8007ce2:	4903      	ldr	r1, [pc, #12]	@ (8007cf0 <stdio_exit_handler+0x10>)
 8007ce4:	4803      	ldr	r0, [pc, #12]	@ (8007cf4 <stdio_exit_handler+0x14>)
 8007ce6:	f000 b869 	b.w	8007dbc <_fwalk_sglue>
 8007cea:	bf00      	nop
 8007cec:	2000000c 	.word	0x2000000c
 8007cf0:	08009bf1 	.word	0x08009bf1
 8007cf4:	2000001c 	.word	0x2000001c

08007cf8 <cleanup_stdio>:
 8007cf8:	6841      	ldr	r1, [r0, #4]
 8007cfa:	4b0c      	ldr	r3, [pc, #48]	@ (8007d2c <cleanup_stdio+0x34>)
 8007cfc:	4299      	cmp	r1, r3
 8007cfe:	b510      	push	{r4, lr}
 8007d00:	4604      	mov	r4, r0
 8007d02:	d001      	beq.n	8007d08 <cleanup_stdio+0x10>
 8007d04:	f001 ff74 	bl	8009bf0 <_fflush_r>
 8007d08:	68a1      	ldr	r1, [r4, #8]
 8007d0a:	4b09      	ldr	r3, [pc, #36]	@ (8007d30 <cleanup_stdio+0x38>)
 8007d0c:	4299      	cmp	r1, r3
 8007d0e:	d002      	beq.n	8007d16 <cleanup_stdio+0x1e>
 8007d10:	4620      	mov	r0, r4
 8007d12:	f001 ff6d 	bl	8009bf0 <_fflush_r>
 8007d16:	68e1      	ldr	r1, [r4, #12]
 8007d18:	4b06      	ldr	r3, [pc, #24]	@ (8007d34 <cleanup_stdio+0x3c>)
 8007d1a:	4299      	cmp	r1, r3
 8007d1c:	d004      	beq.n	8007d28 <cleanup_stdio+0x30>
 8007d1e:	4620      	mov	r0, r4
 8007d20:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
 8007d24:	f001 bf64 	b.w	8009bf0 <_fflush_r>
 8007d28:	bd10      	pop	{r4, pc}
 8007d2a:	bf00      	nop
 8007d2c:	200003a4 	.word	0x200003a4
 8007d30:	2000040c 	.word	0x2000040c
 8007d34:	20000474 	.word	0x20000474

08007d38 <global_stdio_init.part.0>:
 8007d38:	b510      	push	{r4, lr}
 8007d3a:	4b0b      	ldr	r3, [pc, #44]	@ (8007d68 <global_stdio_init.part.0+0x30>)
 8007d3c:	4c0b      	ldr	r4, [pc, #44]	@ (8007d6c <global_stdio_init.part.0+0x34>)
 8007d3e:	4a0c      	ldr	r2, [pc, #48]	@ (8007d70 <global_stdio_init.part.0+0x38>)
 8007d40:	601a      	str	r2, [r3, #0]
 8007d42:	4620      	mov	r0, r4
 8007d44:	2200      	movs	r2, #0
 8007d46:	2104      	movs	r1, #4
 8007d48:	f7ff ff94 	bl	8007c74 <std>
 8007d4c:	f104 0068 	add.w	r0, r4, #104	@ 0x68
 8007d50:	2201      	movs	r2, #1
 8007d52:	2109      	movs	r1, #9
 8007d54:	f7ff ff8e 	bl	8007c74 <std>
 8007d58:	f104 00d0 	add.w	r0, r4, #208	@ 0xd0
 8007d5c:	2202      	movs	r2, #2
 8007d5e:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
 8007d62:	2112      	movs	r1, #18
 8007d64:	f7ff bf86 	b.w	8007c74 <std>
 8007d68:	200004dc 	.word	0x200004dc
 8007d6c:	200003a4 	.word	0x200003a4
 8007d70:	08007ce1 	.word	0x08007ce1

08007d74 <__sfp_lock_acquire>:
 8007d74:	4801      	ldr	r0, [pc, #4]	@ (8007d7c <__sfp_lock_acquire+0x8>)
 8007d76:	f000 b948 	b.w	800800a <__retarget_lock_acquire_recursive>
 8007d7a:	bf00      	nop
 8007d7c:	200004e5 	.word	0x200004e5

08007d80 <__sfp_lock_release>:
 8007d80:	4801      	ldr	r0, [pc, #4]	@ (8007d88 <__sfp_lock_release+0x8>)
 8007d82:	f000 b943 	b.w	800800c <__retarget_lock_release_recursive>
 8007d86:	bf00      	nop
 8007d88:	200004e5 	.word	0x200004e5

08007d8c <__sinit>:
 8007d8c:	b510      	push	{r4, lr}
 8007d8e:	4604      	mov	r4, r0
 8007d90:	f7ff fff0 	bl	8007d74 <__sfp_lock_acquire>
 8007d94:	6a23      	ldr	r3, [r4, #32]
 8007d96:	b11b      	cbz	r3, 8007da0 <__sinit+0x14>
 8007d98:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
 8007d9c:	f7ff bff0 	b.w	8007d80 <__sfp_lock_release>
 8007da0:	4b04      	ldr	r3, [pc, #16]	@ (8007db4 <__sinit+0x28>)
 8007da2:	6223      	str	r3, [r4, #32]
 8007da4:	4b04      	ldr	r3, [pc, #16]	@ (8007db8 <__sinit+0x2c>)
 8007da6:	681b      	ldr	r3, [r3, #0]
 8007da8:	2b00      	cmp	r3, #0
 8007daa:	d1f5      	bne.n	8007d98 <__sinit+0xc>
 8007dac:	f7ff ffc4 	bl	8007d38 <global_stdio_init.part.0>
 8007db0:	e7f2      	b.n	8007d98 <__sinit+0xc>
 8007db2:	bf00      	nop
 8007db4:	08007cf9 	.word	0x08007cf9
 8007db8:	200004dc 	.word	0x200004dc

08007dbc <_fwalk_sglue>:
 8007dbc:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 8007dc0:	4607      	mov	r7, r0
 8007dc2:	4688      	mov	r8, r1
 8007dc4:	4614      	mov	r4, r2
 8007dc6:	2600      	movs	r6, #0
 8007dc8:	e9d4 9501 	ldrd	r9, r5, [r4, #4]
 8007dcc:	f1b9 0901 	subs.w	r9, r9, #1
 8007dd0:	d505      	bpl.n	8007dde <_fwalk_sglue+0x22>
 8007dd2:	6824      	ldr	r4, [r4, #0]
 8007dd4:	2c00      	cmp	r4, #0
 8007dd6:	d1f7      	bne.n	8007dc8 <_fwalk_sglue+0xc>
 8007dd8:	4630      	mov	r0, r6
 8007dda:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 8007dde:	89ab      	ldrh	r3, [r5, #12]
 8007de0:	2b01      	cmp	r3, #1
 8007de2:	d907      	bls.n	8007df4 <_fwalk_sglue+0x38>
 8007de4:	f9b5 300e 	ldrsh.w	r3, [r5, #14]
 8007de8:	3301      	adds	r3, #1
 8007dea:	d003      	beq.n	8007df4 <_fwalk_sglue+0x38>
 8007dec:	4629      	mov	r1, r5
 8007dee:	4638      	mov	r0, r7
 8007df0:	47c0      	blx	r8
 8007df2:	4306      	orrs	r6, r0
 8007df4:	3568      	adds	r5, #104	@ 0x68
 8007df6:	e7e9      	b.n	8007dcc <_fwalk_sglue+0x10>

08007df8 <iprintf>:
 8007df8:	b40f      	push	{r0, r1, r2, r3}
 8007dfa:	b507      	push	{r0, r1, r2, lr}
 8007dfc:	4906      	ldr	r1, [pc, #24]	@ (8007e18 <iprintf+0x20>)
 8007dfe:	ab04      	add	r3, sp, #16
 8007e00:	6808      	ldr	r0, [r1, #0]
 8007e02:	f853 2b04 	ldr.w	r2, [r3], #4
 8007e06:	6881      	ldr	r1, [r0, #8]
 8007e08:	9301      	str	r3, [sp, #4]
 8007e0a:	f001 fd55 	bl	80098b8 <_vfiprintf_r>
 8007e0e:	b003      	add	sp, #12
 8007e10:	f85d eb04 	ldr.w	lr, [sp], #4
 8007e14:	b004      	add	sp, #16
 8007e16:	4770      	bx	lr
 8007e18:	20000018 	.word	0x20000018

08007e1c <sniprintf>:
 8007e1c:	b40c      	push	{r2, r3}
 8007e1e:	b530      	push	{r4, r5, lr}
 8007e20:	4b18      	ldr	r3, [pc, #96]	@ (8007e84 <sniprintf+0x68>)
 8007e22:	1e0c      	subs	r4, r1, #0
 8007e24:	681d      	ldr	r5, [r3, #0]
 8007e26:	b09d      	sub	sp, #116	@ 0x74
 8007e28:	da08      	bge.n	8007e3c <sniprintf+0x20>
 8007e2a:	238b      	movs	r3, #139	@ 0x8b
 8007e2c:	602b      	str	r3, [r5, #0]
 8007e2e:	f04f 30ff 	mov.w	r0, #4294967295
 8007e32:	b01d      	add	sp, #116	@ 0x74
 8007e34:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
 8007e38:	b002      	add	sp, #8
 8007e3a:	4770      	bx	lr
 8007e3c:	f44f 7302 	mov.w	r3, #520	@ 0x208
 8007e40:	f8ad 3014 	strh.w	r3, [sp, #20]
 8007e44:	f04f 0300 	mov.w	r3, #0
 8007e48:	931b      	str	r3, [sp, #108]	@ 0x6c
 8007e4a:	bf14      	ite	ne
 8007e4c:	f104 33ff 	addne.w	r3, r4, #4294967295
 8007e50:	4623      	moveq	r3, r4
 8007e52:	9304      	str	r3, [sp, #16]
 8007e54:	9307      	str	r3, [sp, #28]
 8007e56:	f64f 73ff 	movw	r3, #65535	@ 0xffff
 8007e5a:	9002      	str	r0, [sp, #8]
 8007e5c:	9006      	str	r0, [sp, #24]
 8007e5e:	f8ad 3016 	strh.w	r3, [sp, #22]
 8007e62:	9a20      	ldr	r2, [sp, #128]	@ 0x80
 8007e64:	ab21      	add	r3, sp, #132	@ 0x84
 8007e66:	a902      	add	r1, sp, #8
 8007e68:	4628      	mov	r0, r5
 8007e6a:	9301      	str	r3, [sp, #4]
 8007e6c:	f001 fbfe 	bl	800966c <_svfiprintf_r>
 8007e70:	1c43      	adds	r3, r0, #1
 8007e72:	bfbc      	itt	lt
 8007e74:	238b      	movlt	r3, #139	@ 0x8b
 8007e76:	602b      	strlt	r3, [r5, #0]
 8007e78:	2c00      	cmp	r4, #0
 8007e7a:	d0da      	beq.n	8007e32 <sniprintf+0x16>
 8007e7c:	9b02      	ldr	r3, [sp, #8]
 8007e7e:	2200      	movs	r2, #0
 8007e80:	701a      	strb	r2, [r3, #0]
 8007e82:	e7d6      	b.n	8007e32 <sniprintf+0x16>
 8007e84:	20000018 	.word	0x20000018

08007e88 <__sread>:
 8007e88:	b510      	push	{r4, lr}
 8007e8a:	460c      	mov	r4, r1
 8007e8c:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8007e90:	f000 f86c 	bl	8007f6c <_read_r>
 8007e94:	2800      	cmp	r0, #0
 8007e96:	bfab      	itete	ge
 8007e98:	6d63      	ldrge	r3, [r4, #84]	@ 0x54
 8007e9a:	89a3      	ldrhlt	r3, [r4, #12]
 8007e9c:	181b      	addge	r3, r3, r0
 8007e9e:	f423 5380 	biclt.w	r3, r3, #4096	@ 0x1000
 8007ea2:	bfac      	ite	ge
 8007ea4:	6563      	strge	r3, [r4, #84]	@ 0x54
 8007ea6:	81a3      	strhlt	r3, [r4, #12]
 8007ea8:	bd10      	pop	{r4, pc}

08007eaa <__swrite>:
 8007eaa:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8007eae:	461f      	mov	r7, r3
 8007eb0:	898b      	ldrh	r3, [r1, #12]
 8007eb2:	05db      	lsls	r3, r3, #23
 8007eb4:	4605      	mov	r5, r0
 8007eb6:	460c      	mov	r4, r1
 8007eb8:	4616      	mov	r6, r2
 8007eba:	d505      	bpl.n	8007ec8 <__swrite+0x1e>
 8007ebc:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8007ec0:	2302      	movs	r3, #2
 8007ec2:	2200      	movs	r2, #0
 8007ec4:	f000 f840 	bl	8007f48 <_lseek_r>
 8007ec8:	89a3      	ldrh	r3, [r4, #12]
 8007eca:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 8007ece:	f423 5380 	bic.w	r3, r3, #4096	@ 0x1000
 8007ed2:	81a3      	strh	r3, [r4, #12]
 8007ed4:	4632      	mov	r2, r6
 8007ed6:	463b      	mov	r3, r7
 8007ed8:	4628      	mov	r0, r5
 8007eda:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
 8007ede:	f000 b857 	b.w	8007f90 <_write_r>

08007ee2 <__sseek>:
 8007ee2:	b510      	push	{r4, lr}
 8007ee4:	460c      	mov	r4, r1
 8007ee6:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8007eea:	f000 f82d 	bl	8007f48 <_lseek_r>
 8007eee:	1c43      	adds	r3, r0, #1
 8007ef0:	89a3      	ldrh	r3, [r4, #12]
 8007ef2:	bf15      	itete	ne
 8007ef4:	6560      	strne	r0, [r4, #84]	@ 0x54
 8007ef6:	f423 5380 	biceq.w	r3, r3, #4096	@ 0x1000
 8007efa:	f443 5380 	orrne.w	r3, r3, #4096	@ 0x1000
 8007efe:	81a3      	strheq	r3, [r4, #12]
 8007f00:	bf18      	it	ne
 8007f02:	81a3      	strhne	r3, [r4, #12]
 8007f04:	bd10      	pop	{r4, pc}

08007f06 <__sclose>:
 8007f06:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8007f0a:	f000 b80d 	b.w	8007f28 <_close_r>

08007f0e <memset>:
 8007f0e:	4402      	add	r2, r0
 8007f10:	4603      	mov	r3, r0
 8007f12:	4293      	cmp	r3, r2
 8007f14:	d100      	bne.n	8007f18 <memset+0xa>
 8007f16:	4770      	bx	lr
 8007f18:	f803 1b01 	strb.w	r1, [r3], #1
 8007f1c:	e7f9      	b.n	8007f12 <memset+0x4>
	...

08007f20 <_localeconv_r>:
 8007f20:	4800      	ldr	r0, [pc, #0]	@ (8007f24 <_localeconv_r+0x4>)
 8007f22:	4770      	bx	lr
 8007f24:	20000158 	.word	0x20000158

08007f28 <_close_r>:
 8007f28:	b538      	push	{r3, r4, r5, lr}
 8007f2a:	4d06      	ldr	r5, [pc, #24]	@ (8007f44 <_close_r+0x1c>)
 8007f2c:	2300      	movs	r3, #0
 8007f2e:	4604      	mov	r4, r0
 8007f30:	4608      	mov	r0, r1
 8007f32:	602b      	str	r3, [r5, #0]
 8007f34:	f7fb ffdb 	bl	8003eee <_close>
 8007f38:	1c43      	adds	r3, r0, #1
 8007f3a:	d102      	bne.n	8007f42 <_close_r+0x1a>
 8007f3c:	682b      	ldr	r3, [r5, #0]
 8007f3e:	b103      	cbz	r3, 8007f42 <_close_r+0x1a>
 8007f40:	6023      	str	r3, [r4, #0]
 8007f42:	bd38      	pop	{r3, r4, r5, pc}
 8007f44:	200004e0 	.word	0x200004e0

08007f48 <_lseek_r>:
 8007f48:	b538      	push	{r3, r4, r5, lr}
 8007f4a:	4d07      	ldr	r5, [pc, #28]	@ (8007f68 <_lseek_r+0x20>)
 8007f4c:	4604      	mov	r4, r0
 8007f4e:	4608      	mov	r0, r1
 8007f50:	4611      	mov	r1, r2
 8007f52:	2200      	movs	r2, #0
 8007f54:	602a      	str	r2, [r5, #0]
 8007f56:	461a      	mov	r2, r3
 8007f58:	f7fb fff0 	bl	8003f3c <_lseek>
 8007f5c:	1c43      	adds	r3, r0, #1
 8007f5e:	d102      	bne.n	8007f66 <_lseek_r+0x1e>
 8007f60:	682b      	ldr	r3, [r5, #0]
 8007f62:	b103      	cbz	r3, 8007f66 <_lseek_r+0x1e>
 8007f64:	6023      	str	r3, [r4, #0]
 8007f66:	bd38      	pop	{r3, r4, r5, pc}
 8007f68:	200004e0 	.word	0x200004e0

08007f6c <_read_r>:
 8007f6c:	b538      	push	{r3, r4, r5, lr}
 8007f6e:	4d07      	ldr	r5, [pc, #28]	@ (8007f8c <_read_r+0x20>)
 8007f70:	4604      	mov	r4, r0
 8007f72:	4608      	mov	r0, r1
 8007f74:	4611      	mov	r1, r2
 8007f76:	2200      	movs	r2, #0
 8007f78:	602a      	str	r2, [r5, #0]
 8007f7a:	461a      	mov	r2, r3
 8007f7c:	f7fb ff7e 	bl	8003e7c <_read>
 8007f80:	1c43      	adds	r3, r0, #1
 8007f82:	d102      	bne.n	8007f8a <_read_r+0x1e>
 8007f84:	682b      	ldr	r3, [r5, #0]
 8007f86:	b103      	cbz	r3, 8007f8a <_read_r+0x1e>
 8007f88:	6023      	str	r3, [r4, #0]
 8007f8a:	bd38      	pop	{r3, r4, r5, pc}
 8007f8c:	200004e0 	.word	0x200004e0

08007f90 <_write_r>:
 8007f90:	b538      	push	{r3, r4, r5, lr}
 8007f92:	4d07      	ldr	r5, [pc, #28]	@ (8007fb0 <_write_r+0x20>)
 8007f94:	4604      	mov	r4, r0
 8007f96:	4608      	mov	r0, r1
 8007f98:	4611      	mov	r1, r2
 8007f9a:	2200      	movs	r2, #0
 8007f9c:	602a      	str	r2, [r5, #0]
 8007f9e:	461a      	mov	r2, r3
 8007fa0:	f7fb ff89 	bl	8003eb6 <_write>
 8007fa4:	1c43      	adds	r3, r0, #1
 8007fa6:	d102      	bne.n	8007fae <_write_r+0x1e>
 8007fa8:	682b      	ldr	r3, [r5, #0]
 8007faa:	b103      	cbz	r3, 8007fae <_write_r+0x1e>
 8007fac:	6023      	str	r3, [r4, #0]
 8007fae:	bd38      	pop	{r3, r4, r5, pc}
 8007fb0:	200004e0 	.word	0x200004e0

08007fb4 <__errno>:
 8007fb4:	4b01      	ldr	r3, [pc, #4]	@ (8007fbc <__errno+0x8>)
 8007fb6:	6818      	ldr	r0, [r3, #0]
 8007fb8:	4770      	bx	lr
 8007fba:	bf00      	nop
 8007fbc:	20000018 	.word	0x20000018

08007fc0 <__libc_init_array>:
 8007fc0:	b570      	push	{r4, r5, r6, lr}
 8007fc2:	4d0d      	ldr	r5, [pc, #52]	@ (8007ff8 <__libc_init_array+0x38>)
 8007fc4:	4c0d      	ldr	r4, [pc, #52]	@ (8007ffc <__libc_init_array+0x3c>)
 8007fc6:	1b64      	subs	r4, r4, r5
 8007fc8:	10a4      	asrs	r4, r4, #2
 8007fca:	2600      	movs	r6, #0
 8007fcc:	42a6      	cmp	r6, r4
 8007fce:	d109      	bne.n	8007fe4 <__libc_init_array+0x24>
 8007fd0:	4d0b      	ldr	r5, [pc, #44]	@ (8008000 <__libc_init_array+0x40>)
 8007fd2:	4c0c      	ldr	r4, [pc, #48]	@ (8008004 <__libc_init_array+0x44>)
 8007fd4:	f003 fb9e 	bl	800b714 <_init>
 8007fd8:	1b64      	subs	r4, r4, r5
 8007fda:	10a4      	asrs	r4, r4, #2
 8007fdc:	2600      	movs	r6, #0
 8007fde:	42a6      	cmp	r6, r4
 8007fe0:	d105      	bne.n	8007fee <__libc_init_array+0x2e>
 8007fe2:	bd70      	pop	{r4, r5, r6, pc}
 8007fe4:	f855 3b04 	ldr.w	r3, [r5], #4
 8007fe8:	4798      	blx	r3
 8007fea:	3601      	adds	r6, #1
 8007fec:	e7ee      	b.n	8007fcc <__libc_init_array+0xc>
 8007fee:	f855 3b04 	ldr.w	r3, [r5], #4
 8007ff2:	4798      	blx	r3
 8007ff4:	3601      	adds	r6, #1
 8007ff6:	e7f2      	b.n	8007fde <__libc_init_array+0x1e>
 8007ff8:	0800c0dc 	.word	0x0800c0dc
 8007ffc:	0800c0dc 	.word	0x0800c0dc
 8008000:	0800c0dc 	.word	0x0800c0dc
 8008004:	0800c0e0 	.word	0x0800c0e0

08008008 <__retarget_lock_init_recursive>:
 8008008:	4770      	bx	lr

0800800a <__retarget_lock_acquire_recursive>:
 800800a:	4770      	bx	lr

0800800c <__retarget_lock_release_recursive>:
 800800c:	4770      	bx	lr

0800800e <quorem>:
 800800e:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8008012:	6903      	ldr	r3, [r0, #16]
 8008014:	690c      	ldr	r4, [r1, #16]
 8008016:	42a3      	cmp	r3, r4
 8008018:	4607      	mov	r7, r0
 800801a:	db7e      	blt.n	800811a <quorem+0x10c>
 800801c:	3c01      	subs	r4, #1
 800801e:	f101 0814 	add.w	r8, r1, #20
 8008022:	00a3      	lsls	r3, r4, #2
 8008024:	f100 0514 	add.w	r5, r0, #20
 8008028:	9300      	str	r3, [sp, #0]
 800802a:	eb05 0384 	add.w	r3, r5, r4, lsl #2
 800802e:	9301      	str	r3, [sp, #4]
 8008030:	f858 3024 	ldr.w	r3, [r8, r4, lsl #2]
 8008034:	f855 2024 	ldr.w	r2, [r5, r4, lsl #2]
 8008038:	3301      	adds	r3, #1
 800803a:	429a      	cmp	r2, r3
 800803c:	eb08 0984 	add.w	r9, r8, r4, lsl #2
 8008040:	fbb2 f6f3 	udiv	r6, r2, r3
 8008044:	d32e      	bcc.n	80080a4 <quorem+0x96>
 8008046:	f04f 0a00 	mov.w	sl, #0
 800804a:	46c4      	mov	ip, r8
 800804c:	46ae      	mov	lr, r5
 800804e:	46d3      	mov	fp, sl
 8008050:	f85c 3b04 	ldr.w	r3, [ip], #4
 8008054:	b298      	uxth	r0, r3
 8008056:	fb06 a000 	mla	r0, r6, r0, sl
 800805a:	0c02      	lsrs	r2, r0, #16
 800805c:	0c1b      	lsrs	r3, r3, #16
 800805e:	fb06 2303 	mla	r3, r6, r3, r2
 8008062:	f8de 2000 	ldr.w	r2, [lr]
 8008066:	b280      	uxth	r0, r0
 8008068:	b292      	uxth	r2, r2
 800806a:	1a12      	subs	r2, r2, r0
 800806c:	445a      	add	r2, fp
 800806e:	f8de 0000 	ldr.w	r0, [lr]
 8008072:	ea4f 4a13 	mov.w	sl, r3, lsr #16
 8008076:	b29b      	uxth	r3, r3
 8008078:	ebc3 4322 	rsb	r3, r3, r2, asr #16
 800807c:	eb03 4310 	add.w	r3, r3, r0, lsr #16
 8008080:	b292      	uxth	r2, r2
 8008082:	ea42 4203 	orr.w	r2, r2, r3, lsl #16
 8008086:	45e1      	cmp	r9, ip
 8008088:	f84e 2b04 	str.w	r2, [lr], #4
 800808c:	ea4f 4b23 	mov.w	fp, r3, asr #16
 8008090:	d2de      	bcs.n	8008050 <quorem+0x42>
 8008092:	9b00      	ldr	r3, [sp, #0]
 8008094:	58eb      	ldr	r3, [r5, r3]
 8008096:	b92b      	cbnz	r3, 80080a4 <quorem+0x96>
 8008098:	9b01      	ldr	r3, [sp, #4]
 800809a:	3b04      	subs	r3, #4
 800809c:	429d      	cmp	r5, r3
 800809e:	461a      	mov	r2, r3
 80080a0:	d32f      	bcc.n	8008102 <quorem+0xf4>
 80080a2:	613c      	str	r4, [r7, #16]
 80080a4:	4638      	mov	r0, r7
 80080a6:	f001 f97d 	bl	80093a4 <__mcmp>
 80080aa:	2800      	cmp	r0, #0
 80080ac:	db25      	blt.n	80080fa <quorem+0xec>
 80080ae:	4629      	mov	r1, r5
 80080b0:	2000      	movs	r0, #0
 80080b2:	f858 2b04 	ldr.w	r2, [r8], #4
 80080b6:	f8d1 c000 	ldr.w	ip, [r1]
 80080ba:	fa1f fe82 	uxth.w	lr, r2
 80080be:	fa1f f38c 	uxth.w	r3, ip
 80080c2:	eba3 030e 	sub.w	r3, r3, lr
 80080c6:	4403      	add	r3, r0
 80080c8:	0c12      	lsrs	r2, r2, #16
 80080ca:	ebc2 4223 	rsb	r2, r2, r3, asr #16
 80080ce:	eb02 421c 	add.w	r2, r2, ip, lsr #16
 80080d2:	b29b      	uxth	r3, r3
 80080d4:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
 80080d8:	45c1      	cmp	r9, r8
 80080da:	f841 3b04 	str.w	r3, [r1], #4
 80080de:	ea4f 4022 	mov.w	r0, r2, asr #16
 80080e2:	d2e6      	bcs.n	80080b2 <quorem+0xa4>
 80080e4:	f855 2024 	ldr.w	r2, [r5, r4, lsl #2]
 80080e8:	eb05 0384 	add.w	r3, r5, r4, lsl #2
 80080ec:	b922      	cbnz	r2, 80080f8 <quorem+0xea>
 80080ee:	3b04      	subs	r3, #4
 80080f0:	429d      	cmp	r5, r3
 80080f2:	461a      	mov	r2, r3
 80080f4:	d30b      	bcc.n	800810e <quorem+0x100>
 80080f6:	613c      	str	r4, [r7, #16]
 80080f8:	3601      	adds	r6, #1
 80080fa:	4630      	mov	r0, r6
 80080fc:	b003      	add	sp, #12
 80080fe:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 8008102:	6812      	ldr	r2, [r2, #0]
 8008104:	3b04      	subs	r3, #4
 8008106:	2a00      	cmp	r2, #0
 8008108:	d1cb      	bne.n	80080a2 <quorem+0x94>
 800810a:	3c01      	subs	r4, #1
 800810c:	e7c6      	b.n	800809c <quorem+0x8e>
 800810e:	6812      	ldr	r2, [r2, #0]
 8008110:	3b04      	subs	r3, #4
 8008112:	2a00      	cmp	r2, #0
 8008114:	d1ef      	bne.n	80080f6 <quorem+0xe8>
 8008116:	3c01      	subs	r4, #1
 8008118:	e7ea      	b.n	80080f0 <quorem+0xe2>
 800811a:	2000      	movs	r0, #0
 800811c:	e7ee      	b.n	80080fc <quorem+0xee>
	...

08008120 <_dtoa_r>:
 8008120:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8008124:	69c7      	ldr	r7, [r0, #28]
 8008126:	b097      	sub	sp, #92	@ 0x5c
 8008128:	ed8d 0b04 	vstr	d0, [sp, #16]
 800812c:	ec55 4b10 	vmov	r4, r5, d0
 8008130:	9e20      	ldr	r6, [sp, #128]	@ 0x80
 8008132:	9107      	str	r1, [sp, #28]
 8008134:	4681      	mov	r9, r0
 8008136:	920c      	str	r2, [sp, #48]	@ 0x30
 8008138:	9311      	str	r3, [sp, #68]	@ 0x44
 800813a:	b97f      	cbnz	r7, 800815c <_dtoa_r+0x3c>
 800813c:	2010      	movs	r0, #16
 800813e:	f000 fe09 	bl	8008d54 <malloc>
 8008142:	4602      	mov	r2, r0
 8008144:	f8c9 001c 	str.w	r0, [r9, #28]
 8008148:	b920      	cbnz	r0, 8008154 <_dtoa_r+0x34>
 800814a:	4ba9      	ldr	r3, [pc, #676]	@ (80083f0 <_dtoa_r+0x2d0>)
 800814c:	21ef      	movs	r1, #239	@ 0xef
 800814e:	48a9      	ldr	r0, [pc, #676]	@ (80083f4 <_dtoa_r+0x2d4>)
 8008150:	f001 fe42 	bl	8009dd8 <__assert_func>
 8008154:	e9c0 7701 	strd	r7, r7, [r0, #4]
 8008158:	6007      	str	r7, [r0, #0]
 800815a:	60c7      	str	r7, [r0, #12]
 800815c:	f8d9 301c 	ldr.w	r3, [r9, #28]
 8008160:	6819      	ldr	r1, [r3, #0]
 8008162:	b159      	cbz	r1, 800817c <_dtoa_r+0x5c>
 8008164:	685a      	ldr	r2, [r3, #4]
 8008166:	604a      	str	r2, [r1, #4]
 8008168:	2301      	movs	r3, #1
 800816a:	4093      	lsls	r3, r2
 800816c:	608b      	str	r3, [r1, #8]
 800816e:	4648      	mov	r0, r9
 8008170:	f000 fee6 	bl	8008f40 <_Bfree>
 8008174:	f8d9 301c 	ldr.w	r3, [r9, #28]
 8008178:	2200      	movs	r2, #0
 800817a:	601a      	str	r2, [r3, #0]
 800817c:	1e2b      	subs	r3, r5, #0
 800817e:	bfb9      	ittee	lt
 8008180:	f023 4300 	biclt.w	r3, r3, #2147483648	@ 0x80000000
 8008184:	9305      	strlt	r3, [sp, #20]
 8008186:	2300      	movge	r3, #0
 8008188:	6033      	strge	r3, [r6, #0]
 800818a:	9f05      	ldr	r7, [sp, #20]
 800818c:	4b9a      	ldr	r3, [pc, #616]	@ (80083f8 <_dtoa_r+0x2d8>)
 800818e:	bfbc      	itt	lt
 8008190:	2201      	movlt	r2, #1
 8008192:	6032      	strlt	r2, [r6, #0]
 8008194:	43bb      	bics	r3, r7
 8008196:	d112      	bne.n	80081be <_dtoa_r+0x9e>
 8008198:	9a11      	ldr	r2, [sp, #68]	@ 0x44
 800819a:	f242 730f 	movw	r3, #9999	@ 0x270f
 800819e:	6013      	str	r3, [r2, #0]
 80081a0:	f3c7 0313 	ubfx	r3, r7, #0, #20
 80081a4:	4323      	orrs	r3, r4
 80081a6:	f000 855a 	beq.w	8008c5e <_dtoa_r+0xb3e>
 80081aa:	9b21      	ldr	r3, [sp, #132]	@ 0x84
 80081ac:	f8df a25c 	ldr.w	sl, [pc, #604]	@ 800840c <_dtoa_r+0x2ec>
 80081b0:	2b00      	cmp	r3, #0
 80081b2:	f000 855c 	beq.w	8008c6e <_dtoa_r+0xb4e>
 80081b6:	f10a 0303 	add.w	r3, sl, #3
 80081ba:	f000 bd56 	b.w	8008c6a <_dtoa_r+0xb4a>
 80081be:	ed9d 7b04 	vldr	d7, [sp, #16]
 80081c2:	2200      	movs	r2, #0
 80081c4:	ec51 0b17 	vmov	r0, r1, d7
 80081c8:	2300      	movs	r3, #0
 80081ca:	ed8d 7b0a 	vstr	d7, [sp, #40]	@ 0x28
 80081ce:	f7f8 fc83 	bl	8000ad8 <__aeabi_dcmpeq>
 80081d2:	4680      	mov	r8, r0
 80081d4:	b158      	cbz	r0, 80081ee <_dtoa_r+0xce>
 80081d6:	9a11      	ldr	r2, [sp, #68]	@ 0x44
 80081d8:	2301      	movs	r3, #1
 80081da:	6013      	str	r3, [r2, #0]
 80081dc:	9b21      	ldr	r3, [sp, #132]	@ 0x84
 80081de:	b113      	cbz	r3, 80081e6 <_dtoa_r+0xc6>
 80081e0:	9a21      	ldr	r2, [sp, #132]	@ 0x84
 80081e2:	4b86      	ldr	r3, [pc, #536]	@ (80083fc <_dtoa_r+0x2dc>)
 80081e4:	6013      	str	r3, [r2, #0]
 80081e6:	f8df a228 	ldr.w	sl, [pc, #552]	@ 8008410 <_dtoa_r+0x2f0>
 80081ea:	f000 bd40 	b.w	8008c6e <_dtoa_r+0xb4e>
 80081ee:	ed9d 0b0a 	vldr	d0, [sp, #40]	@ 0x28
 80081f2:	aa14      	add	r2, sp, #80	@ 0x50
 80081f4:	a915      	add	r1, sp, #84	@ 0x54
 80081f6:	4648      	mov	r0, r9
 80081f8:	f001 f984 	bl	8009504 <__d2b>
 80081fc:	f3c7 560a 	ubfx	r6, r7, #20, #11
 8008200:	9002      	str	r0, [sp, #8]
 8008202:	2e00      	cmp	r6, #0
 8008204:	d078      	beq.n	80082f8 <_dtoa_r+0x1d8>
 8008206:	9b0b      	ldr	r3, [sp, #44]	@ 0x2c
 8008208:	f8cd 8048 	str.w	r8, [sp, #72]	@ 0x48
 800820c:	f3c3 0313 	ubfx	r3, r3, #0, #20
 8008210:	e9dd 010a 	ldrd	r0, r1, [sp, #40]	@ 0x28
 8008214:	f043 537f 	orr.w	r3, r3, #1069547520	@ 0x3fc00000
 8008218:	f443 1340 	orr.w	r3, r3, #3145728	@ 0x300000
 800821c:	f2a6 36ff 	subw	r6, r6, #1023	@ 0x3ff
 8008220:	4619      	mov	r1, r3
 8008222:	2200      	movs	r2, #0
 8008224:	4b76      	ldr	r3, [pc, #472]	@ (8008400 <_dtoa_r+0x2e0>)
 8008226:	f7f8 f837 	bl	8000298 <__aeabi_dsub>
 800822a:	a36b      	add	r3, pc, #428	@ (adr r3, 80083d8 <_dtoa_r+0x2b8>)
 800822c:	e9d3 2300 	ldrd	r2, r3, [r3]
 8008230:	f7f8 f9ea 	bl	8000608 <__aeabi_dmul>
 8008234:	a36a      	add	r3, pc, #424	@ (adr r3, 80083e0 <_dtoa_r+0x2c0>)
 8008236:	e9d3 2300 	ldrd	r2, r3, [r3]
 800823a:	f7f8 f82f 	bl	800029c <__adddf3>
 800823e:	4604      	mov	r4, r0
 8008240:	4630      	mov	r0, r6
 8008242:	460d      	mov	r5, r1
 8008244:	f7f8 f976 	bl	8000534 <__aeabi_i2d>
 8008248:	a367      	add	r3, pc, #412	@ (adr r3, 80083e8 <_dtoa_r+0x2c8>)
 800824a:	e9d3 2300 	ldrd	r2, r3, [r3]
 800824e:	f7f8 f9db 	bl	8000608 <__aeabi_dmul>
 8008252:	4602      	mov	r2, r0
 8008254:	460b      	mov	r3, r1
 8008256:	4620      	mov	r0, r4
 8008258:	4629      	mov	r1, r5
 800825a:	f7f8 f81f 	bl	800029c <__adddf3>
 800825e:	4604      	mov	r4, r0
 8008260:	460d      	mov	r5, r1
 8008262:	f7f8 fc81 	bl	8000b68 <__aeabi_d2iz>
 8008266:	2200      	movs	r2, #0
 8008268:	4607      	mov	r7, r0
 800826a:	2300      	movs	r3, #0
 800826c:	4620      	mov	r0, r4
 800826e:	4629      	mov	r1, r5
 8008270:	f7f8 fc3c 	bl	8000aec <__aeabi_dcmplt>
 8008274:	b140      	cbz	r0, 8008288 <_dtoa_r+0x168>
 8008276:	4638      	mov	r0, r7
 8008278:	f7f8 f95c 	bl	8000534 <__aeabi_i2d>
 800827c:	4622      	mov	r2, r4
 800827e:	462b      	mov	r3, r5
 8008280:	f7f8 fc2a 	bl	8000ad8 <__aeabi_dcmpeq>
 8008284:	b900      	cbnz	r0, 8008288 <_dtoa_r+0x168>
 8008286:	3f01      	subs	r7, #1
 8008288:	2f16      	cmp	r7, #22
 800828a:	d852      	bhi.n	8008332 <_dtoa_r+0x212>
 800828c:	4b5d      	ldr	r3, [pc, #372]	@ (8008404 <_dtoa_r+0x2e4>)
 800828e:	eb03 03c7 	add.w	r3, r3, r7, lsl #3
 8008292:	e9d3 2300 	ldrd	r2, r3, [r3]
 8008296:	e9dd 010a 	ldrd	r0, r1, [sp, #40]	@ 0x28
 800829a:	f7f8 fc27 	bl	8000aec <__aeabi_dcmplt>
 800829e:	2800      	cmp	r0, #0
 80082a0:	d049      	beq.n	8008336 <_dtoa_r+0x216>
 80082a2:	3f01      	subs	r7, #1
 80082a4:	2300      	movs	r3, #0
 80082a6:	9310      	str	r3, [sp, #64]	@ 0x40
 80082a8:	9b14      	ldr	r3, [sp, #80]	@ 0x50
 80082aa:	1b9b      	subs	r3, r3, r6
 80082ac:	1e5a      	subs	r2, r3, #1
 80082ae:	bf45      	ittet	mi
 80082b0:	f1c3 0301 	rsbmi	r3, r3, #1
 80082b4:	9300      	strmi	r3, [sp, #0]
 80082b6:	2300      	movpl	r3, #0
 80082b8:	2300      	movmi	r3, #0
 80082ba:	9206      	str	r2, [sp, #24]
 80082bc:	bf54      	ite	pl
 80082be:	9300      	strpl	r3, [sp, #0]
 80082c0:	9306      	strmi	r3, [sp, #24]
 80082c2:	2f00      	cmp	r7, #0
 80082c4:	db39      	blt.n	800833a <_dtoa_r+0x21a>
 80082c6:	9b06      	ldr	r3, [sp, #24]
 80082c8:	970d      	str	r7, [sp, #52]	@ 0x34
 80082ca:	443b      	add	r3, r7
 80082cc:	9306      	str	r3, [sp, #24]
 80082ce:	2300      	movs	r3, #0
 80082d0:	9308      	str	r3, [sp, #32]
 80082d2:	9b07      	ldr	r3, [sp, #28]
 80082d4:	2b09      	cmp	r3, #9
 80082d6:	d863      	bhi.n	80083a0 <_dtoa_r+0x280>
 80082d8:	2b05      	cmp	r3, #5
 80082da:	bfc4      	itt	gt
 80082dc:	3b04      	subgt	r3, #4
 80082de:	9307      	strgt	r3, [sp, #28]
 80082e0:	9b07      	ldr	r3, [sp, #28]
 80082e2:	f1a3 0302 	sub.w	r3, r3, #2
 80082e6:	bfcc      	ite	gt
 80082e8:	2400      	movgt	r4, #0
 80082ea:	2401      	movle	r4, #1
 80082ec:	2b03      	cmp	r3, #3
 80082ee:	d863      	bhi.n	80083b8 <_dtoa_r+0x298>
 80082f0:	e8df f003 	tbb	[pc, r3]
 80082f4:	2b375452 	.word	0x2b375452
 80082f8:	e9dd 6314 	ldrd	r6, r3, [sp, #80]	@ 0x50
 80082fc:	441e      	add	r6, r3
 80082fe:	f206 4332 	addw	r3, r6, #1074	@ 0x432
 8008302:	2b20      	cmp	r3, #32
 8008304:	bfc1      	itttt	gt
 8008306:	f1c3 0340 	rsbgt	r3, r3, #64	@ 0x40
 800830a:	409f      	lslgt	r7, r3
 800830c:	f206 4312 	addwgt	r3, r6, #1042	@ 0x412
 8008310:	fa24 f303 	lsrgt.w	r3, r4, r3
 8008314:	bfd6      	itet	le
 8008316:	f1c3 0320 	rsble	r3, r3, #32
 800831a:	ea47 0003 	orrgt.w	r0, r7, r3
 800831e:	fa04 f003 	lslle.w	r0, r4, r3
 8008322:	f7f8 f8f7 	bl	8000514 <__aeabi_ui2d>
 8008326:	2201      	movs	r2, #1
 8008328:	f1a1 73f8 	sub.w	r3, r1, #32505856	@ 0x1f00000
 800832c:	3e01      	subs	r6, #1
 800832e:	9212      	str	r2, [sp, #72]	@ 0x48
 8008330:	e776      	b.n	8008220 <_dtoa_r+0x100>
 8008332:	2301      	movs	r3, #1
 8008334:	e7b7      	b.n	80082a6 <_dtoa_r+0x186>
 8008336:	9010      	str	r0, [sp, #64]	@ 0x40
 8008338:	e7b6      	b.n	80082a8 <_dtoa_r+0x188>
 800833a:	9b00      	ldr	r3, [sp, #0]
 800833c:	1bdb      	subs	r3, r3, r7
 800833e:	9300      	str	r3, [sp, #0]
 8008340:	427b      	negs	r3, r7
 8008342:	9308      	str	r3, [sp, #32]
 8008344:	2300      	movs	r3, #0
 8008346:	930d      	str	r3, [sp, #52]	@ 0x34
 8008348:	e7c3      	b.n	80082d2 <_dtoa_r+0x1b2>
 800834a:	2301      	movs	r3, #1
 800834c:	9309      	str	r3, [sp, #36]	@ 0x24
 800834e:	9b0c      	ldr	r3, [sp, #48]	@ 0x30
 8008350:	eb07 0b03 	add.w	fp, r7, r3
 8008354:	f10b 0301 	add.w	r3, fp, #1
 8008358:	2b01      	cmp	r3, #1
 800835a:	9303      	str	r3, [sp, #12]
 800835c:	bfb8      	it	lt
 800835e:	2301      	movlt	r3, #1
 8008360:	e006      	b.n	8008370 <_dtoa_r+0x250>
 8008362:	2301      	movs	r3, #1
 8008364:	9309      	str	r3, [sp, #36]	@ 0x24
 8008366:	9b0c      	ldr	r3, [sp, #48]	@ 0x30
 8008368:	2b00      	cmp	r3, #0
 800836a:	dd28      	ble.n	80083be <_dtoa_r+0x29e>
 800836c:	469b      	mov	fp, r3
 800836e:	9303      	str	r3, [sp, #12]
 8008370:	f8d9 001c 	ldr.w	r0, [r9, #28]
 8008374:	2100      	movs	r1, #0
 8008376:	2204      	movs	r2, #4
 8008378:	f102 0514 	add.w	r5, r2, #20
 800837c:	429d      	cmp	r5, r3
 800837e:	d926      	bls.n	80083ce <_dtoa_r+0x2ae>
 8008380:	6041      	str	r1, [r0, #4]
 8008382:	4648      	mov	r0, r9
 8008384:	f000 fd9c 	bl	8008ec0 <_Balloc>
 8008388:	4682      	mov	sl, r0
 800838a:	2800      	cmp	r0, #0
 800838c:	d142      	bne.n	8008414 <_dtoa_r+0x2f4>
 800838e:	4b1e      	ldr	r3, [pc, #120]	@ (8008408 <_dtoa_r+0x2e8>)
 8008390:	4602      	mov	r2, r0
 8008392:	f240 11af 	movw	r1, #431	@ 0x1af
 8008396:	e6da      	b.n	800814e <_dtoa_r+0x2e>
 8008398:	2300      	movs	r3, #0
 800839a:	e7e3      	b.n	8008364 <_dtoa_r+0x244>
 800839c:	2300      	movs	r3, #0
 800839e:	e7d5      	b.n	800834c <_dtoa_r+0x22c>
 80083a0:	2401      	movs	r4, #1
 80083a2:	2300      	movs	r3, #0
 80083a4:	9307      	str	r3, [sp, #28]
 80083a6:	9409      	str	r4, [sp, #36]	@ 0x24
 80083a8:	f04f 3bff 	mov.w	fp, #4294967295
 80083ac:	2200      	movs	r2, #0
 80083ae:	f8cd b00c 	str.w	fp, [sp, #12]
 80083b2:	2312      	movs	r3, #18
 80083b4:	920c      	str	r2, [sp, #48]	@ 0x30
 80083b6:	e7db      	b.n	8008370 <_dtoa_r+0x250>
 80083b8:	2301      	movs	r3, #1
 80083ba:	9309      	str	r3, [sp, #36]	@ 0x24
 80083bc:	e7f4      	b.n	80083a8 <_dtoa_r+0x288>
 80083be:	f04f 0b01 	mov.w	fp, #1
 80083c2:	f8cd b00c 	str.w	fp, [sp, #12]
 80083c6:	465b      	mov	r3, fp
 80083c8:	f8cd b030 	str.w	fp, [sp, #48]	@ 0x30
 80083cc:	e7d0      	b.n	8008370 <_dtoa_r+0x250>
 80083ce:	3101      	adds	r1, #1
 80083d0:	0052      	lsls	r2, r2, #1
 80083d2:	e7d1      	b.n	8008378 <_dtoa_r+0x258>
 80083d4:	f3af 8000 	nop.w
 80083d8:	636f4361 	.word	0x636f4361
 80083dc:	3fd287a7 	.word	0x3fd287a7
 80083e0:	8b60c8b3 	.word	0x8b60c8b3
 80083e4:	3fc68a28 	.word	0x3fc68a28
 80083e8:	509f79fb 	.word	0x509f79fb
 80083ec:	3fd34413 	.word	0x3fd34413
 80083f0:	0800b97d 	.word	0x0800b97d
 80083f4:	0800b994 	.word	0x0800b994
 80083f8:	7ff00000 	.word	0x7ff00000
 80083fc:	0800b94d 	.word	0x0800b94d
 8008400:	3ff80000 	.word	0x3ff80000
 8008404:	0800bae8 	.word	0x0800bae8
 8008408:	0800b9ec 	.word	0x0800b9ec
 800840c:	0800b979 	.word	0x0800b979
 8008410:	0800b94c 	.word	0x0800b94c
 8008414:	f8d9 301c 	ldr.w	r3, [r9, #28]
 8008418:	6018      	str	r0, [r3, #0]
 800841a:	9b03      	ldr	r3, [sp, #12]
 800841c:	2b0e      	cmp	r3, #14
 800841e:	f200 80a1 	bhi.w	8008564 <_dtoa_r+0x444>
 8008422:	2c00      	cmp	r4, #0
 8008424:	f000 809e 	beq.w	8008564 <_dtoa_r+0x444>
 8008428:	2f00      	cmp	r7, #0
 800842a:	dd33      	ble.n	8008494 <_dtoa_r+0x374>
 800842c:	4b9c      	ldr	r3, [pc, #624]	@ (80086a0 <_dtoa_r+0x580>)
 800842e:	f007 020f 	and.w	r2, r7, #15
 8008432:	eb03 03c2 	add.w	r3, r3, r2, lsl #3
 8008436:	ed93 7b00 	vldr	d7, [r3]
 800843a:	05f8      	lsls	r0, r7, #23
 800843c:	ed8d 7b0e 	vstr	d7, [sp, #56]	@ 0x38
 8008440:	ea4f 1427 	mov.w	r4, r7, asr #4
 8008444:	d516      	bpl.n	8008474 <_dtoa_r+0x354>
 8008446:	4b97      	ldr	r3, [pc, #604]	@ (80086a4 <_dtoa_r+0x584>)
 8008448:	e9dd 010a 	ldrd	r0, r1, [sp, #40]	@ 0x28
 800844c:	e9d3 2308 	ldrd	r2, r3, [r3, #32]
 8008450:	f7f8 fa04 	bl	800085c <__aeabi_ddiv>
 8008454:	e9cd 0104 	strd	r0, r1, [sp, #16]
 8008458:	f004 040f 	and.w	r4, r4, #15
 800845c:	2603      	movs	r6, #3
 800845e:	4d91      	ldr	r5, [pc, #580]	@ (80086a4 <_dtoa_r+0x584>)
 8008460:	b954      	cbnz	r4, 8008478 <_dtoa_r+0x358>
 8008462:	e9dd 230e 	ldrd	r2, r3, [sp, #56]	@ 0x38
 8008466:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 800846a:	f7f8 f9f7 	bl	800085c <__aeabi_ddiv>
 800846e:	e9cd 0104 	strd	r0, r1, [sp, #16]
 8008472:	e028      	b.n	80084c6 <_dtoa_r+0x3a6>
 8008474:	2602      	movs	r6, #2
 8008476:	e7f2      	b.n	800845e <_dtoa_r+0x33e>
 8008478:	07e1      	lsls	r1, r4, #31
 800847a:	d508      	bpl.n	800848e <_dtoa_r+0x36e>
 800847c:	e9dd 010e 	ldrd	r0, r1, [sp, #56]	@ 0x38
 8008480:	e9d5 2300 	ldrd	r2, r3, [r5]
 8008484:	f7f8 f8c0 	bl	8000608 <__aeabi_dmul>
 8008488:	e9cd 010e 	strd	r0, r1, [sp, #56]	@ 0x38
 800848c:	3601      	adds	r6, #1
 800848e:	1064      	asrs	r4, r4, #1
 8008490:	3508      	adds	r5, #8
 8008492:	e7e5      	b.n	8008460 <_dtoa_r+0x340>
 8008494:	f000 80af 	beq.w	80085f6 <_dtoa_r+0x4d6>
 8008498:	427c      	negs	r4, r7
 800849a:	4b81      	ldr	r3, [pc, #516]	@ (80086a0 <_dtoa_r+0x580>)
 800849c:	4d81      	ldr	r5, [pc, #516]	@ (80086a4 <_dtoa_r+0x584>)
 800849e:	f004 020f 	and.w	r2, r4, #15
 80084a2:	eb03 03c2 	add.w	r3, r3, r2, lsl #3
 80084a6:	e9d3 2300 	ldrd	r2, r3, [r3]
 80084aa:	e9dd 010a 	ldrd	r0, r1, [sp, #40]	@ 0x28
 80084ae:	f7f8 f8ab 	bl	8000608 <__aeabi_dmul>
 80084b2:	e9cd 0104 	strd	r0, r1, [sp, #16]
 80084b6:	1124      	asrs	r4, r4, #4
 80084b8:	2300      	movs	r3, #0
 80084ba:	2602      	movs	r6, #2
 80084bc:	2c00      	cmp	r4, #0
 80084be:	f040 808f 	bne.w	80085e0 <_dtoa_r+0x4c0>
 80084c2:	2b00      	cmp	r3, #0
 80084c4:	d1d3      	bne.n	800846e <_dtoa_r+0x34e>
 80084c6:	9b10      	ldr	r3, [sp, #64]	@ 0x40
 80084c8:	e9dd 4504 	ldrd	r4, r5, [sp, #16]
 80084cc:	2b00      	cmp	r3, #0
 80084ce:	f000 8094 	beq.w	80085fa <_dtoa_r+0x4da>
 80084d2:	4b75      	ldr	r3, [pc, #468]	@ (80086a8 <_dtoa_r+0x588>)
 80084d4:	2200      	movs	r2, #0
 80084d6:	4620      	mov	r0, r4
 80084d8:	4629      	mov	r1, r5
 80084da:	f7f8 fb07 	bl	8000aec <__aeabi_dcmplt>
 80084de:	2800      	cmp	r0, #0
 80084e0:	f000 808b 	beq.w	80085fa <_dtoa_r+0x4da>
 80084e4:	9b03      	ldr	r3, [sp, #12]
 80084e6:	2b00      	cmp	r3, #0
 80084e8:	f000 8087 	beq.w	80085fa <_dtoa_r+0x4da>
 80084ec:	f1bb 0f00 	cmp.w	fp, #0
 80084f0:	dd34      	ble.n	800855c <_dtoa_r+0x43c>
 80084f2:	4620      	mov	r0, r4
 80084f4:	4b6d      	ldr	r3, [pc, #436]	@ (80086ac <_dtoa_r+0x58c>)
 80084f6:	2200      	movs	r2, #0
 80084f8:	4629      	mov	r1, r5
 80084fa:	f7f8 f885 	bl	8000608 <__aeabi_dmul>
 80084fe:	e9cd 0104 	strd	r0, r1, [sp, #16]
 8008502:	f107 38ff 	add.w	r8, r7, #4294967295
 8008506:	3601      	adds	r6, #1
 8008508:	465c      	mov	r4, fp
 800850a:	4630      	mov	r0, r6
 800850c:	f7f8 f812 	bl	8000534 <__aeabi_i2d>
 8008510:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
 8008514:	f7f8 f878 	bl	8000608 <__aeabi_dmul>
 8008518:	4b65      	ldr	r3, [pc, #404]	@ (80086b0 <_dtoa_r+0x590>)
 800851a:	2200      	movs	r2, #0
 800851c:	f7f7 febe 	bl	800029c <__adddf3>
 8008520:	4605      	mov	r5, r0
 8008522:	f1a1 7650 	sub.w	r6, r1, #54525952	@ 0x3400000
 8008526:	2c00      	cmp	r4, #0
 8008528:	d16a      	bne.n	8008600 <_dtoa_r+0x4e0>
 800852a:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 800852e:	4b61      	ldr	r3, [pc, #388]	@ (80086b4 <_dtoa_r+0x594>)
 8008530:	2200      	movs	r2, #0
 8008532:	f7f7 feb1 	bl	8000298 <__aeabi_dsub>
 8008536:	4602      	mov	r2, r0
 8008538:	460b      	mov	r3, r1
 800853a:	e9cd 2304 	strd	r2, r3, [sp, #16]
 800853e:	462a      	mov	r2, r5
 8008540:	4633      	mov	r3, r6
 8008542:	f7f8 faf1 	bl	8000b28 <__aeabi_dcmpgt>
 8008546:	2800      	cmp	r0, #0
 8008548:	f040 8298 	bne.w	8008a7c <_dtoa_r+0x95c>
 800854c:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 8008550:	462a      	mov	r2, r5
 8008552:	f106 4300 	add.w	r3, r6, #2147483648	@ 0x80000000
 8008556:	f7f8 fac9 	bl	8000aec <__aeabi_dcmplt>
 800855a:	bb38      	cbnz	r0, 80085ac <_dtoa_r+0x48c>
 800855c:	e9dd 340a 	ldrd	r3, r4, [sp, #40]	@ 0x28
 8008560:	e9cd 3404 	strd	r3, r4, [sp, #16]
 8008564:	9b15      	ldr	r3, [sp, #84]	@ 0x54
 8008566:	2b00      	cmp	r3, #0
 8008568:	f2c0 8157 	blt.w	800881a <_dtoa_r+0x6fa>
 800856c:	2f0e      	cmp	r7, #14
 800856e:	f300 8154 	bgt.w	800881a <_dtoa_r+0x6fa>
 8008572:	4b4b      	ldr	r3, [pc, #300]	@ (80086a0 <_dtoa_r+0x580>)
 8008574:	eb03 03c7 	add.w	r3, r3, r7, lsl #3
 8008578:	ed93 7b00 	vldr	d7, [r3]
 800857c:	9b0c      	ldr	r3, [sp, #48]	@ 0x30
 800857e:	2b00      	cmp	r3, #0
 8008580:	ed8d 7b00 	vstr	d7, [sp]
 8008584:	f280 80e5 	bge.w	8008752 <_dtoa_r+0x632>
 8008588:	9b03      	ldr	r3, [sp, #12]
 800858a:	2b00      	cmp	r3, #0
 800858c:	f300 80e1 	bgt.w	8008752 <_dtoa_r+0x632>
 8008590:	d10c      	bne.n	80085ac <_dtoa_r+0x48c>
 8008592:	4b48      	ldr	r3, [pc, #288]	@ (80086b4 <_dtoa_r+0x594>)
 8008594:	2200      	movs	r2, #0
 8008596:	ec51 0b17 	vmov	r0, r1, d7
 800859a:	f7f8 f835 	bl	8000608 <__aeabi_dmul>
 800859e:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
 80085a2:	f7f8 fab7 	bl	8000b14 <__aeabi_dcmpge>
 80085a6:	2800      	cmp	r0, #0
 80085a8:	f000 8266 	beq.w	8008a78 <_dtoa_r+0x958>
 80085ac:	2400      	movs	r4, #0
 80085ae:	4625      	mov	r5, r4
 80085b0:	9b0c      	ldr	r3, [sp, #48]	@ 0x30
 80085b2:	4656      	mov	r6, sl
 80085b4:	ea6f 0803 	mvn.w	r8, r3
 80085b8:	2700      	movs	r7, #0
 80085ba:	4621      	mov	r1, r4
 80085bc:	4648      	mov	r0, r9
 80085be:	f000 fcbf 	bl	8008f40 <_Bfree>
 80085c2:	2d00      	cmp	r5, #0
 80085c4:	f000 80bd 	beq.w	8008742 <_dtoa_r+0x622>
 80085c8:	b12f      	cbz	r7, 80085d6 <_dtoa_r+0x4b6>
 80085ca:	42af      	cmp	r7, r5
 80085cc:	d003      	beq.n	80085d6 <_dtoa_r+0x4b6>
 80085ce:	4639      	mov	r1, r7
 80085d0:	4648      	mov	r0, r9
 80085d2:	f000 fcb5 	bl	8008f40 <_Bfree>
 80085d6:	4629      	mov	r1, r5
 80085d8:	4648      	mov	r0, r9
 80085da:	f000 fcb1 	bl	8008f40 <_Bfree>
 80085de:	e0b0      	b.n	8008742 <_dtoa_r+0x622>
 80085e0:	07e2      	lsls	r2, r4, #31
 80085e2:	d505      	bpl.n	80085f0 <_dtoa_r+0x4d0>
 80085e4:	e9d5 2300 	ldrd	r2, r3, [r5]
 80085e8:	f7f8 f80e 	bl	8000608 <__aeabi_dmul>
 80085ec:	3601      	adds	r6, #1
 80085ee:	2301      	movs	r3, #1
 80085f0:	1064      	asrs	r4, r4, #1
 80085f2:	3508      	adds	r5, #8
 80085f4:	e762      	b.n	80084bc <_dtoa_r+0x39c>
 80085f6:	2602      	movs	r6, #2
 80085f8:	e765      	b.n	80084c6 <_dtoa_r+0x3a6>
 80085fa:	9c03      	ldr	r4, [sp, #12]
 80085fc:	46b8      	mov	r8, r7
 80085fe:	e784      	b.n	800850a <_dtoa_r+0x3ea>
 8008600:	4b27      	ldr	r3, [pc, #156]	@ (80086a0 <_dtoa_r+0x580>)
 8008602:	9909      	ldr	r1, [sp, #36]	@ 0x24
 8008604:	eb03 03c4 	add.w	r3, r3, r4, lsl #3
 8008608:	e953 2302 	ldrd	r2, r3, [r3, #-8]
 800860c:	4454      	add	r4, sl
 800860e:	2900      	cmp	r1, #0
 8008610:	d054      	beq.n	80086bc <_dtoa_r+0x59c>
 8008612:	4929      	ldr	r1, [pc, #164]	@ (80086b8 <_dtoa_r+0x598>)
 8008614:	2000      	movs	r0, #0
 8008616:	f7f8 f921 	bl	800085c <__aeabi_ddiv>
 800861a:	4633      	mov	r3, r6
 800861c:	462a      	mov	r2, r5
 800861e:	f7f7 fe3b 	bl	8000298 <__aeabi_dsub>
 8008622:	e9cd 010e 	strd	r0, r1, [sp, #56]	@ 0x38
 8008626:	4656      	mov	r6, sl
 8008628:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 800862c:	f7f8 fa9c 	bl	8000b68 <__aeabi_d2iz>
 8008630:	4605      	mov	r5, r0
 8008632:	f7f7 ff7f 	bl	8000534 <__aeabi_i2d>
 8008636:	4602      	mov	r2, r0
 8008638:	460b      	mov	r3, r1
 800863a:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 800863e:	f7f7 fe2b 	bl	8000298 <__aeabi_dsub>
 8008642:	3530      	adds	r5, #48	@ 0x30
 8008644:	4602      	mov	r2, r0
 8008646:	460b      	mov	r3, r1
 8008648:	e9cd 2304 	strd	r2, r3, [sp, #16]
 800864c:	f806 5b01 	strb.w	r5, [r6], #1
 8008650:	e9dd 230e 	ldrd	r2, r3, [sp, #56]	@ 0x38
 8008654:	f7f8 fa4a 	bl	8000aec <__aeabi_dcmplt>
 8008658:	2800      	cmp	r0, #0
 800865a:	d172      	bne.n	8008742 <_dtoa_r+0x622>
 800865c:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
 8008660:	4911      	ldr	r1, [pc, #68]	@ (80086a8 <_dtoa_r+0x588>)
 8008662:	2000      	movs	r0, #0
 8008664:	f7f7 fe18 	bl	8000298 <__aeabi_dsub>
 8008668:	e9dd 230e 	ldrd	r2, r3, [sp, #56]	@ 0x38
 800866c:	f7f8 fa3e 	bl	8000aec <__aeabi_dcmplt>
 8008670:	2800      	cmp	r0, #0
 8008672:	f040 80b4 	bne.w	80087de <_dtoa_r+0x6be>
 8008676:	42a6      	cmp	r6, r4
 8008678:	f43f af70 	beq.w	800855c <_dtoa_r+0x43c>
 800867c:	e9dd 010e 	ldrd	r0, r1, [sp, #56]	@ 0x38
 8008680:	4b0a      	ldr	r3, [pc, #40]	@ (80086ac <_dtoa_r+0x58c>)
 8008682:	2200      	movs	r2, #0
 8008684:	f7f7 ffc0 	bl	8000608 <__aeabi_dmul>
 8008688:	4b08      	ldr	r3, [pc, #32]	@ (80086ac <_dtoa_r+0x58c>)
 800868a:	e9cd 010e 	strd	r0, r1, [sp, #56]	@ 0x38
 800868e:	2200      	movs	r2, #0
 8008690:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 8008694:	f7f7 ffb8 	bl	8000608 <__aeabi_dmul>
 8008698:	e9cd 0104 	strd	r0, r1, [sp, #16]
 800869c:	e7c4      	b.n	8008628 <_dtoa_r+0x508>
 800869e:	bf00      	nop
 80086a0:	0800bae8 	.word	0x0800bae8
 80086a4:	0800bac0 	.word	0x0800bac0
 80086a8:	3ff00000 	.word	0x3ff00000
 80086ac:	40240000 	.word	0x40240000
 80086b0:	401c0000 	.word	0x401c0000
 80086b4:	40140000 	.word	0x40140000
 80086b8:	3fe00000 	.word	0x3fe00000
 80086bc:	4631      	mov	r1, r6
 80086be:	4628      	mov	r0, r5
 80086c0:	f7f7 ffa2 	bl	8000608 <__aeabi_dmul>
 80086c4:	e9cd 010e 	strd	r0, r1, [sp, #56]	@ 0x38
 80086c8:	9413      	str	r4, [sp, #76]	@ 0x4c
 80086ca:	4656      	mov	r6, sl
 80086cc:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 80086d0:	f7f8 fa4a 	bl	8000b68 <__aeabi_d2iz>
 80086d4:	4605      	mov	r5, r0
 80086d6:	f7f7 ff2d 	bl	8000534 <__aeabi_i2d>
 80086da:	4602      	mov	r2, r0
 80086dc:	460b      	mov	r3, r1
 80086de:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 80086e2:	f7f7 fdd9 	bl	8000298 <__aeabi_dsub>
 80086e6:	3530      	adds	r5, #48	@ 0x30
 80086e8:	f806 5b01 	strb.w	r5, [r6], #1
 80086ec:	4602      	mov	r2, r0
 80086ee:	460b      	mov	r3, r1
 80086f0:	42a6      	cmp	r6, r4
 80086f2:	e9cd 2304 	strd	r2, r3, [sp, #16]
 80086f6:	f04f 0200 	mov.w	r2, #0
 80086fa:	d124      	bne.n	8008746 <_dtoa_r+0x626>
 80086fc:	4baf      	ldr	r3, [pc, #700]	@ (80089bc <_dtoa_r+0x89c>)
 80086fe:	e9dd 010e 	ldrd	r0, r1, [sp, #56]	@ 0x38
 8008702:	f7f7 fdcb 	bl	800029c <__adddf3>
 8008706:	4602      	mov	r2, r0
 8008708:	460b      	mov	r3, r1
 800870a:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 800870e:	f7f8 fa0b 	bl	8000b28 <__aeabi_dcmpgt>
 8008712:	2800      	cmp	r0, #0
 8008714:	d163      	bne.n	80087de <_dtoa_r+0x6be>
 8008716:	e9dd 230e 	ldrd	r2, r3, [sp, #56]	@ 0x38
 800871a:	49a8      	ldr	r1, [pc, #672]	@ (80089bc <_dtoa_r+0x89c>)
 800871c:	2000      	movs	r0, #0
 800871e:	f7f7 fdbb 	bl	8000298 <__aeabi_dsub>
 8008722:	4602      	mov	r2, r0
 8008724:	460b      	mov	r3, r1
 8008726:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 800872a:	f7f8 f9df 	bl	8000aec <__aeabi_dcmplt>
 800872e:	2800      	cmp	r0, #0
 8008730:	f43f af14 	beq.w	800855c <_dtoa_r+0x43c>
 8008734:	9e13      	ldr	r6, [sp, #76]	@ 0x4c
 8008736:	1e73      	subs	r3, r6, #1
 8008738:	9313      	str	r3, [sp, #76]	@ 0x4c
 800873a:	f816 3c01 	ldrb.w	r3, [r6, #-1]
 800873e:	2b30      	cmp	r3, #48	@ 0x30
 8008740:	d0f8      	beq.n	8008734 <_dtoa_r+0x614>
 8008742:	4647      	mov	r7, r8
 8008744:	e03b      	b.n	80087be <_dtoa_r+0x69e>
 8008746:	4b9e      	ldr	r3, [pc, #632]	@ (80089c0 <_dtoa_r+0x8a0>)
 8008748:	f7f7 ff5e 	bl	8000608 <__aeabi_dmul>
 800874c:	e9cd 0104 	strd	r0, r1, [sp, #16]
 8008750:	e7bc      	b.n	80086cc <_dtoa_r+0x5ac>
 8008752:	e9dd 4504 	ldrd	r4, r5, [sp, #16]
 8008756:	4656      	mov	r6, sl
 8008758:	e9dd 2300 	ldrd	r2, r3, [sp]
 800875c:	4620      	mov	r0, r4
 800875e:	4629      	mov	r1, r5
 8008760:	f7f8 f87c 	bl	800085c <__aeabi_ddiv>
 8008764:	f7f8 fa00 	bl	8000b68 <__aeabi_d2iz>
 8008768:	4680      	mov	r8, r0
 800876a:	f7f7 fee3 	bl	8000534 <__aeabi_i2d>
 800876e:	e9dd 2300 	ldrd	r2, r3, [sp]
 8008772:	f7f7 ff49 	bl	8000608 <__aeabi_dmul>
 8008776:	4602      	mov	r2, r0
 8008778:	460b      	mov	r3, r1
 800877a:	4620      	mov	r0, r4
 800877c:	4629      	mov	r1, r5
 800877e:	f108 0430 	add.w	r4, r8, #48	@ 0x30
 8008782:	f7f7 fd89 	bl	8000298 <__aeabi_dsub>
 8008786:	f806 4b01 	strb.w	r4, [r6], #1
 800878a:	9d03      	ldr	r5, [sp, #12]
 800878c:	eba6 040a 	sub.w	r4, r6, sl
 8008790:	42a5      	cmp	r5, r4
 8008792:	4602      	mov	r2, r0
 8008794:	460b      	mov	r3, r1
 8008796:	d133      	bne.n	8008800 <_dtoa_r+0x6e0>
 8008798:	f7f7 fd80 	bl	800029c <__adddf3>
 800879c:	e9dd 2300 	ldrd	r2, r3, [sp]
 80087a0:	4604      	mov	r4, r0
 80087a2:	460d      	mov	r5, r1
 80087a4:	f7f8 f9c0 	bl	8000b28 <__aeabi_dcmpgt>
 80087a8:	b9c0      	cbnz	r0, 80087dc <_dtoa_r+0x6bc>
 80087aa:	e9dd 2300 	ldrd	r2, r3, [sp]
 80087ae:	4620      	mov	r0, r4
 80087b0:	4629      	mov	r1, r5
 80087b2:	f7f8 f991 	bl	8000ad8 <__aeabi_dcmpeq>
 80087b6:	b110      	cbz	r0, 80087be <_dtoa_r+0x69e>
 80087b8:	f018 0f01 	tst.w	r8, #1
 80087bc:	d10e      	bne.n	80087dc <_dtoa_r+0x6bc>
 80087be:	9902      	ldr	r1, [sp, #8]
 80087c0:	4648      	mov	r0, r9
 80087c2:	f000 fbbd 	bl	8008f40 <_Bfree>
 80087c6:	2300      	movs	r3, #0
 80087c8:	7033      	strb	r3, [r6, #0]
 80087ca:	9b11      	ldr	r3, [sp, #68]	@ 0x44
 80087cc:	3701      	adds	r7, #1
 80087ce:	601f      	str	r7, [r3, #0]
 80087d0:	9b21      	ldr	r3, [sp, #132]	@ 0x84
 80087d2:	2b00      	cmp	r3, #0
 80087d4:	f000 824b 	beq.w	8008c6e <_dtoa_r+0xb4e>
 80087d8:	601e      	str	r6, [r3, #0]
 80087da:	e248      	b.n	8008c6e <_dtoa_r+0xb4e>
 80087dc:	46b8      	mov	r8, r7
 80087de:	4633      	mov	r3, r6
 80087e0:	461e      	mov	r6, r3
 80087e2:	f813 2d01 	ldrb.w	r2, [r3, #-1]!
 80087e6:	2a39      	cmp	r2, #57	@ 0x39
 80087e8:	d106      	bne.n	80087f8 <_dtoa_r+0x6d8>
 80087ea:	459a      	cmp	sl, r3
 80087ec:	d1f8      	bne.n	80087e0 <_dtoa_r+0x6c0>
 80087ee:	2230      	movs	r2, #48	@ 0x30
 80087f0:	f108 0801 	add.w	r8, r8, #1
 80087f4:	f88a 2000 	strb.w	r2, [sl]
 80087f8:	781a      	ldrb	r2, [r3, #0]
 80087fa:	3201      	adds	r2, #1
 80087fc:	701a      	strb	r2, [r3, #0]
 80087fe:	e7a0      	b.n	8008742 <_dtoa_r+0x622>
 8008800:	4b6f      	ldr	r3, [pc, #444]	@ (80089c0 <_dtoa_r+0x8a0>)
 8008802:	2200      	movs	r2, #0
 8008804:	f7f7 ff00 	bl	8000608 <__aeabi_dmul>
 8008808:	2200      	movs	r2, #0
 800880a:	2300      	movs	r3, #0
 800880c:	4604      	mov	r4, r0
 800880e:	460d      	mov	r5, r1
 8008810:	f7f8 f962 	bl	8000ad8 <__aeabi_dcmpeq>
 8008814:	2800      	cmp	r0, #0
 8008816:	d09f      	beq.n	8008758 <_dtoa_r+0x638>
 8008818:	e7d1      	b.n	80087be <_dtoa_r+0x69e>
 800881a:	9a09      	ldr	r2, [sp, #36]	@ 0x24
 800881c:	2a00      	cmp	r2, #0
 800881e:	f000 80ea 	beq.w	80089f6 <_dtoa_r+0x8d6>
 8008822:	9a07      	ldr	r2, [sp, #28]
 8008824:	2a01      	cmp	r2, #1
 8008826:	f300 80cd 	bgt.w	80089c4 <_dtoa_r+0x8a4>
 800882a:	9a12      	ldr	r2, [sp, #72]	@ 0x48
 800882c:	2a00      	cmp	r2, #0
 800882e:	f000 80c1 	beq.w	80089b4 <_dtoa_r+0x894>
 8008832:	f203 4333 	addw	r3, r3, #1075	@ 0x433
 8008836:	9c08      	ldr	r4, [sp, #32]
 8008838:	9e00      	ldr	r6, [sp, #0]
 800883a:	9a00      	ldr	r2, [sp, #0]
 800883c:	441a      	add	r2, r3
 800883e:	9200      	str	r2, [sp, #0]
 8008840:	9a06      	ldr	r2, [sp, #24]
 8008842:	2101      	movs	r1, #1
 8008844:	441a      	add	r2, r3
 8008846:	4648      	mov	r0, r9
 8008848:	9206      	str	r2, [sp, #24]
 800884a:	f000 fc2d 	bl	80090a8 <__i2b>
 800884e:	4605      	mov	r5, r0
 8008850:	b166      	cbz	r6, 800886c <_dtoa_r+0x74c>
 8008852:	9b06      	ldr	r3, [sp, #24]
 8008854:	2b00      	cmp	r3, #0
 8008856:	dd09      	ble.n	800886c <_dtoa_r+0x74c>
 8008858:	42b3      	cmp	r3, r6
 800885a:	9a00      	ldr	r2, [sp, #0]
 800885c:	bfa8      	it	ge
 800885e:	4633      	movge	r3, r6
 8008860:	1ad2      	subs	r2, r2, r3
 8008862:	9200      	str	r2, [sp, #0]
 8008864:	9a06      	ldr	r2, [sp, #24]
 8008866:	1af6      	subs	r6, r6, r3
 8008868:	1ad3      	subs	r3, r2, r3
 800886a:	9306      	str	r3, [sp, #24]
 800886c:	9b08      	ldr	r3, [sp, #32]
 800886e:	b30b      	cbz	r3, 80088b4 <_dtoa_r+0x794>
 8008870:	9b09      	ldr	r3, [sp, #36]	@ 0x24
 8008872:	2b00      	cmp	r3, #0
 8008874:	f000 80c6 	beq.w	8008a04 <_dtoa_r+0x8e4>
 8008878:	2c00      	cmp	r4, #0
 800887a:	f000 80c0 	beq.w	80089fe <_dtoa_r+0x8de>
 800887e:	4629      	mov	r1, r5
 8008880:	4622      	mov	r2, r4
 8008882:	4648      	mov	r0, r9
 8008884:	f000 fcc8 	bl	8009218 <__pow5mult>
 8008888:	9a02      	ldr	r2, [sp, #8]
 800888a:	4601      	mov	r1, r0
 800888c:	4605      	mov	r5, r0
 800888e:	4648      	mov	r0, r9
 8008890:	f000 fc20 	bl	80090d4 <__multiply>
 8008894:	9902      	ldr	r1, [sp, #8]
 8008896:	4680      	mov	r8, r0
 8008898:	4648      	mov	r0, r9
 800889a:	f000 fb51 	bl	8008f40 <_Bfree>
 800889e:	9b08      	ldr	r3, [sp, #32]
 80088a0:	1b1b      	subs	r3, r3, r4
 80088a2:	9308      	str	r3, [sp, #32]
 80088a4:	f000 80b1 	beq.w	8008a0a <_dtoa_r+0x8ea>
 80088a8:	9a08      	ldr	r2, [sp, #32]
 80088aa:	4641      	mov	r1, r8
 80088ac:	4648      	mov	r0, r9
 80088ae:	f000 fcb3 	bl	8009218 <__pow5mult>
 80088b2:	9002      	str	r0, [sp, #8]
 80088b4:	2101      	movs	r1, #1
 80088b6:	4648      	mov	r0, r9
 80088b8:	f000 fbf6 	bl	80090a8 <__i2b>
 80088bc:	9b0d      	ldr	r3, [sp, #52]	@ 0x34
 80088be:	4604      	mov	r4, r0
 80088c0:	2b00      	cmp	r3, #0
 80088c2:	f000 81d8 	beq.w	8008c76 <_dtoa_r+0xb56>
 80088c6:	461a      	mov	r2, r3
 80088c8:	4601      	mov	r1, r0
 80088ca:	4648      	mov	r0, r9
 80088cc:	f000 fca4 	bl	8009218 <__pow5mult>
 80088d0:	9b07      	ldr	r3, [sp, #28]
 80088d2:	2b01      	cmp	r3, #1
 80088d4:	4604      	mov	r4, r0
 80088d6:	f300 809f 	bgt.w	8008a18 <_dtoa_r+0x8f8>
 80088da:	9b04      	ldr	r3, [sp, #16]
 80088dc:	2b00      	cmp	r3, #0
 80088de:	f040 8097 	bne.w	8008a10 <_dtoa_r+0x8f0>
 80088e2:	9b05      	ldr	r3, [sp, #20]
 80088e4:	f3c3 0313 	ubfx	r3, r3, #0, #20
 80088e8:	2b00      	cmp	r3, #0
 80088ea:	f040 8093 	bne.w	8008a14 <_dtoa_r+0x8f4>
 80088ee:	9b05      	ldr	r3, [sp, #20]
 80088f0:	f023 4300 	bic.w	r3, r3, #2147483648	@ 0x80000000
 80088f4:	0d1b      	lsrs	r3, r3, #20
 80088f6:	051b      	lsls	r3, r3, #20
 80088f8:	b133      	cbz	r3, 8008908 <_dtoa_r+0x7e8>
 80088fa:	9b00      	ldr	r3, [sp, #0]
 80088fc:	3301      	adds	r3, #1
 80088fe:	9300      	str	r3, [sp, #0]
 8008900:	9b06      	ldr	r3, [sp, #24]
 8008902:	3301      	adds	r3, #1
 8008904:	9306      	str	r3, [sp, #24]
 8008906:	2301      	movs	r3, #1
 8008908:	9308      	str	r3, [sp, #32]
 800890a:	9b0d      	ldr	r3, [sp, #52]	@ 0x34
 800890c:	2b00      	cmp	r3, #0
 800890e:	f000 81b8 	beq.w	8008c82 <_dtoa_r+0xb62>
 8008912:	6923      	ldr	r3, [r4, #16]
 8008914:	eb04 0383 	add.w	r3, r4, r3, lsl #2
 8008918:	6918      	ldr	r0, [r3, #16]
 800891a:	f000 fb79 	bl	8009010 <__hi0bits>
 800891e:	f1c0 0020 	rsb	r0, r0, #32
 8008922:	9b06      	ldr	r3, [sp, #24]
 8008924:	4418      	add	r0, r3
 8008926:	f010 001f 	ands.w	r0, r0, #31
 800892a:	f000 8082 	beq.w	8008a32 <_dtoa_r+0x912>
 800892e:	f1c0 0320 	rsb	r3, r0, #32
 8008932:	2b04      	cmp	r3, #4
 8008934:	dd73      	ble.n	8008a1e <_dtoa_r+0x8fe>
 8008936:	9b00      	ldr	r3, [sp, #0]
 8008938:	f1c0 001c 	rsb	r0, r0, #28
 800893c:	4403      	add	r3, r0
 800893e:	9300      	str	r3, [sp, #0]
 8008940:	9b06      	ldr	r3, [sp, #24]
 8008942:	4403      	add	r3, r0
 8008944:	4406      	add	r6, r0
 8008946:	9306      	str	r3, [sp, #24]
 8008948:	9b00      	ldr	r3, [sp, #0]
 800894a:	2b00      	cmp	r3, #0
 800894c:	dd05      	ble.n	800895a <_dtoa_r+0x83a>
 800894e:	9902      	ldr	r1, [sp, #8]
 8008950:	461a      	mov	r2, r3
 8008952:	4648      	mov	r0, r9
 8008954:	f000 fcba 	bl	80092cc <__lshift>
 8008958:	9002      	str	r0, [sp, #8]
 800895a:	9b06      	ldr	r3, [sp, #24]
 800895c:	2b00      	cmp	r3, #0
 800895e:	dd05      	ble.n	800896c <_dtoa_r+0x84c>
 8008960:	4621      	mov	r1, r4
 8008962:	461a      	mov	r2, r3
 8008964:	4648      	mov	r0, r9
 8008966:	f000 fcb1 	bl	80092cc <__lshift>
 800896a:	4604      	mov	r4, r0
 800896c:	9b10      	ldr	r3, [sp, #64]	@ 0x40
 800896e:	2b00      	cmp	r3, #0
 8008970:	d061      	beq.n	8008a36 <_dtoa_r+0x916>
 8008972:	9802      	ldr	r0, [sp, #8]
 8008974:	4621      	mov	r1, r4
 8008976:	f000 fd15 	bl	80093a4 <__mcmp>
 800897a:	2800      	cmp	r0, #0
 800897c:	da5b      	bge.n	8008a36 <_dtoa_r+0x916>
 800897e:	2300      	movs	r3, #0
 8008980:	9902      	ldr	r1, [sp, #8]
 8008982:	220a      	movs	r2, #10
 8008984:	4648      	mov	r0, r9
 8008986:	f000 fafd 	bl	8008f84 <__multadd>
 800898a:	9b09      	ldr	r3, [sp, #36]	@ 0x24
 800898c:	9002      	str	r0, [sp, #8]
 800898e:	f107 38ff 	add.w	r8, r7, #4294967295
 8008992:	2b00      	cmp	r3, #0
 8008994:	f000 8177 	beq.w	8008c86 <_dtoa_r+0xb66>
 8008998:	4629      	mov	r1, r5
 800899a:	2300      	movs	r3, #0
 800899c:	220a      	movs	r2, #10
 800899e:	4648      	mov	r0, r9
 80089a0:	f000 faf0 	bl	8008f84 <__multadd>
 80089a4:	f1bb 0f00 	cmp.w	fp, #0
 80089a8:	4605      	mov	r5, r0
 80089aa:	dc6f      	bgt.n	8008a8c <_dtoa_r+0x96c>
 80089ac:	9b07      	ldr	r3, [sp, #28]
 80089ae:	2b02      	cmp	r3, #2
 80089b0:	dc49      	bgt.n	8008a46 <_dtoa_r+0x926>
 80089b2:	e06b      	b.n	8008a8c <_dtoa_r+0x96c>
 80089b4:	9b14      	ldr	r3, [sp, #80]	@ 0x50
 80089b6:	f1c3 0336 	rsb	r3, r3, #54	@ 0x36
 80089ba:	e73c      	b.n	8008836 <_dtoa_r+0x716>
 80089bc:	3fe00000 	.word	0x3fe00000
 80089c0:	40240000 	.word	0x40240000
 80089c4:	9b03      	ldr	r3, [sp, #12]
 80089c6:	1e5c      	subs	r4, r3, #1
 80089c8:	9b08      	ldr	r3, [sp, #32]
 80089ca:	42a3      	cmp	r3, r4
 80089cc:	db09      	blt.n	80089e2 <_dtoa_r+0x8c2>
 80089ce:	1b1c      	subs	r4, r3, r4
 80089d0:	9b03      	ldr	r3, [sp, #12]
 80089d2:	2b00      	cmp	r3, #0
 80089d4:	f6bf af30 	bge.w	8008838 <_dtoa_r+0x718>
 80089d8:	9b00      	ldr	r3, [sp, #0]
 80089da:	9a03      	ldr	r2, [sp, #12]
 80089dc:	1a9e      	subs	r6, r3, r2
 80089de:	2300      	movs	r3, #0
 80089e0:	e72b      	b.n	800883a <_dtoa_r+0x71a>
 80089e2:	9b08      	ldr	r3, [sp, #32]
 80089e4:	9a0d      	ldr	r2, [sp, #52]	@ 0x34
 80089e6:	9408      	str	r4, [sp, #32]
 80089e8:	1ae3      	subs	r3, r4, r3
 80089ea:	441a      	add	r2, r3
 80089ec:	9e00      	ldr	r6, [sp, #0]
 80089ee:	9b03      	ldr	r3, [sp, #12]
 80089f0:	920d      	str	r2, [sp, #52]	@ 0x34
 80089f2:	2400      	movs	r4, #0
 80089f4:	e721      	b.n	800883a <_dtoa_r+0x71a>
 80089f6:	9c08      	ldr	r4, [sp, #32]
 80089f8:	9e00      	ldr	r6, [sp, #0]
 80089fa:	9d09      	ldr	r5, [sp, #36]	@ 0x24
 80089fc:	e728      	b.n	8008850 <_dtoa_r+0x730>
 80089fe:	f8dd 8008 	ldr.w	r8, [sp, #8]
 8008a02:	e751      	b.n	80088a8 <_dtoa_r+0x788>
 8008a04:	9a08      	ldr	r2, [sp, #32]
 8008a06:	9902      	ldr	r1, [sp, #8]
 8008a08:	e750      	b.n	80088ac <_dtoa_r+0x78c>
 8008a0a:	f8cd 8008 	str.w	r8, [sp, #8]
 8008a0e:	e751      	b.n	80088b4 <_dtoa_r+0x794>
 8008a10:	2300      	movs	r3, #0
 8008a12:	e779      	b.n	8008908 <_dtoa_r+0x7e8>
 8008a14:	9b04      	ldr	r3, [sp, #16]
 8008a16:	e777      	b.n	8008908 <_dtoa_r+0x7e8>
 8008a18:	2300      	movs	r3, #0
 8008a1a:	9308      	str	r3, [sp, #32]
 8008a1c:	e779      	b.n	8008912 <_dtoa_r+0x7f2>
 8008a1e:	d093      	beq.n	8008948 <_dtoa_r+0x828>
 8008a20:	9a00      	ldr	r2, [sp, #0]
 8008a22:	331c      	adds	r3, #28
 8008a24:	441a      	add	r2, r3
 8008a26:	9200      	str	r2, [sp, #0]
 8008a28:	9a06      	ldr	r2, [sp, #24]
 8008a2a:	441a      	add	r2, r3
 8008a2c:	441e      	add	r6, r3
 8008a2e:	9206      	str	r2, [sp, #24]
 8008a30:	e78a      	b.n	8008948 <_dtoa_r+0x828>
 8008a32:	4603      	mov	r3, r0
 8008a34:	e7f4      	b.n	8008a20 <_dtoa_r+0x900>
 8008a36:	9b03      	ldr	r3, [sp, #12]
 8008a38:	2b00      	cmp	r3, #0
 8008a3a:	46b8      	mov	r8, r7
 8008a3c:	dc20      	bgt.n	8008a80 <_dtoa_r+0x960>
 8008a3e:	469b      	mov	fp, r3
 8008a40:	9b07      	ldr	r3, [sp, #28]
 8008a42:	2b02      	cmp	r3, #2
 8008a44:	dd1e      	ble.n	8008a84 <_dtoa_r+0x964>
 8008a46:	f1bb 0f00 	cmp.w	fp, #0
 8008a4a:	f47f adb1 	bne.w	80085b0 <_dtoa_r+0x490>
 8008a4e:	4621      	mov	r1, r4
 8008a50:	465b      	mov	r3, fp
 8008a52:	2205      	movs	r2, #5
 8008a54:	4648      	mov	r0, r9
 8008a56:	f000 fa95 	bl	8008f84 <__multadd>
 8008a5a:	4601      	mov	r1, r0
 8008a5c:	4604      	mov	r4, r0
 8008a5e:	9802      	ldr	r0, [sp, #8]
 8008a60:	f000 fca0 	bl	80093a4 <__mcmp>
 8008a64:	2800      	cmp	r0, #0
 8008a66:	f77f ada3 	ble.w	80085b0 <_dtoa_r+0x490>
 8008a6a:	4656      	mov	r6, sl
 8008a6c:	2331      	movs	r3, #49	@ 0x31
 8008a6e:	f806 3b01 	strb.w	r3, [r6], #1
 8008a72:	f108 0801 	add.w	r8, r8, #1
 8008a76:	e59f      	b.n	80085b8 <_dtoa_r+0x498>
 8008a78:	9c03      	ldr	r4, [sp, #12]
 8008a7a:	46b8      	mov	r8, r7
 8008a7c:	4625      	mov	r5, r4
 8008a7e:	e7f4      	b.n	8008a6a <_dtoa_r+0x94a>
 8008a80:	f8dd b00c 	ldr.w	fp, [sp, #12]
 8008a84:	9b09      	ldr	r3, [sp, #36]	@ 0x24
 8008a86:	2b00      	cmp	r3, #0
 8008a88:	f000 8101 	beq.w	8008c8e <_dtoa_r+0xb6e>
 8008a8c:	2e00      	cmp	r6, #0
 8008a8e:	dd05      	ble.n	8008a9c <_dtoa_r+0x97c>
 8008a90:	4629      	mov	r1, r5
 8008a92:	4632      	mov	r2, r6
 8008a94:	4648      	mov	r0, r9
 8008a96:	f000 fc19 	bl	80092cc <__lshift>
 8008a9a:	4605      	mov	r5, r0
 8008a9c:	9b08      	ldr	r3, [sp, #32]
 8008a9e:	2b00      	cmp	r3, #0
 8008aa0:	d05c      	beq.n	8008b5c <_dtoa_r+0xa3c>
 8008aa2:	6869      	ldr	r1, [r5, #4]
 8008aa4:	4648      	mov	r0, r9
 8008aa6:	f000 fa0b 	bl	8008ec0 <_Balloc>
 8008aaa:	4606      	mov	r6, r0
 8008aac:	b928      	cbnz	r0, 8008aba <_dtoa_r+0x99a>
 8008aae:	4b82      	ldr	r3, [pc, #520]	@ (8008cb8 <_dtoa_r+0xb98>)
 8008ab0:	4602      	mov	r2, r0
 8008ab2:	f240 21ef 	movw	r1, #751	@ 0x2ef
 8008ab6:	f7ff bb4a 	b.w	800814e <_dtoa_r+0x2e>
 8008aba:	692a      	ldr	r2, [r5, #16]
 8008abc:	3202      	adds	r2, #2
 8008abe:	0092      	lsls	r2, r2, #2
 8008ac0:	f105 010c 	add.w	r1, r5, #12
 8008ac4:	300c      	adds	r0, #12
 8008ac6:	f001 f979 	bl	8009dbc <memcpy>
 8008aca:	2201      	movs	r2, #1
 8008acc:	4631      	mov	r1, r6
 8008ace:	4648      	mov	r0, r9
 8008ad0:	f000 fbfc 	bl	80092cc <__lshift>
 8008ad4:	f10a 0301 	add.w	r3, sl, #1
 8008ad8:	9300      	str	r3, [sp, #0]
 8008ada:	eb0a 030b 	add.w	r3, sl, fp
 8008ade:	9308      	str	r3, [sp, #32]
 8008ae0:	9b04      	ldr	r3, [sp, #16]
 8008ae2:	f003 0301 	and.w	r3, r3, #1
 8008ae6:	462f      	mov	r7, r5
 8008ae8:	9306      	str	r3, [sp, #24]
 8008aea:	4605      	mov	r5, r0
 8008aec:	9b00      	ldr	r3, [sp, #0]
 8008aee:	9802      	ldr	r0, [sp, #8]
 8008af0:	4621      	mov	r1, r4
 8008af2:	f103 3bff 	add.w	fp, r3, #4294967295
 8008af6:	f7ff fa8a 	bl	800800e <quorem>
 8008afa:	4603      	mov	r3, r0
 8008afc:	3330      	adds	r3, #48	@ 0x30
 8008afe:	9003      	str	r0, [sp, #12]
 8008b00:	4639      	mov	r1, r7
 8008b02:	9802      	ldr	r0, [sp, #8]
 8008b04:	9309      	str	r3, [sp, #36]	@ 0x24
 8008b06:	f000 fc4d 	bl	80093a4 <__mcmp>
 8008b0a:	462a      	mov	r2, r5
 8008b0c:	9004      	str	r0, [sp, #16]
 8008b0e:	4621      	mov	r1, r4
 8008b10:	4648      	mov	r0, r9
 8008b12:	f000 fc63 	bl	80093dc <__mdiff>
 8008b16:	68c2      	ldr	r2, [r0, #12]
 8008b18:	9b09      	ldr	r3, [sp, #36]	@ 0x24
 8008b1a:	4606      	mov	r6, r0
 8008b1c:	bb02      	cbnz	r2, 8008b60 <_dtoa_r+0xa40>
 8008b1e:	4601      	mov	r1, r0
 8008b20:	9802      	ldr	r0, [sp, #8]
 8008b22:	f000 fc3f 	bl	80093a4 <__mcmp>
 8008b26:	9b09      	ldr	r3, [sp, #36]	@ 0x24
 8008b28:	4602      	mov	r2, r0
 8008b2a:	4631      	mov	r1, r6
 8008b2c:	4648      	mov	r0, r9
 8008b2e:	920c      	str	r2, [sp, #48]	@ 0x30
 8008b30:	9309      	str	r3, [sp, #36]	@ 0x24
 8008b32:	f000 fa05 	bl	8008f40 <_Bfree>
 8008b36:	9b07      	ldr	r3, [sp, #28]
 8008b38:	9a0c      	ldr	r2, [sp, #48]	@ 0x30
 8008b3a:	9e00      	ldr	r6, [sp, #0]
 8008b3c:	ea42 0103 	orr.w	r1, r2, r3
 8008b40:	9b06      	ldr	r3, [sp, #24]
 8008b42:	4319      	orrs	r1, r3
 8008b44:	9b09      	ldr	r3, [sp, #36]	@ 0x24
 8008b46:	d10d      	bne.n	8008b64 <_dtoa_r+0xa44>
 8008b48:	2b39      	cmp	r3, #57	@ 0x39
 8008b4a:	d027      	beq.n	8008b9c <_dtoa_r+0xa7c>
 8008b4c:	9a04      	ldr	r2, [sp, #16]
 8008b4e:	2a00      	cmp	r2, #0
 8008b50:	dd01      	ble.n	8008b56 <_dtoa_r+0xa36>
 8008b52:	9b03      	ldr	r3, [sp, #12]
 8008b54:	3331      	adds	r3, #49	@ 0x31
 8008b56:	f88b 3000 	strb.w	r3, [fp]
 8008b5a:	e52e      	b.n	80085ba <_dtoa_r+0x49a>
 8008b5c:	4628      	mov	r0, r5
 8008b5e:	e7b9      	b.n	8008ad4 <_dtoa_r+0x9b4>
 8008b60:	2201      	movs	r2, #1
 8008b62:	e7e2      	b.n	8008b2a <_dtoa_r+0xa0a>
 8008b64:	9904      	ldr	r1, [sp, #16]
 8008b66:	2900      	cmp	r1, #0
 8008b68:	db04      	blt.n	8008b74 <_dtoa_r+0xa54>
 8008b6a:	9807      	ldr	r0, [sp, #28]
 8008b6c:	4301      	orrs	r1, r0
 8008b6e:	9806      	ldr	r0, [sp, #24]
 8008b70:	4301      	orrs	r1, r0
 8008b72:	d120      	bne.n	8008bb6 <_dtoa_r+0xa96>
 8008b74:	2a00      	cmp	r2, #0
 8008b76:	ddee      	ble.n	8008b56 <_dtoa_r+0xa36>
 8008b78:	9902      	ldr	r1, [sp, #8]
 8008b7a:	9300      	str	r3, [sp, #0]
 8008b7c:	2201      	movs	r2, #1
 8008b7e:	4648      	mov	r0, r9
 8008b80:	f000 fba4 	bl	80092cc <__lshift>
 8008b84:	4621      	mov	r1, r4
 8008b86:	9002      	str	r0, [sp, #8]
 8008b88:	f000 fc0c 	bl	80093a4 <__mcmp>
 8008b8c:	2800      	cmp	r0, #0
 8008b8e:	9b00      	ldr	r3, [sp, #0]
 8008b90:	dc02      	bgt.n	8008b98 <_dtoa_r+0xa78>
 8008b92:	d1e0      	bne.n	8008b56 <_dtoa_r+0xa36>
 8008b94:	07da      	lsls	r2, r3, #31
 8008b96:	d5de      	bpl.n	8008b56 <_dtoa_r+0xa36>
 8008b98:	2b39      	cmp	r3, #57	@ 0x39
 8008b9a:	d1da      	bne.n	8008b52 <_dtoa_r+0xa32>
 8008b9c:	2339      	movs	r3, #57	@ 0x39
 8008b9e:	f88b 3000 	strb.w	r3, [fp]
 8008ba2:	4633      	mov	r3, r6
 8008ba4:	461e      	mov	r6, r3
 8008ba6:	3b01      	subs	r3, #1
 8008ba8:	f816 2c01 	ldrb.w	r2, [r6, #-1]
 8008bac:	2a39      	cmp	r2, #57	@ 0x39
 8008bae:	d04e      	beq.n	8008c4e <_dtoa_r+0xb2e>
 8008bb0:	3201      	adds	r2, #1
 8008bb2:	701a      	strb	r2, [r3, #0]
 8008bb4:	e501      	b.n	80085ba <_dtoa_r+0x49a>
 8008bb6:	2a00      	cmp	r2, #0
 8008bb8:	dd03      	ble.n	8008bc2 <_dtoa_r+0xaa2>
 8008bba:	2b39      	cmp	r3, #57	@ 0x39
 8008bbc:	d0ee      	beq.n	8008b9c <_dtoa_r+0xa7c>
 8008bbe:	3301      	adds	r3, #1
 8008bc0:	e7c9      	b.n	8008b56 <_dtoa_r+0xa36>
 8008bc2:	9a00      	ldr	r2, [sp, #0]
 8008bc4:	9908      	ldr	r1, [sp, #32]
 8008bc6:	f802 3c01 	strb.w	r3, [r2, #-1]
 8008bca:	428a      	cmp	r2, r1
 8008bcc:	d028      	beq.n	8008c20 <_dtoa_r+0xb00>
 8008bce:	9902      	ldr	r1, [sp, #8]
 8008bd0:	2300      	movs	r3, #0
 8008bd2:	220a      	movs	r2, #10
 8008bd4:	4648      	mov	r0, r9
 8008bd6:	f000 f9d5 	bl	8008f84 <__multadd>
 8008bda:	42af      	cmp	r7, r5
 8008bdc:	9002      	str	r0, [sp, #8]
 8008bde:	f04f 0300 	mov.w	r3, #0
 8008be2:	f04f 020a 	mov.w	r2, #10
 8008be6:	4639      	mov	r1, r7
 8008be8:	4648      	mov	r0, r9
 8008bea:	d107      	bne.n	8008bfc <_dtoa_r+0xadc>
 8008bec:	f000 f9ca 	bl	8008f84 <__multadd>
 8008bf0:	4607      	mov	r7, r0
 8008bf2:	4605      	mov	r5, r0
 8008bf4:	9b00      	ldr	r3, [sp, #0]
 8008bf6:	3301      	adds	r3, #1
 8008bf8:	9300      	str	r3, [sp, #0]
 8008bfa:	e777      	b.n	8008aec <_dtoa_r+0x9cc>
 8008bfc:	f000 f9c2 	bl	8008f84 <__multadd>
 8008c00:	4629      	mov	r1, r5
 8008c02:	4607      	mov	r7, r0
 8008c04:	2300      	movs	r3, #0
 8008c06:	220a      	movs	r2, #10
 8008c08:	4648      	mov	r0, r9
 8008c0a:	f000 f9bb 	bl	8008f84 <__multadd>
 8008c0e:	4605      	mov	r5, r0
 8008c10:	e7f0      	b.n	8008bf4 <_dtoa_r+0xad4>
 8008c12:	f1bb 0f00 	cmp.w	fp, #0
 8008c16:	bfcc      	ite	gt
 8008c18:	465e      	movgt	r6, fp
 8008c1a:	2601      	movle	r6, #1
 8008c1c:	4456      	add	r6, sl
 8008c1e:	2700      	movs	r7, #0
 8008c20:	9902      	ldr	r1, [sp, #8]
 8008c22:	9300      	str	r3, [sp, #0]
 8008c24:	2201      	movs	r2, #1
 8008c26:	4648      	mov	r0, r9
 8008c28:	f000 fb50 	bl	80092cc <__lshift>
 8008c2c:	4621      	mov	r1, r4
 8008c2e:	9002      	str	r0, [sp, #8]
 8008c30:	f000 fbb8 	bl	80093a4 <__mcmp>
 8008c34:	2800      	cmp	r0, #0
 8008c36:	dcb4      	bgt.n	8008ba2 <_dtoa_r+0xa82>
 8008c38:	d102      	bne.n	8008c40 <_dtoa_r+0xb20>
 8008c3a:	9b00      	ldr	r3, [sp, #0]
 8008c3c:	07db      	lsls	r3, r3, #31
 8008c3e:	d4b0      	bmi.n	8008ba2 <_dtoa_r+0xa82>
 8008c40:	4633      	mov	r3, r6
 8008c42:	461e      	mov	r6, r3
 8008c44:	f813 2d01 	ldrb.w	r2, [r3, #-1]!
 8008c48:	2a30      	cmp	r2, #48	@ 0x30
 8008c4a:	d0fa      	beq.n	8008c42 <_dtoa_r+0xb22>
 8008c4c:	e4b5      	b.n	80085ba <_dtoa_r+0x49a>
 8008c4e:	459a      	cmp	sl, r3
 8008c50:	d1a8      	bne.n	8008ba4 <_dtoa_r+0xa84>
 8008c52:	2331      	movs	r3, #49	@ 0x31
 8008c54:	f108 0801 	add.w	r8, r8, #1
 8008c58:	f88a 3000 	strb.w	r3, [sl]
 8008c5c:	e4ad      	b.n	80085ba <_dtoa_r+0x49a>
 8008c5e:	9b21      	ldr	r3, [sp, #132]	@ 0x84
 8008c60:	f8df a058 	ldr.w	sl, [pc, #88]	@ 8008cbc <_dtoa_r+0xb9c>
 8008c64:	b11b      	cbz	r3, 8008c6e <_dtoa_r+0xb4e>
 8008c66:	f10a 0308 	add.w	r3, sl, #8
 8008c6a:	9a21      	ldr	r2, [sp, #132]	@ 0x84
 8008c6c:	6013      	str	r3, [r2, #0]
 8008c6e:	4650      	mov	r0, sl
 8008c70:	b017      	add	sp, #92	@ 0x5c
 8008c72:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 8008c76:	9b07      	ldr	r3, [sp, #28]
 8008c78:	2b01      	cmp	r3, #1
 8008c7a:	f77f ae2e 	ble.w	80088da <_dtoa_r+0x7ba>
 8008c7e:	9b0d      	ldr	r3, [sp, #52]	@ 0x34
 8008c80:	9308      	str	r3, [sp, #32]
 8008c82:	2001      	movs	r0, #1
 8008c84:	e64d      	b.n	8008922 <_dtoa_r+0x802>
 8008c86:	f1bb 0f00 	cmp.w	fp, #0
 8008c8a:	f77f aed9 	ble.w	8008a40 <_dtoa_r+0x920>
 8008c8e:	4656      	mov	r6, sl
 8008c90:	9802      	ldr	r0, [sp, #8]
 8008c92:	4621      	mov	r1, r4
 8008c94:	f7ff f9bb 	bl	800800e <quorem>
 8008c98:	f100 0330 	add.w	r3, r0, #48	@ 0x30
 8008c9c:	f806 3b01 	strb.w	r3, [r6], #1
 8008ca0:	eba6 020a 	sub.w	r2, r6, sl
 8008ca4:	4593      	cmp	fp, r2
 8008ca6:	ddb4      	ble.n	8008c12 <_dtoa_r+0xaf2>
 8008ca8:	9902      	ldr	r1, [sp, #8]
 8008caa:	2300      	movs	r3, #0
 8008cac:	220a      	movs	r2, #10
 8008cae:	4648      	mov	r0, r9
 8008cb0:	f000 f968 	bl	8008f84 <__multadd>
 8008cb4:	9002      	str	r0, [sp, #8]
 8008cb6:	e7eb      	b.n	8008c90 <_dtoa_r+0xb70>
 8008cb8:	0800b9ec 	.word	0x0800b9ec
 8008cbc:	0800b970 	.word	0x0800b970

08008cc0 <_free_r>:
 8008cc0:	b538      	push	{r3, r4, r5, lr}
 8008cc2:	4605      	mov	r5, r0
 8008cc4:	2900      	cmp	r1, #0
 8008cc6:	d041      	beq.n	8008d4c <_free_r+0x8c>
 8008cc8:	f851 3c04 	ldr.w	r3, [r1, #-4]
 8008ccc:	1f0c      	subs	r4, r1, #4
 8008cce:	2b00      	cmp	r3, #0
 8008cd0:	bfb8      	it	lt
 8008cd2:	18e4      	addlt	r4, r4, r3
 8008cd4:	f000 f8e8 	bl	8008ea8 <__malloc_lock>
 8008cd8:	4a1d      	ldr	r2, [pc, #116]	@ (8008d50 <_free_r+0x90>)
 8008cda:	6813      	ldr	r3, [r2, #0]
 8008cdc:	b933      	cbnz	r3, 8008cec <_free_r+0x2c>
 8008cde:	6063      	str	r3, [r4, #4]
 8008ce0:	6014      	str	r4, [r2, #0]
 8008ce2:	4628      	mov	r0, r5
 8008ce4:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 8008ce8:	f000 b8e4 	b.w	8008eb4 <__malloc_unlock>
 8008cec:	42a3      	cmp	r3, r4
 8008cee:	d908      	bls.n	8008d02 <_free_r+0x42>
 8008cf0:	6820      	ldr	r0, [r4, #0]
 8008cf2:	1821      	adds	r1, r4, r0
 8008cf4:	428b      	cmp	r3, r1
 8008cf6:	bf01      	itttt	eq
 8008cf8:	6819      	ldreq	r1, [r3, #0]
 8008cfa:	685b      	ldreq	r3, [r3, #4]
 8008cfc:	1809      	addeq	r1, r1, r0
 8008cfe:	6021      	streq	r1, [r4, #0]
 8008d00:	e7ed      	b.n	8008cde <_free_r+0x1e>
 8008d02:	461a      	mov	r2, r3
 8008d04:	685b      	ldr	r3, [r3, #4]
 8008d06:	b10b      	cbz	r3, 8008d0c <_free_r+0x4c>
 8008d08:	42a3      	cmp	r3, r4
 8008d0a:	d9fa      	bls.n	8008d02 <_free_r+0x42>
 8008d0c:	6811      	ldr	r1, [r2, #0]
 8008d0e:	1850      	adds	r0, r2, r1
 8008d10:	42a0      	cmp	r0, r4
 8008d12:	d10b      	bne.n	8008d2c <_free_r+0x6c>
 8008d14:	6820      	ldr	r0, [r4, #0]
 8008d16:	4401      	add	r1, r0
 8008d18:	1850      	adds	r0, r2, r1
 8008d1a:	4283      	cmp	r3, r0
 8008d1c:	6011      	str	r1, [r2, #0]
 8008d1e:	d1e0      	bne.n	8008ce2 <_free_r+0x22>
 8008d20:	6818      	ldr	r0, [r3, #0]
 8008d22:	685b      	ldr	r3, [r3, #4]
 8008d24:	6053      	str	r3, [r2, #4]
 8008d26:	4408      	add	r0, r1
 8008d28:	6010      	str	r0, [r2, #0]
 8008d2a:	e7da      	b.n	8008ce2 <_free_r+0x22>
 8008d2c:	d902      	bls.n	8008d34 <_free_r+0x74>
 8008d2e:	230c      	movs	r3, #12
 8008d30:	602b      	str	r3, [r5, #0]
 8008d32:	e7d6      	b.n	8008ce2 <_free_r+0x22>
 8008d34:	6820      	ldr	r0, [r4, #0]
 8008d36:	1821      	adds	r1, r4, r0
 8008d38:	428b      	cmp	r3, r1
 8008d3a:	bf04      	itt	eq
 8008d3c:	6819      	ldreq	r1, [r3, #0]
 8008d3e:	685b      	ldreq	r3, [r3, #4]
 8008d40:	6063      	str	r3, [r4, #4]
 8008d42:	bf04      	itt	eq
 8008d44:	1809      	addeq	r1, r1, r0
 8008d46:	6021      	streq	r1, [r4, #0]
 8008d48:	6054      	str	r4, [r2, #4]
 8008d4a:	e7ca      	b.n	8008ce2 <_free_r+0x22>
 8008d4c:	bd38      	pop	{r3, r4, r5, pc}
 8008d4e:	bf00      	nop
 8008d50:	200004ec 	.word	0x200004ec

08008d54 <malloc>:
 8008d54:	4b02      	ldr	r3, [pc, #8]	@ (8008d60 <malloc+0xc>)
 8008d56:	4601      	mov	r1, r0
 8008d58:	6818      	ldr	r0, [r3, #0]
 8008d5a:	f000 b825 	b.w	8008da8 <_malloc_r>
 8008d5e:	bf00      	nop
 8008d60:	20000018 	.word	0x20000018

08008d64 <sbrk_aligned>:
 8008d64:	b570      	push	{r4, r5, r6, lr}
 8008d66:	4e0f      	ldr	r6, [pc, #60]	@ (8008da4 <sbrk_aligned+0x40>)
 8008d68:	460c      	mov	r4, r1
 8008d6a:	6831      	ldr	r1, [r6, #0]
 8008d6c:	4605      	mov	r5, r0
 8008d6e:	b911      	cbnz	r1, 8008d76 <sbrk_aligned+0x12>
 8008d70:	f001 f814 	bl	8009d9c <_sbrk_r>
 8008d74:	6030      	str	r0, [r6, #0]
 8008d76:	4621      	mov	r1, r4
 8008d78:	4628      	mov	r0, r5
 8008d7a:	f001 f80f 	bl	8009d9c <_sbrk_r>
 8008d7e:	1c43      	adds	r3, r0, #1
 8008d80:	d103      	bne.n	8008d8a <sbrk_aligned+0x26>
 8008d82:	f04f 34ff 	mov.w	r4, #4294967295
 8008d86:	4620      	mov	r0, r4
 8008d88:	bd70      	pop	{r4, r5, r6, pc}
 8008d8a:	1cc4      	adds	r4, r0, #3
 8008d8c:	f024 0403 	bic.w	r4, r4, #3
 8008d90:	42a0      	cmp	r0, r4
 8008d92:	d0f8      	beq.n	8008d86 <sbrk_aligned+0x22>
 8008d94:	1a21      	subs	r1, r4, r0
 8008d96:	4628      	mov	r0, r5
 8008d98:	f001 f800 	bl	8009d9c <_sbrk_r>
 8008d9c:	3001      	adds	r0, #1
 8008d9e:	d1f2      	bne.n	8008d86 <sbrk_aligned+0x22>
 8008da0:	e7ef      	b.n	8008d82 <sbrk_aligned+0x1e>
 8008da2:	bf00      	nop
 8008da4:	200004e8 	.word	0x200004e8

08008da8 <_malloc_r>:
 8008da8:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 8008dac:	1ccd      	adds	r5, r1, #3
 8008dae:	f025 0503 	bic.w	r5, r5, #3
 8008db2:	3508      	adds	r5, #8
 8008db4:	2d0c      	cmp	r5, #12
 8008db6:	bf38      	it	cc
 8008db8:	250c      	movcc	r5, #12
 8008dba:	2d00      	cmp	r5, #0
 8008dbc:	4606      	mov	r6, r0
 8008dbe:	db01      	blt.n	8008dc4 <_malloc_r+0x1c>
 8008dc0:	42a9      	cmp	r1, r5
 8008dc2:	d904      	bls.n	8008dce <_malloc_r+0x26>
 8008dc4:	230c      	movs	r3, #12
 8008dc6:	6033      	str	r3, [r6, #0]
 8008dc8:	2000      	movs	r0, #0
 8008dca:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 8008dce:	f8df 80d4 	ldr.w	r8, [pc, #212]	@ 8008ea4 <_malloc_r+0xfc>
 8008dd2:	f000 f869 	bl	8008ea8 <__malloc_lock>
 8008dd6:	f8d8 3000 	ldr.w	r3, [r8]
 8008dda:	461c      	mov	r4, r3
 8008ddc:	bb44      	cbnz	r4, 8008e30 <_malloc_r+0x88>
 8008dde:	4629      	mov	r1, r5
 8008de0:	4630      	mov	r0, r6
 8008de2:	f7ff ffbf 	bl	8008d64 <sbrk_aligned>
 8008de6:	1c43      	adds	r3, r0, #1
 8008de8:	4604      	mov	r4, r0
 8008dea:	d158      	bne.n	8008e9e <_malloc_r+0xf6>
 8008dec:	f8d8 4000 	ldr.w	r4, [r8]
 8008df0:	4627      	mov	r7, r4
 8008df2:	2f00      	cmp	r7, #0
 8008df4:	d143      	bne.n	8008e7e <_malloc_r+0xd6>
 8008df6:	2c00      	cmp	r4, #0
 8008df8:	d04b      	beq.n	8008e92 <_malloc_r+0xea>
 8008dfa:	6823      	ldr	r3, [r4, #0]
 8008dfc:	4639      	mov	r1, r7
 8008dfe:	4630      	mov	r0, r6
 8008e00:	eb04 0903 	add.w	r9, r4, r3
 8008e04:	f000 ffca 	bl	8009d9c <_sbrk_r>
 8008e08:	4581      	cmp	r9, r0
 8008e0a:	d142      	bne.n	8008e92 <_malloc_r+0xea>
 8008e0c:	6821      	ldr	r1, [r4, #0]
 8008e0e:	1a6d      	subs	r5, r5, r1
 8008e10:	4629      	mov	r1, r5
 8008e12:	4630      	mov	r0, r6
 8008e14:	f7ff ffa6 	bl	8008d64 <sbrk_aligned>
 8008e18:	3001      	adds	r0, #1
 8008e1a:	d03a      	beq.n	8008e92 <_malloc_r+0xea>
 8008e1c:	6823      	ldr	r3, [r4, #0]
 8008e1e:	442b      	add	r3, r5
 8008e20:	6023      	str	r3, [r4, #0]
 8008e22:	f8d8 3000 	ldr.w	r3, [r8]
 8008e26:	685a      	ldr	r2, [r3, #4]
 8008e28:	bb62      	cbnz	r2, 8008e84 <_malloc_r+0xdc>
 8008e2a:	f8c8 7000 	str.w	r7, [r8]
 8008e2e:	e00f      	b.n	8008e50 <_malloc_r+0xa8>
 8008e30:	6822      	ldr	r2, [r4, #0]
 8008e32:	1b52      	subs	r2, r2, r5
 8008e34:	d420      	bmi.n	8008e78 <_malloc_r+0xd0>
 8008e36:	2a0b      	cmp	r2, #11
 8008e38:	d917      	bls.n	8008e6a <_malloc_r+0xc2>
 8008e3a:	1961      	adds	r1, r4, r5
 8008e3c:	42a3      	cmp	r3, r4
 8008e3e:	6025      	str	r5, [r4, #0]
 8008e40:	bf18      	it	ne
 8008e42:	6059      	strne	r1, [r3, #4]
 8008e44:	6863      	ldr	r3, [r4, #4]
 8008e46:	bf08      	it	eq
 8008e48:	f8c8 1000 	streq.w	r1, [r8]
 8008e4c:	5162      	str	r2, [r4, r5]
 8008e4e:	604b      	str	r3, [r1, #4]
 8008e50:	4630      	mov	r0, r6
 8008e52:	f000 f82f 	bl	8008eb4 <__malloc_unlock>
 8008e56:	f104 000b 	add.w	r0, r4, #11
 8008e5a:	1d23      	adds	r3, r4, #4
 8008e5c:	f020 0007 	bic.w	r0, r0, #7
 8008e60:	1ac2      	subs	r2, r0, r3
 8008e62:	bf1c      	itt	ne
 8008e64:	1a1b      	subne	r3, r3, r0
 8008e66:	50a3      	strne	r3, [r4, r2]
 8008e68:	e7af      	b.n	8008dca <_malloc_r+0x22>
 8008e6a:	6862      	ldr	r2, [r4, #4]
 8008e6c:	42a3      	cmp	r3, r4
 8008e6e:	bf0c      	ite	eq
 8008e70:	f8c8 2000 	streq.w	r2, [r8]
 8008e74:	605a      	strne	r2, [r3, #4]
 8008e76:	e7eb      	b.n	8008e50 <_malloc_r+0xa8>
 8008e78:	4623      	mov	r3, r4
 8008e7a:	6864      	ldr	r4, [r4, #4]
 8008e7c:	e7ae      	b.n	8008ddc <_malloc_r+0x34>
 8008e7e:	463c      	mov	r4, r7
 8008e80:	687f      	ldr	r7, [r7, #4]
 8008e82:	e7b6      	b.n	8008df2 <_malloc_r+0x4a>
 8008e84:	461a      	mov	r2, r3
 8008e86:	685b      	ldr	r3, [r3, #4]
 8008e88:	42a3      	cmp	r3, r4
 8008e8a:	d1fb      	bne.n	8008e84 <_malloc_r+0xdc>
 8008e8c:	2300      	movs	r3, #0
 8008e8e:	6053      	str	r3, [r2, #4]
 8008e90:	e7de      	b.n	8008e50 <_malloc_r+0xa8>
 8008e92:	230c      	movs	r3, #12
 8008e94:	6033      	str	r3, [r6, #0]
 8008e96:	4630      	mov	r0, r6
 8008e98:	f000 f80c 	bl	8008eb4 <__malloc_unlock>
 8008e9c:	e794      	b.n	8008dc8 <_malloc_r+0x20>
 8008e9e:	6005      	str	r5, [r0, #0]
 8008ea0:	e7d6      	b.n	8008e50 <_malloc_r+0xa8>
 8008ea2:	bf00      	nop
 8008ea4:	200004ec 	.word	0x200004ec

08008ea8 <__malloc_lock>:
 8008ea8:	4801      	ldr	r0, [pc, #4]	@ (8008eb0 <__malloc_lock+0x8>)
 8008eaa:	f7ff b8ae 	b.w	800800a <__retarget_lock_acquire_recursive>
 8008eae:	bf00      	nop
 8008eb0:	200004e4 	.word	0x200004e4

08008eb4 <__malloc_unlock>:
 8008eb4:	4801      	ldr	r0, [pc, #4]	@ (8008ebc <__malloc_unlock+0x8>)
 8008eb6:	f7ff b8a9 	b.w	800800c <__retarget_lock_release_recursive>
 8008eba:	bf00      	nop
 8008ebc:	200004e4 	.word	0x200004e4

08008ec0 <_Balloc>:
 8008ec0:	b570      	push	{r4, r5, r6, lr}
 8008ec2:	69c6      	ldr	r6, [r0, #28]
 8008ec4:	4604      	mov	r4, r0
 8008ec6:	460d      	mov	r5, r1
 8008ec8:	b976      	cbnz	r6, 8008ee8 <_Balloc+0x28>
 8008eca:	2010      	movs	r0, #16
 8008ecc:	f7ff ff42 	bl	8008d54 <malloc>
 8008ed0:	4602      	mov	r2, r0
 8008ed2:	61e0      	str	r0, [r4, #28]
 8008ed4:	b920      	cbnz	r0, 8008ee0 <_Balloc+0x20>
 8008ed6:	4b18      	ldr	r3, [pc, #96]	@ (8008f38 <_Balloc+0x78>)
 8008ed8:	4818      	ldr	r0, [pc, #96]	@ (8008f3c <_Balloc+0x7c>)
 8008eda:	216b      	movs	r1, #107	@ 0x6b
 8008edc:	f000 ff7c 	bl	8009dd8 <__assert_func>
 8008ee0:	e9c0 6601 	strd	r6, r6, [r0, #4]
 8008ee4:	6006      	str	r6, [r0, #0]
 8008ee6:	60c6      	str	r6, [r0, #12]
 8008ee8:	69e6      	ldr	r6, [r4, #28]
 8008eea:	68f3      	ldr	r3, [r6, #12]
 8008eec:	b183      	cbz	r3, 8008f10 <_Balloc+0x50>
 8008eee:	69e3      	ldr	r3, [r4, #28]
 8008ef0:	68db      	ldr	r3, [r3, #12]
 8008ef2:	f853 0025 	ldr.w	r0, [r3, r5, lsl #2]
 8008ef6:	b9b8      	cbnz	r0, 8008f28 <_Balloc+0x68>
 8008ef8:	2101      	movs	r1, #1
 8008efa:	fa01 f605 	lsl.w	r6, r1, r5
 8008efe:	1d72      	adds	r2, r6, #5
 8008f00:	0092      	lsls	r2, r2, #2
 8008f02:	4620      	mov	r0, r4
 8008f04:	f000 ff86 	bl	8009e14 <_calloc_r>
 8008f08:	b160      	cbz	r0, 8008f24 <_Balloc+0x64>
 8008f0a:	e9c0 5601 	strd	r5, r6, [r0, #4]
 8008f0e:	e00e      	b.n	8008f2e <_Balloc+0x6e>
 8008f10:	2221      	movs	r2, #33	@ 0x21
 8008f12:	2104      	movs	r1, #4
 8008f14:	4620      	mov	r0, r4
 8008f16:	f000 ff7d 	bl	8009e14 <_calloc_r>
 8008f1a:	69e3      	ldr	r3, [r4, #28]
 8008f1c:	60f0      	str	r0, [r6, #12]
 8008f1e:	68db      	ldr	r3, [r3, #12]
 8008f20:	2b00      	cmp	r3, #0
 8008f22:	d1e4      	bne.n	8008eee <_Balloc+0x2e>
 8008f24:	2000      	movs	r0, #0
 8008f26:	bd70      	pop	{r4, r5, r6, pc}
 8008f28:	6802      	ldr	r2, [r0, #0]
 8008f2a:	f843 2025 	str.w	r2, [r3, r5, lsl #2]
 8008f2e:	2300      	movs	r3, #0
 8008f30:	e9c0 3303 	strd	r3, r3, [r0, #12]
 8008f34:	e7f7      	b.n	8008f26 <_Balloc+0x66>
 8008f36:	bf00      	nop
 8008f38:	0800b97d 	.word	0x0800b97d
 8008f3c:	0800b9fd 	.word	0x0800b9fd

08008f40 <_Bfree>:
 8008f40:	b570      	push	{r4, r5, r6, lr}
 8008f42:	69c6      	ldr	r6, [r0, #28]
 8008f44:	4605      	mov	r5, r0
 8008f46:	460c      	mov	r4, r1
 8008f48:	b976      	cbnz	r6, 8008f68 <_Bfree+0x28>
 8008f4a:	2010      	movs	r0, #16
 8008f4c:	f7ff ff02 	bl	8008d54 <malloc>
 8008f50:	4602      	mov	r2, r0
 8008f52:	61e8      	str	r0, [r5, #28]
 8008f54:	b920      	cbnz	r0, 8008f60 <_Bfree+0x20>
 8008f56:	4b09      	ldr	r3, [pc, #36]	@ (8008f7c <_Bfree+0x3c>)
 8008f58:	4809      	ldr	r0, [pc, #36]	@ (8008f80 <_Bfree+0x40>)
 8008f5a:	218f      	movs	r1, #143	@ 0x8f
 8008f5c:	f000 ff3c 	bl	8009dd8 <__assert_func>
 8008f60:	e9c0 6601 	strd	r6, r6, [r0, #4]
 8008f64:	6006      	str	r6, [r0, #0]
 8008f66:	60c6      	str	r6, [r0, #12]
 8008f68:	b13c      	cbz	r4, 8008f7a <_Bfree+0x3a>
 8008f6a:	69eb      	ldr	r3, [r5, #28]
 8008f6c:	6862      	ldr	r2, [r4, #4]
 8008f6e:	68db      	ldr	r3, [r3, #12]
 8008f70:	f853 1022 	ldr.w	r1, [r3, r2, lsl #2]
 8008f74:	6021      	str	r1, [r4, #0]
 8008f76:	f843 4022 	str.w	r4, [r3, r2, lsl #2]
 8008f7a:	bd70      	pop	{r4, r5, r6, pc}
 8008f7c:	0800b97d 	.word	0x0800b97d
 8008f80:	0800b9fd 	.word	0x0800b9fd

08008f84 <__multadd>:
 8008f84:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8008f88:	690d      	ldr	r5, [r1, #16]
 8008f8a:	4607      	mov	r7, r0
 8008f8c:	460c      	mov	r4, r1
 8008f8e:	461e      	mov	r6, r3
 8008f90:	f101 0c14 	add.w	ip, r1, #20
 8008f94:	2000      	movs	r0, #0
 8008f96:	f8dc 3000 	ldr.w	r3, [ip]
 8008f9a:	b299      	uxth	r1, r3
 8008f9c:	fb02 6101 	mla	r1, r2, r1, r6
 8008fa0:	0c1e      	lsrs	r6, r3, #16
 8008fa2:	0c0b      	lsrs	r3, r1, #16
 8008fa4:	fb02 3306 	mla	r3, r2, r6, r3
 8008fa8:	b289      	uxth	r1, r1
 8008faa:	3001      	adds	r0, #1
 8008fac:	eb01 4103 	add.w	r1, r1, r3, lsl #16
 8008fb0:	4285      	cmp	r5, r0
 8008fb2:	f84c 1b04 	str.w	r1, [ip], #4
 8008fb6:	ea4f 4613 	mov.w	r6, r3, lsr #16
 8008fba:	dcec      	bgt.n	8008f96 <__multadd+0x12>
 8008fbc:	b30e      	cbz	r6, 8009002 <__multadd+0x7e>
 8008fbe:	68a3      	ldr	r3, [r4, #8]
 8008fc0:	42ab      	cmp	r3, r5
 8008fc2:	dc19      	bgt.n	8008ff8 <__multadd+0x74>
 8008fc4:	6861      	ldr	r1, [r4, #4]
 8008fc6:	4638      	mov	r0, r7
 8008fc8:	3101      	adds	r1, #1
 8008fca:	f7ff ff79 	bl	8008ec0 <_Balloc>
 8008fce:	4680      	mov	r8, r0
 8008fd0:	b928      	cbnz	r0, 8008fde <__multadd+0x5a>
 8008fd2:	4602      	mov	r2, r0
 8008fd4:	4b0c      	ldr	r3, [pc, #48]	@ (8009008 <__multadd+0x84>)
 8008fd6:	480d      	ldr	r0, [pc, #52]	@ (800900c <__multadd+0x88>)
 8008fd8:	21ba      	movs	r1, #186	@ 0xba
 8008fda:	f000 fefd 	bl	8009dd8 <__assert_func>
 8008fde:	6922      	ldr	r2, [r4, #16]
 8008fe0:	3202      	adds	r2, #2
 8008fe2:	f104 010c 	add.w	r1, r4, #12
 8008fe6:	0092      	lsls	r2, r2, #2
 8008fe8:	300c      	adds	r0, #12
 8008fea:	f000 fee7 	bl	8009dbc <memcpy>
 8008fee:	4621      	mov	r1, r4
 8008ff0:	4638      	mov	r0, r7
 8008ff2:	f7ff ffa5 	bl	8008f40 <_Bfree>
 8008ff6:	4644      	mov	r4, r8
 8008ff8:	eb04 0385 	add.w	r3, r4, r5, lsl #2
 8008ffc:	3501      	adds	r5, #1
 8008ffe:	615e      	str	r6, [r3, #20]
 8009000:	6125      	str	r5, [r4, #16]
 8009002:	4620      	mov	r0, r4
 8009004:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8009008:	0800b9ec 	.word	0x0800b9ec
 800900c:	0800b9fd 	.word	0x0800b9fd

08009010 <__hi0bits>:
 8009010:	f5b0 3f80 	cmp.w	r0, #65536	@ 0x10000
 8009014:	4603      	mov	r3, r0
 8009016:	bf36      	itet	cc
 8009018:	0403      	lslcc	r3, r0, #16
 800901a:	2000      	movcs	r0, #0
 800901c:	2010      	movcc	r0, #16
 800901e:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
 8009022:	bf3c      	itt	cc
 8009024:	021b      	lslcc	r3, r3, #8
 8009026:	3008      	addcc	r0, #8
 8009028:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
 800902c:	bf3c      	itt	cc
 800902e:	011b      	lslcc	r3, r3, #4
 8009030:	3004      	addcc	r0, #4
 8009032:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
 8009036:	bf3c      	itt	cc
 8009038:	009b      	lslcc	r3, r3, #2
 800903a:	3002      	addcc	r0, #2
 800903c:	2b00      	cmp	r3, #0
 800903e:	db05      	blt.n	800904c <__hi0bits+0x3c>
 8009040:	f013 4f80 	tst.w	r3, #1073741824	@ 0x40000000
 8009044:	f100 0001 	add.w	r0, r0, #1
 8009048:	bf08      	it	eq
 800904a:	2020      	moveq	r0, #32
 800904c:	4770      	bx	lr

0800904e <__lo0bits>:
 800904e:	6803      	ldr	r3, [r0, #0]
 8009050:	4602      	mov	r2, r0
 8009052:	f013 0007 	ands.w	r0, r3, #7
 8009056:	d00b      	beq.n	8009070 <__lo0bits+0x22>
 8009058:	07d9      	lsls	r1, r3, #31
 800905a:	d421      	bmi.n	80090a0 <__lo0bits+0x52>
 800905c:	0798      	lsls	r0, r3, #30
 800905e:	bf49      	itett	mi
 8009060:	085b      	lsrmi	r3, r3, #1
 8009062:	089b      	lsrpl	r3, r3, #2
 8009064:	2001      	movmi	r0, #1
 8009066:	6013      	strmi	r3, [r2, #0]
 8009068:	bf5c      	itt	pl
 800906a:	6013      	strpl	r3, [r2, #0]
 800906c:	2002      	movpl	r0, #2
 800906e:	4770      	bx	lr
 8009070:	b299      	uxth	r1, r3
 8009072:	b909      	cbnz	r1, 8009078 <__lo0bits+0x2a>
 8009074:	0c1b      	lsrs	r3, r3, #16
 8009076:	2010      	movs	r0, #16
 8009078:	b2d9      	uxtb	r1, r3
 800907a:	b909      	cbnz	r1, 8009080 <__lo0bits+0x32>
 800907c:	3008      	adds	r0, #8
 800907e:	0a1b      	lsrs	r3, r3, #8
 8009080:	0719      	lsls	r1, r3, #28
 8009082:	bf04      	itt	eq
 8009084:	091b      	lsreq	r3, r3, #4
 8009086:	3004      	addeq	r0, #4
 8009088:	0799      	lsls	r1, r3, #30
 800908a:	bf04      	itt	eq
 800908c:	089b      	lsreq	r3, r3, #2
 800908e:	3002      	addeq	r0, #2
 8009090:	07d9      	lsls	r1, r3, #31
 8009092:	d403      	bmi.n	800909c <__lo0bits+0x4e>
 8009094:	085b      	lsrs	r3, r3, #1
 8009096:	f100 0001 	add.w	r0, r0, #1
 800909a:	d003      	beq.n	80090a4 <__lo0bits+0x56>
 800909c:	6013      	str	r3, [r2, #0]
 800909e:	4770      	bx	lr
 80090a0:	2000      	movs	r0, #0
 80090a2:	4770      	bx	lr
 80090a4:	2020      	movs	r0, #32
 80090a6:	4770      	bx	lr

080090a8 <__i2b>:
 80090a8:	b510      	push	{r4, lr}
 80090aa:	460c      	mov	r4, r1
 80090ac:	2101      	movs	r1, #1
 80090ae:	f7ff ff07 	bl	8008ec0 <_Balloc>
 80090b2:	4602      	mov	r2, r0
 80090b4:	b928      	cbnz	r0, 80090c2 <__i2b+0x1a>
 80090b6:	4b05      	ldr	r3, [pc, #20]	@ (80090cc <__i2b+0x24>)
 80090b8:	4805      	ldr	r0, [pc, #20]	@ (80090d0 <__i2b+0x28>)
 80090ba:	f240 1145 	movw	r1, #325	@ 0x145
 80090be:	f000 fe8b 	bl	8009dd8 <__assert_func>
 80090c2:	2301      	movs	r3, #1
 80090c4:	6144      	str	r4, [r0, #20]
 80090c6:	6103      	str	r3, [r0, #16]
 80090c8:	bd10      	pop	{r4, pc}
 80090ca:	bf00      	nop
 80090cc:	0800b9ec 	.word	0x0800b9ec
 80090d0:	0800b9fd 	.word	0x0800b9fd

080090d4 <__multiply>:
 80090d4:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 80090d8:	4617      	mov	r7, r2
 80090da:	690a      	ldr	r2, [r1, #16]
 80090dc:	693b      	ldr	r3, [r7, #16]
 80090de:	429a      	cmp	r2, r3
 80090e0:	bfa8      	it	ge
 80090e2:	463b      	movge	r3, r7
 80090e4:	4689      	mov	r9, r1
 80090e6:	bfa4      	itt	ge
 80090e8:	460f      	movge	r7, r1
 80090ea:	4699      	movge	r9, r3
 80090ec:	693d      	ldr	r5, [r7, #16]
 80090ee:	f8d9 a010 	ldr.w	sl, [r9, #16]
 80090f2:	68bb      	ldr	r3, [r7, #8]
 80090f4:	6879      	ldr	r1, [r7, #4]
 80090f6:	eb05 060a 	add.w	r6, r5, sl
 80090fa:	42b3      	cmp	r3, r6
 80090fc:	b085      	sub	sp, #20
 80090fe:	bfb8      	it	lt
 8009100:	3101      	addlt	r1, #1
 8009102:	f7ff fedd 	bl	8008ec0 <_Balloc>
 8009106:	b930      	cbnz	r0, 8009116 <__multiply+0x42>
 8009108:	4602      	mov	r2, r0
 800910a:	4b41      	ldr	r3, [pc, #260]	@ (8009210 <__multiply+0x13c>)
 800910c:	4841      	ldr	r0, [pc, #260]	@ (8009214 <__multiply+0x140>)
 800910e:	f44f 71b1 	mov.w	r1, #354	@ 0x162
 8009112:	f000 fe61 	bl	8009dd8 <__assert_func>
 8009116:	f100 0414 	add.w	r4, r0, #20
 800911a:	eb04 0e86 	add.w	lr, r4, r6, lsl #2
 800911e:	4623      	mov	r3, r4
 8009120:	2200      	movs	r2, #0
 8009122:	4573      	cmp	r3, lr
 8009124:	d320      	bcc.n	8009168 <__multiply+0x94>
 8009126:	f107 0814 	add.w	r8, r7, #20
 800912a:	f109 0114 	add.w	r1, r9, #20
 800912e:	eb08 0585 	add.w	r5, r8, r5, lsl #2
 8009132:	eb01 038a 	add.w	r3, r1, sl, lsl #2
 8009136:	9302      	str	r3, [sp, #8]
 8009138:	1beb      	subs	r3, r5, r7
 800913a:	3b15      	subs	r3, #21
 800913c:	f023 0303 	bic.w	r3, r3, #3
 8009140:	3304      	adds	r3, #4
 8009142:	3715      	adds	r7, #21
 8009144:	42bd      	cmp	r5, r7
 8009146:	bf38      	it	cc
 8009148:	2304      	movcc	r3, #4
 800914a:	9301      	str	r3, [sp, #4]
 800914c:	9b02      	ldr	r3, [sp, #8]
 800914e:	9103      	str	r1, [sp, #12]
 8009150:	428b      	cmp	r3, r1
 8009152:	d80c      	bhi.n	800916e <__multiply+0x9a>
 8009154:	2e00      	cmp	r6, #0
 8009156:	dd03      	ble.n	8009160 <__multiply+0x8c>
 8009158:	f85e 3d04 	ldr.w	r3, [lr, #-4]!
 800915c:	2b00      	cmp	r3, #0
 800915e:	d055      	beq.n	800920c <__multiply+0x138>
 8009160:	6106      	str	r6, [r0, #16]
 8009162:	b005      	add	sp, #20
 8009164:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 8009168:	f843 2b04 	str.w	r2, [r3], #4
 800916c:	e7d9      	b.n	8009122 <__multiply+0x4e>
 800916e:	f8b1 a000 	ldrh.w	sl, [r1]
 8009172:	f1ba 0f00 	cmp.w	sl, #0
 8009176:	d01f      	beq.n	80091b8 <__multiply+0xe4>
 8009178:	46c4      	mov	ip, r8
 800917a:	46a1      	mov	r9, r4
 800917c:	2700      	movs	r7, #0
 800917e:	f85c 2b04 	ldr.w	r2, [ip], #4
 8009182:	f8d9 3000 	ldr.w	r3, [r9]
 8009186:	fa1f fb82 	uxth.w	fp, r2
 800918a:	b29b      	uxth	r3, r3
 800918c:	fb0a 330b 	mla	r3, sl, fp, r3
 8009190:	443b      	add	r3, r7
 8009192:	f8d9 7000 	ldr.w	r7, [r9]
 8009196:	0c12      	lsrs	r2, r2, #16
 8009198:	0c3f      	lsrs	r7, r7, #16
 800919a:	fb0a 7202 	mla	r2, sl, r2, r7
 800919e:	eb02 4213 	add.w	r2, r2, r3, lsr #16
 80091a2:	b29b      	uxth	r3, r3
 80091a4:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
 80091a8:	4565      	cmp	r5, ip
 80091aa:	f849 3b04 	str.w	r3, [r9], #4
 80091ae:	ea4f 4712 	mov.w	r7, r2, lsr #16
 80091b2:	d8e4      	bhi.n	800917e <__multiply+0xaa>
 80091b4:	9b01      	ldr	r3, [sp, #4]
 80091b6:	50e7      	str	r7, [r4, r3]
 80091b8:	9b03      	ldr	r3, [sp, #12]
 80091ba:	f8b3 9002 	ldrh.w	r9, [r3, #2]
 80091be:	3104      	adds	r1, #4
 80091c0:	f1b9 0f00 	cmp.w	r9, #0
 80091c4:	d020      	beq.n	8009208 <__multiply+0x134>
 80091c6:	6823      	ldr	r3, [r4, #0]
 80091c8:	4647      	mov	r7, r8
 80091ca:	46a4      	mov	ip, r4
 80091cc:	f04f 0a00 	mov.w	sl, #0
 80091d0:	f8b7 b000 	ldrh.w	fp, [r7]
 80091d4:	f8bc 2002 	ldrh.w	r2, [ip, #2]
 80091d8:	fb09 220b 	mla	r2, r9, fp, r2
 80091dc:	4452      	add	r2, sl
 80091de:	b29b      	uxth	r3, r3
 80091e0:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
 80091e4:	f84c 3b04 	str.w	r3, [ip], #4
 80091e8:	f857 3b04 	ldr.w	r3, [r7], #4
 80091ec:	ea4f 4a13 	mov.w	sl, r3, lsr #16
 80091f0:	f8bc 3000 	ldrh.w	r3, [ip]
 80091f4:	fb09 330a 	mla	r3, r9, sl, r3
 80091f8:	eb03 4312 	add.w	r3, r3, r2, lsr #16
 80091fc:	42bd      	cmp	r5, r7
 80091fe:	ea4f 4a13 	mov.w	sl, r3, lsr #16
 8009202:	d8e5      	bhi.n	80091d0 <__multiply+0xfc>
 8009204:	9a01      	ldr	r2, [sp, #4]
 8009206:	50a3      	str	r3, [r4, r2]
 8009208:	3404      	adds	r4, #4
 800920a:	e79f      	b.n	800914c <__multiply+0x78>
 800920c:	3e01      	subs	r6, #1
 800920e:	e7a1      	b.n	8009154 <__multiply+0x80>
 8009210:	0800b9ec 	.word	0x0800b9ec
 8009214:	0800b9fd 	.word	0x0800b9fd

08009218 <__pow5mult>:
 8009218:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 800921c:	4615      	mov	r5, r2
 800921e:	f012 0203 	ands.w	r2, r2, #3
 8009222:	4607      	mov	r7, r0
 8009224:	460e      	mov	r6, r1
 8009226:	d007      	beq.n	8009238 <__pow5mult+0x20>
 8009228:	4c25      	ldr	r4, [pc, #148]	@ (80092c0 <__pow5mult+0xa8>)
 800922a:	3a01      	subs	r2, #1
 800922c:	2300      	movs	r3, #0
 800922e:	f854 2022 	ldr.w	r2, [r4, r2, lsl #2]
 8009232:	f7ff fea7 	bl	8008f84 <__multadd>
 8009236:	4606      	mov	r6, r0
 8009238:	10ad      	asrs	r5, r5, #2
 800923a:	d03d      	beq.n	80092b8 <__pow5mult+0xa0>
 800923c:	69fc      	ldr	r4, [r7, #28]
 800923e:	b97c      	cbnz	r4, 8009260 <__pow5mult+0x48>
 8009240:	2010      	movs	r0, #16
 8009242:	f7ff fd87 	bl	8008d54 <malloc>
 8009246:	4602      	mov	r2, r0
 8009248:	61f8      	str	r0, [r7, #28]
 800924a:	b928      	cbnz	r0, 8009258 <__pow5mult+0x40>
 800924c:	4b1d      	ldr	r3, [pc, #116]	@ (80092c4 <__pow5mult+0xac>)
 800924e:	481e      	ldr	r0, [pc, #120]	@ (80092c8 <__pow5mult+0xb0>)
 8009250:	f240 11b3 	movw	r1, #435	@ 0x1b3
 8009254:	f000 fdc0 	bl	8009dd8 <__assert_func>
 8009258:	e9c0 4401 	strd	r4, r4, [r0, #4]
 800925c:	6004      	str	r4, [r0, #0]
 800925e:	60c4      	str	r4, [r0, #12]
 8009260:	f8d7 801c 	ldr.w	r8, [r7, #28]
 8009264:	f8d8 4008 	ldr.w	r4, [r8, #8]
 8009268:	b94c      	cbnz	r4, 800927e <__pow5mult+0x66>
 800926a:	f240 2171 	movw	r1, #625	@ 0x271
 800926e:	4638      	mov	r0, r7
 8009270:	f7ff ff1a 	bl	80090a8 <__i2b>
 8009274:	2300      	movs	r3, #0
 8009276:	f8c8 0008 	str.w	r0, [r8, #8]
 800927a:	4604      	mov	r4, r0
 800927c:	6003      	str	r3, [r0, #0]
 800927e:	f04f 0900 	mov.w	r9, #0
 8009282:	07eb      	lsls	r3, r5, #31
 8009284:	d50a      	bpl.n	800929c <__pow5mult+0x84>
 8009286:	4631      	mov	r1, r6
 8009288:	4622      	mov	r2, r4
 800928a:	4638      	mov	r0, r7
 800928c:	f7ff ff22 	bl	80090d4 <__multiply>
 8009290:	4631      	mov	r1, r6
 8009292:	4680      	mov	r8, r0
 8009294:	4638      	mov	r0, r7
 8009296:	f7ff fe53 	bl	8008f40 <_Bfree>
 800929a:	4646      	mov	r6, r8
 800929c:	106d      	asrs	r5, r5, #1
 800929e:	d00b      	beq.n	80092b8 <__pow5mult+0xa0>
 80092a0:	6820      	ldr	r0, [r4, #0]
 80092a2:	b938      	cbnz	r0, 80092b4 <__pow5mult+0x9c>
 80092a4:	4622      	mov	r2, r4
 80092a6:	4621      	mov	r1, r4
 80092a8:	4638      	mov	r0, r7
 80092aa:	f7ff ff13 	bl	80090d4 <__multiply>
 80092ae:	6020      	str	r0, [r4, #0]
 80092b0:	f8c0 9000 	str.w	r9, [r0]
 80092b4:	4604      	mov	r4, r0
 80092b6:	e7e4      	b.n	8009282 <__pow5mult+0x6a>
 80092b8:	4630      	mov	r0, r6
 80092ba:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 80092be:	bf00      	nop
 80092c0:	0800bab0 	.word	0x0800bab0
 80092c4:	0800b97d 	.word	0x0800b97d
 80092c8:	0800b9fd 	.word	0x0800b9fd

080092cc <__lshift>:
 80092cc:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 80092d0:	460c      	mov	r4, r1
 80092d2:	6849      	ldr	r1, [r1, #4]
 80092d4:	6923      	ldr	r3, [r4, #16]
 80092d6:	eb03 1862 	add.w	r8, r3, r2, asr #5
 80092da:	68a3      	ldr	r3, [r4, #8]
 80092dc:	4607      	mov	r7, r0
 80092de:	4691      	mov	r9, r2
 80092e0:	ea4f 1a62 	mov.w	sl, r2, asr #5
 80092e4:	f108 0601 	add.w	r6, r8, #1
 80092e8:	42b3      	cmp	r3, r6
 80092ea:	db0b      	blt.n	8009304 <__lshift+0x38>
 80092ec:	4638      	mov	r0, r7
 80092ee:	f7ff fde7 	bl	8008ec0 <_Balloc>
 80092f2:	4605      	mov	r5, r0
 80092f4:	b948      	cbnz	r0, 800930a <__lshift+0x3e>
 80092f6:	4602      	mov	r2, r0
 80092f8:	4b28      	ldr	r3, [pc, #160]	@ (800939c <__lshift+0xd0>)
 80092fa:	4829      	ldr	r0, [pc, #164]	@ (80093a0 <__lshift+0xd4>)
 80092fc:	f44f 71ef 	mov.w	r1, #478	@ 0x1de
 8009300:	f000 fd6a 	bl	8009dd8 <__assert_func>
 8009304:	3101      	adds	r1, #1
 8009306:	005b      	lsls	r3, r3, #1
 8009308:	e7ee      	b.n	80092e8 <__lshift+0x1c>
 800930a:	2300      	movs	r3, #0
 800930c:	f100 0114 	add.w	r1, r0, #20
 8009310:	f100 0210 	add.w	r2, r0, #16
 8009314:	4618      	mov	r0, r3
 8009316:	4553      	cmp	r3, sl
 8009318:	db33      	blt.n	8009382 <__lshift+0xb6>
 800931a:	6920      	ldr	r0, [r4, #16]
 800931c:	ea2a 7aea 	bic.w	sl, sl, sl, asr #31
 8009320:	f104 0314 	add.w	r3, r4, #20
 8009324:	f019 091f 	ands.w	r9, r9, #31
 8009328:	eb01 018a 	add.w	r1, r1, sl, lsl #2
 800932c:	eb03 0c80 	add.w	ip, r3, r0, lsl #2
 8009330:	d02b      	beq.n	800938a <__lshift+0xbe>
 8009332:	f1c9 0e20 	rsb	lr, r9, #32
 8009336:	468a      	mov	sl, r1
 8009338:	2200      	movs	r2, #0
 800933a:	6818      	ldr	r0, [r3, #0]
 800933c:	fa00 f009 	lsl.w	r0, r0, r9
 8009340:	4310      	orrs	r0, r2
 8009342:	f84a 0b04 	str.w	r0, [sl], #4
 8009346:	f853 2b04 	ldr.w	r2, [r3], #4
 800934a:	459c      	cmp	ip, r3
 800934c:	fa22 f20e 	lsr.w	r2, r2, lr
 8009350:	d8f3      	bhi.n	800933a <__lshift+0x6e>
 8009352:	ebac 0304 	sub.w	r3, ip, r4
 8009356:	3b15      	subs	r3, #21
 8009358:	f023 0303 	bic.w	r3, r3, #3
 800935c:	3304      	adds	r3, #4
 800935e:	f104 0015 	add.w	r0, r4, #21
 8009362:	4560      	cmp	r0, ip
 8009364:	bf88      	it	hi
 8009366:	2304      	movhi	r3, #4
 8009368:	50ca      	str	r2, [r1, r3]
 800936a:	b10a      	cbz	r2, 8009370 <__lshift+0xa4>
 800936c:	f108 0602 	add.w	r6, r8, #2
 8009370:	3e01      	subs	r6, #1
 8009372:	4638      	mov	r0, r7
 8009374:	612e      	str	r6, [r5, #16]
 8009376:	4621      	mov	r1, r4
 8009378:	f7ff fde2 	bl	8008f40 <_Bfree>
 800937c:	4628      	mov	r0, r5
 800937e:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8009382:	f842 0f04 	str.w	r0, [r2, #4]!
 8009386:	3301      	adds	r3, #1
 8009388:	e7c5      	b.n	8009316 <__lshift+0x4a>
 800938a:	3904      	subs	r1, #4
 800938c:	f853 2b04 	ldr.w	r2, [r3], #4
 8009390:	f841 2f04 	str.w	r2, [r1, #4]!
 8009394:	459c      	cmp	ip, r3
 8009396:	d8f9      	bhi.n	800938c <__lshift+0xc0>
 8009398:	e7ea      	b.n	8009370 <__lshift+0xa4>
 800939a:	bf00      	nop
 800939c:	0800b9ec 	.word	0x0800b9ec
 80093a0:	0800b9fd 	.word	0x0800b9fd

080093a4 <__mcmp>:
 80093a4:	690a      	ldr	r2, [r1, #16]
 80093a6:	4603      	mov	r3, r0
 80093a8:	6900      	ldr	r0, [r0, #16]
 80093aa:	1a80      	subs	r0, r0, r2
 80093ac:	b530      	push	{r4, r5, lr}
 80093ae:	d10e      	bne.n	80093ce <__mcmp+0x2a>
 80093b0:	3314      	adds	r3, #20
 80093b2:	3114      	adds	r1, #20
 80093b4:	eb03 0482 	add.w	r4, r3, r2, lsl #2
 80093b8:	eb01 0182 	add.w	r1, r1, r2, lsl #2
 80093bc:	f854 5d04 	ldr.w	r5, [r4, #-4]!
 80093c0:	f851 2d04 	ldr.w	r2, [r1, #-4]!
 80093c4:	4295      	cmp	r5, r2
 80093c6:	d003      	beq.n	80093d0 <__mcmp+0x2c>
 80093c8:	d205      	bcs.n	80093d6 <__mcmp+0x32>
 80093ca:	f04f 30ff 	mov.w	r0, #4294967295
 80093ce:	bd30      	pop	{r4, r5, pc}
 80093d0:	42a3      	cmp	r3, r4
 80093d2:	d3f3      	bcc.n	80093bc <__mcmp+0x18>
 80093d4:	e7fb      	b.n	80093ce <__mcmp+0x2a>
 80093d6:	2001      	movs	r0, #1
 80093d8:	e7f9      	b.n	80093ce <__mcmp+0x2a>
	...

080093dc <__mdiff>:
 80093dc:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
 80093e0:	4689      	mov	r9, r1
 80093e2:	4606      	mov	r6, r0
 80093e4:	4611      	mov	r1, r2
 80093e6:	4648      	mov	r0, r9
 80093e8:	4614      	mov	r4, r2
 80093ea:	f7ff ffdb 	bl	80093a4 <__mcmp>
 80093ee:	1e05      	subs	r5, r0, #0
 80093f0:	d112      	bne.n	8009418 <__mdiff+0x3c>
 80093f2:	4629      	mov	r1, r5
 80093f4:	4630      	mov	r0, r6
 80093f6:	f7ff fd63 	bl	8008ec0 <_Balloc>
 80093fa:	4602      	mov	r2, r0
 80093fc:	b928      	cbnz	r0, 800940a <__mdiff+0x2e>
 80093fe:	4b3f      	ldr	r3, [pc, #252]	@ (80094fc <__mdiff+0x120>)
 8009400:	f240 2137 	movw	r1, #567	@ 0x237
 8009404:	483e      	ldr	r0, [pc, #248]	@ (8009500 <__mdiff+0x124>)
 8009406:	f000 fce7 	bl	8009dd8 <__assert_func>
 800940a:	2301      	movs	r3, #1
 800940c:	e9c0 3504 	strd	r3, r5, [r0, #16]
 8009410:	4610      	mov	r0, r2
 8009412:	b003      	add	sp, #12
 8009414:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 8009418:	bfbc      	itt	lt
 800941a:	464b      	movlt	r3, r9
 800941c:	46a1      	movlt	r9, r4
 800941e:	4630      	mov	r0, r6
 8009420:	f8d9 1004 	ldr.w	r1, [r9, #4]
 8009424:	bfba      	itte	lt
 8009426:	461c      	movlt	r4, r3
 8009428:	2501      	movlt	r5, #1
 800942a:	2500      	movge	r5, #0
 800942c:	f7ff fd48 	bl	8008ec0 <_Balloc>
 8009430:	4602      	mov	r2, r0
 8009432:	b918      	cbnz	r0, 800943c <__mdiff+0x60>
 8009434:	4b31      	ldr	r3, [pc, #196]	@ (80094fc <__mdiff+0x120>)
 8009436:	f240 2145 	movw	r1, #581	@ 0x245
 800943a:	e7e3      	b.n	8009404 <__mdiff+0x28>
 800943c:	f8d9 7010 	ldr.w	r7, [r9, #16]
 8009440:	6926      	ldr	r6, [r4, #16]
 8009442:	60c5      	str	r5, [r0, #12]
 8009444:	f109 0310 	add.w	r3, r9, #16
 8009448:	f109 0514 	add.w	r5, r9, #20
 800944c:	f104 0e14 	add.w	lr, r4, #20
 8009450:	f100 0b14 	add.w	fp, r0, #20
 8009454:	eb05 0887 	add.w	r8, r5, r7, lsl #2
 8009458:	eb0e 0686 	add.w	r6, lr, r6, lsl #2
 800945c:	9301      	str	r3, [sp, #4]
 800945e:	46d9      	mov	r9, fp
 8009460:	f04f 0c00 	mov.w	ip, #0
 8009464:	9b01      	ldr	r3, [sp, #4]
 8009466:	f85e 0b04 	ldr.w	r0, [lr], #4
 800946a:	f853 af04 	ldr.w	sl, [r3, #4]!
 800946e:	9301      	str	r3, [sp, #4]
 8009470:	fa1f f38a 	uxth.w	r3, sl
 8009474:	4619      	mov	r1, r3
 8009476:	b283      	uxth	r3, r0
 8009478:	1acb      	subs	r3, r1, r3
 800947a:	0c00      	lsrs	r0, r0, #16
 800947c:	4463      	add	r3, ip
 800947e:	ebc0 401a 	rsb	r0, r0, sl, lsr #16
 8009482:	eb00 4023 	add.w	r0, r0, r3, asr #16
 8009486:	b29b      	uxth	r3, r3
 8009488:	ea43 4300 	orr.w	r3, r3, r0, lsl #16
 800948c:	4576      	cmp	r6, lr
 800948e:	f849 3b04 	str.w	r3, [r9], #4
 8009492:	ea4f 4c20 	mov.w	ip, r0, asr #16
 8009496:	d8e5      	bhi.n	8009464 <__mdiff+0x88>
 8009498:	1b33      	subs	r3, r6, r4
 800949a:	3b15      	subs	r3, #21
 800949c:	f023 0303 	bic.w	r3, r3, #3
 80094a0:	3415      	adds	r4, #21
 80094a2:	3304      	adds	r3, #4
 80094a4:	42a6      	cmp	r6, r4
 80094a6:	bf38      	it	cc
 80094a8:	2304      	movcc	r3, #4
 80094aa:	441d      	add	r5, r3
 80094ac:	445b      	add	r3, fp
 80094ae:	461e      	mov	r6, r3
 80094b0:	462c      	mov	r4, r5
 80094b2:	4544      	cmp	r4, r8
 80094b4:	d30e      	bcc.n	80094d4 <__mdiff+0xf8>
 80094b6:	f108 0103 	add.w	r1, r8, #3
 80094ba:	1b49      	subs	r1, r1, r5
 80094bc:	f021 0103 	bic.w	r1, r1, #3
 80094c0:	3d03      	subs	r5, #3
 80094c2:	45a8      	cmp	r8, r5
 80094c4:	bf38      	it	cc
 80094c6:	2100      	movcc	r1, #0
 80094c8:	440b      	add	r3, r1
 80094ca:	f853 1d04 	ldr.w	r1, [r3, #-4]!
 80094ce:	b191      	cbz	r1, 80094f6 <__mdiff+0x11a>
 80094d0:	6117      	str	r7, [r2, #16]
 80094d2:	e79d      	b.n	8009410 <__mdiff+0x34>
 80094d4:	f854 1b04 	ldr.w	r1, [r4], #4
 80094d8:	46e6      	mov	lr, ip
 80094da:	0c08      	lsrs	r0, r1, #16
 80094dc:	fa1c fc81 	uxtah	ip, ip, r1
 80094e0:	4471      	add	r1, lr
 80094e2:	eb00 402c 	add.w	r0, r0, ip, asr #16
 80094e6:	b289      	uxth	r1, r1
 80094e8:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
 80094ec:	f846 1b04 	str.w	r1, [r6], #4
 80094f0:	ea4f 4c20 	mov.w	ip, r0, asr #16
 80094f4:	e7dd      	b.n	80094b2 <__mdiff+0xd6>
 80094f6:	3f01      	subs	r7, #1
 80094f8:	e7e7      	b.n	80094ca <__mdiff+0xee>
 80094fa:	bf00      	nop
 80094fc:	0800b9ec 	.word	0x0800b9ec
 8009500:	0800b9fd 	.word	0x0800b9fd

08009504 <__d2b>:
 8009504:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
 8009508:	460f      	mov	r7, r1
 800950a:	2101      	movs	r1, #1
 800950c:	ec59 8b10 	vmov	r8, r9, d0
 8009510:	4616      	mov	r6, r2
 8009512:	f7ff fcd5 	bl	8008ec0 <_Balloc>
 8009516:	4604      	mov	r4, r0
 8009518:	b930      	cbnz	r0, 8009528 <__d2b+0x24>
 800951a:	4602      	mov	r2, r0
 800951c:	4b23      	ldr	r3, [pc, #140]	@ (80095ac <__d2b+0xa8>)
 800951e:	4824      	ldr	r0, [pc, #144]	@ (80095b0 <__d2b+0xac>)
 8009520:	f240 310f 	movw	r1, #783	@ 0x30f
 8009524:	f000 fc58 	bl	8009dd8 <__assert_func>
 8009528:	f3c9 550a 	ubfx	r5, r9, #20, #11
 800952c:	f3c9 0313 	ubfx	r3, r9, #0, #20
 8009530:	b10d      	cbz	r5, 8009536 <__d2b+0x32>
 8009532:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
 8009536:	9301      	str	r3, [sp, #4]
 8009538:	f1b8 0300 	subs.w	r3, r8, #0
 800953c:	d023      	beq.n	8009586 <__d2b+0x82>
 800953e:	4668      	mov	r0, sp
 8009540:	9300      	str	r3, [sp, #0]
 8009542:	f7ff fd84 	bl	800904e <__lo0bits>
 8009546:	e9dd 1200 	ldrd	r1, r2, [sp]
 800954a:	b1d0      	cbz	r0, 8009582 <__d2b+0x7e>
 800954c:	f1c0 0320 	rsb	r3, r0, #32
 8009550:	fa02 f303 	lsl.w	r3, r2, r3
 8009554:	430b      	orrs	r3, r1
 8009556:	40c2      	lsrs	r2, r0
 8009558:	6163      	str	r3, [r4, #20]
 800955a:	9201      	str	r2, [sp, #4]
 800955c:	9b01      	ldr	r3, [sp, #4]
 800955e:	61a3      	str	r3, [r4, #24]
 8009560:	2b00      	cmp	r3, #0
 8009562:	bf0c      	ite	eq
 8009564:	2201      	moveq	r2, #1
 8009566:	2202      	movne	r2, #2
 8009568:	6122      	str	r2, [r4, #16]
 800956a:	b1a5      	cbz	r5, 8009596 <__d2b+0x92>
 800956c:	f2a5 4533 	subw	r5, r5, #1075	@ 0x433
 8009570:	4405      	add	r5, r0
 8009572:	603d      	str	r5, [r7, #0]
 8009574:	f1c0 0035 	rsb	r0, r0, #53	@ 0x35
 8009578:	6030      	str	r0, [r6, #0]
 800957a:	4620      	mov	r0, r4
 800957c:	b003      	add	sp, #12
 800957e:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
 8009582:	6161      	str	r1, [r4, #20]
 8009584:	e7ea      	b.n	800955c <__d2b+0x58>
 8009586:	a801      	add	r0, sp, #4
 8009588:	f7ff fd61 	bl	800904e <__lo0bits>
 800958c:	9b01      	ldr	r3, [sp, #4]
 800958e:	6163      	str	r3, [r4, #20]
 8009590:	3020      	adds	r0, #32
 8009592:	2201      	movs	r2, #1
 8009594:	e7e8      	b.n	8009568 <__d2b+0x64>
 8009596:	eb04 0382 	add.w	r3, r4, r2, lsl #2
 800959a:	f2a0 4032 	subw	r0, r0, #1074	@ 0x432
 800959e:	6038      	str	r0, [r7, #0]
 80095a0:	6918      	ldr	r0, [r3, #16]
 80095a2:	f7ff fd35 	bl	8009010 <__hi0bits>
 80095a6:	ebc0 1042 	rsb	r0, r0, r2, lsl #5
 80095aa:	e7e5      	b.n	8009578 <__d2b+0x74>
 80095ac:	0800b9ec 	.word	0x0800b9ec
 80095b0:	0800b9fd 	.word	0x0800b9fd

080095b4 <__ssputs_r>:
 80095b4:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 80095b8:	688e      	ldr	r6, [r1, #8]
 80095ba:	461f      	mov	r7, r3
 80095bc:	42be      	cmp	r6, r7
 80095be:	680b      	ldr	r3, [r1, #0]
 80095c0:	4682      	mov	sl, r0
 80095c2:	460c      	mov	r4, r1
 80095c4:	4690      	mov	r8, r2
 80095c6:	d82d      	bhi.n	8009624 <__ssputs_r+0x70>
 80095c8:	f9b1 200c 	ldrsh.w	r2, [r1, #12]
 80095cc:	f412 6f90 	tst.w	r2, #1152	@ 0x480
 80095d0:	d026      	beq.n	8009620 <__ssputs_r+0x6c>
 80095d2:	6965      	ldr	r5, [r4, #20]
 80095d4:	6909      	ldr	r1, [r1, #16]
 80095d6:	eb05 0545 	add.w	r5, r5, r5, lsl #1
 80095da:	eba3 0901 	sub.w	r9, r3, r1
 80095de:	eb05 75d5 	add.w	r5, r5, r5, lsr #31
 80095e2:	1c7b      	adds	r3, r7, #1
 80095e4:	444b      	add	r3, r9
 80095e6:	106d      	asrs	r5, r5, #1
 80095e8:	429d      	cmp	r5, r3
 80095ea:	bf38      	it	cc
 80095ec:	461d      	movcc	r5, r3
 80095ee:	0553      	lsls	r3, r2, #21
 80095f0:	d527      	bpl.n	8009642 <__ssputs_r+0x8e>
 80095f2:	4629      	mov	r1, r5
 80095f4:	f7ff fbd8 	bl	8008da8 <_malloc_r>
 80095f8:	4606      	mov	r6, r0
 80095fa:	b360      	cbz	r0, 8009656 <__ssputs_r+0xa2>
 80095fc:	6921      	ldr	r1, [r4, #16]
 80095fe:	464a      	mov	r2, r9
 8009600:	f000 fbdc 	bl	8009dbc <memcpy>
 8009604:	89a3      	ldrh	r3, [r4, #12]
 8009606:	f423 6390 	bic.w	r3, r3, #1152	@ 0x480
 800960a:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
 800960e:	81a3      	strh	r3, [r4, #12]
 8009610:	6126      	str	r6, [r4, #16]
 8009612:	6165      	str	r5, [r4, #20]
 8009614:	444e      	add	r6, r9
 8009616:	eba5 0509 	sub.w	r5, r5, r9
 800961a:	6026      	str	r6, [r4, #0]
 800961c:	60a5      	str	r5, [r4, #8]
 800961e:	463e      	mov	r6, r7
 8009620:	42be      	cmp	r6, r7
 8009622:	d900      	bls.n	8009626 <__ssputs_r+0x72>
 8009624:	463e      	mov	r6, r7
 8009626:	6820      	ldr	r0, [r4, #0]
 8009628:	4632      	mov	r2, r6
 800962a:	4641      	mov	r1, r8
 800962c:	f000 fb9c 	bl	8009d68 <memmove>
 8009630:	68a3      	ldr	r3, [r4, #8]
 8009632:	1b9b      	subs	r3, r3, r6
 8009634:	60a3      	str	r3, [r4, #8]
 8009636:	6823      	ldr	r3, [r4, #0]
 8009638:	4433      	add	r3, r6
 800963a:	6023      	str	r3, [r4, #0]
 800963c:	2000      	movs	r0, #0
 800963e:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8009642:	462a      	mov	r2, r5
 8009644:	f000 fc0c 	bl	8009e60 <_realloc_r>
 8009648:	4606      	mov	r6, r0
 800964a:	2800      	cmp	r0, #0
 800964c:	d1e0      	bne.n	8009610 <__ssputs_r+0x5c>
 800964e:	6921      	ldr	r1, [r4, #16]
 8009650:	4650      	mov	r0, sl
 8009652:	f7ff fb35 	bl	8008cc0 <_free_r>
 8009656:	230c      	movs	r3, #12
 8009658:	f8ca 3000 	str.w	r3, [sl]
 800965c:	89a3      	ldrh	r3, [r4, #12]
 800965e:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 8009662:	81a3      	strh	r3, [r4, #12]
 8009664:	f04f 30ff 	mov.w	r0, #4294967295
 8009668:	e7e9      	b.n	800963e <__ssputs_r+0x8a>
	...

0800966c <_svfiprintf_r>:
 800966c:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8009670:	4698      	mov	r8, r3
 8009672:	898b      	ldrh	r3, [r1, #12]
 8009674:	061b      	lsls	r3, r3, #24
 8009676:	b09d      	sub	sp, #116	@ 0x74
 8009678:	4607      	mov	r7, r0
 800967a:	460d      	mov	r5, r1
 800967c:	4614      	mov	r4, r2
 800967e:	d510      	bpl.n	80096a2 <_svfiprintf_r+0x36>
 8009680:	690b      	ldr	r3, [r1, #16]
 8009682:	b973      	cbnz	r3, 80096a2 <_svfiprintf_r+0x36>
 8009684:	2140      	movs	r1, #64	@ 0x40
 8009686:	f7ff fb8f 	bl	8008da8 <_malloc_r>
 800968a:	6028      	str	r0, [r5, #0]
 800968c:	6128      	str	r0, [r5, #16]
 800968e:	b930      	cbnz	r0, 800969e <_svfiprintf_r+0x32>
 8009690:	230c      	movs	r3, #12
 8009692:	603b      	str	r3, [r7, #0]
 8009694:	f04f 30ff 	mov.w	r0, #4294967295
 8009698:	b01d      	add	sp, #116	@ 0x74
 800969a:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 800969e:	2340      	movs	r3, #64	@ 0x40
 80096a0:	616b      	str	r3, [r5, #20]
 80096a2:	2300      	movs	r3, #0
 80096a4:	9309      	str	r3, [sp, #36]	@ 0x24
 80096a6:	2320      	movs	r3, #32
 80096a8:	f88d 3029 	strb.w	r3, [sp, #41]	@ 0x29
 80096ac:	f8cd 800c 	str.w	r8, [sp, #12]
 80096b0:	2330      	movs	r3, #48	@ 0x30
 80096b2:	f8df 819c 	ldr.w	r8, [pc, #412]	@ 8009850 <_svfiprintf_r+0x1e4>
 80096b6:	f88d 302a 	strb.w	r3, [sp, #42]	@ 0x2a
 80096ba:	f04f 0901 	mov.w	r9, #1
 80096be:	4623      	mov	r3, r4
 80096c0:	469a      	mov	sl, r3
 80096c2:	f813 2b01 	ldrb.w	r2, [r3], #1
 80096c6:	b10a      	cbz	r2, 80096cc <_svfiprintf_r+0x60>
 80096c8:	2a25      	cmp	r2, #37	@ 0x25
 80096ca:	d1f9      	bne.n	80096c0 <_svfiprintf_r+0x54>
 80096cc:	ebba 0b04 	subs.w	fp, sl, r4
 80096d0:	d00b      	beq.n	80096ea <_svfiprintf_r+0x7e>
 80096d2:	465b      	mov	r3, fp
 80096d4:	4622      	mov	r2, r4
 80096d6:	4629      	mov	r1, r5
 80096d8:	4638      	mov	r0, r7
 80096da:	f7ff ff6b 	bl	80095b4 <__ssputs_r>
 80096de:	3001      	adds	r0, #1
 80096e0:	f000 80a7 	beq.w	8009832 <_svfiprintf_r+0x1c6>
 80096e4:	9a09      	ldr	r2, [sp, #36]	@ 0x24
 80096e6:	445a      	add	r2, fp
 80096e8:	9209      	str	r2, [sp, #36]	@ 0x24
 80096ea:	f89a 3000 	ldrb.w	r3, [sl]
 80096ee:	2b00      	cmp	r3, #0
 80096f0:	f000 809f 	beq.w	8009832 <_svfiprintf_r+0x1c6>
 80096f4:	2300      	movs	r3, #0
 80096f6:	f04f 32ff 	mov.w	r2, #4294967295
 80096fa:	e9cd 2305 	strd	r2, r3, [sp, #20]
 80096fe:	f10a 0a01 	add.w	sl, sl, #1
 8009702:	9304      	str	r3, [sp, #16]
 8009704:	9307      	str	r3, [sp, #28]
 8009706:	f88d 3053 	strb.w	r3, [sp, #83]	@ 0x53
 800970a:	931a      	str	r3, [sp, #104]	@ 0x68
 800970c:	4654      	mov	r4, sl
 800970e:	2205      	movs	r2, #5
 8009710:	f814 1b01 	ldrb.w	r1, [r4], #1
 8009714:	484e      	ldr	r0, [pc, #312]	@ (8009850 <_svfiprintf_r+0x1e4>)
 8009716:	f7f6 fd63 	bl	80001e0 <memchr>
 800971a:	9a04      	ldr	r2, [sp, #16]
 800971c:	b9d8      	cbnz	r0, 8009756 <_svfiprintf_r+0xea>
 800971e:	06d0      	lsls	r0, r2, #27
 8009720:	bf44      	itt	mi
 8009722:	2320      	movmi	r3, #32
 8009724:	f88d 3053 	strbmi.w	r3, [sp, #83]	@ 0x53
 8009728:	0711      	lsls	r1, r2, #28
 800972a:	bf44      	itt	mi
 800972c:	232b      	movmi	r3, #43	@ 0x2b
 800972e:	f88d 3053 	strbmi.w	r3, [sp, #83]	@ 0x53
 8009732:	f89a 3000 	ldrb.w	r3, [sl]
 8009736:	2b2a      	cmp	r3, #42	@ 0x2a
 8009738:	d015      	beq.n	8009766 <_svfiprintf_r+0xfa>
 800973a:	9a07      	ldr	r2, [sp, #28]
 800973c:	4654      	mov	r4, sl
 800973e:	2000      	movs	r0, #0
 8009740:	f04f 0c0a 	mov.w	ip, #10
 8009744:	4621      	mov	r1, r4
 8009746:	f811 3b01 	ldrb.w	r3, [r1], #1
 800974a:	3b30      	subs	r3, #48	@ 0x30
 800974c:	2b09      	cmp	r3, #9
 800974e:	d94b      	bls.n	80097e8 <_svfiprintf_r+0x17c>
 8009750:	b1b0      	cbz	r0, 8009780 <_svfiprintf_r+0x114>
 8009752:	9207      	str	r2, [sp, #28]
 8009754:	e014      	b.n	8009780 <_svfiprintf_r+0x114>
 8009756:	eba0 0308 	sub.w	r3, r0, r8
 800975a:	fa09 f303 	lsl.w	r3, r9, r3
 800975e:	4313      	orrs	r3, r2
 8009760:	9304      	str	r3, [sp, #16]
 8009762:	46a2      	mov	sl, r4
 8009764:	e7d2      	b.n	800970c <_svfiprintf_r+0xa0>
 8009766:	9b03      	ldr	r3, [sp, #12]
 8009768:	1d19      	adds	r1, r3, #4
 800976a:	681b      	ldr	r3, [r3, #0]
 800976c:	9103      	str	r1, [sp, #12]
 800976e:	2b00      	cmp	r3, #0
 8009770:	bfbb      	ittet	lt
 8009772:	425b      	neglt	r3, r3
 8009774:	f042 0202 	orrlt.w	r2, r2, #2
 8009778:	9307      	strge	r3, [sp, #28]
 800977a:	9307      	strlt	r3, [sp, #28]
 800977c:	bfb8      	it	lt
 800977e:	9204      	strlt	r2, [sp, #16]
 8009780:	7823      	ldrb	r3, [r4, #0]
 8009782:	2b2e      	cmp	r3, #46	@ 0x2e
 8009784:	d10a      	bne.n	800979c <_svfiprintf_r+0x130>
 8009786:	7863      	ldrb	r3, [r4, #1]
 8009788:	2b2a      	cmp	r3, #42	@ 0x2a
 800978a:	d132      	bne.n	80097f2 <_svfiprintf_r+0x186>
 800978c:	9b03      	ldr	r3, [sp, #12]
 800978e:	1d1a      	adds	r2, r3, #4
 8009790:	681b      	ldr	r3, [r3, #0]
 8009792:	9203      	str	r2, [sp, #12]
 8009794:	ea43 73e3 	orr.w	r3, r3, r3, asr #31
 8009798:	3402      	adds	r4, #2
 800979a:	9305      	str	r3, [sp, #20]
 800979c:	f8df a0c0 	ldr.w	sl, [pc, #192]	@ 8009860 <_svfiprintf_r+0x1f4>
 80097a0:	7821      	ldrb	r1, [r4, #0]
 80097a2:	2203      	movs	r2, #3
 80097a4:	4650      	mov	r0, sl
 80097a6:	f7f6 fd1b 	bl	80001e0 <memchr>
 80097aa:	b138      	cbz	r0, 80097bc <_svfiprintf_r+0x150>
 80097ac:	9b04      	ldr	r3, [sp, #16]
 80097ae:	eba0 000a 	sub.w	r0, r0, sl
 80097b2:	2240      	movs	r2, #64	@ 0x40
 80097b4:	4082      	lsls	r2, r0
 80097b6:	4313      	orrs	r3, r2
 80097b8:	3401      	adds	r4, #1
 80097ba:	9304      	str	r3, [sp, #16]
 80097bc:	f814 1b01 	ldrb.w	r1, [r4], #1
 80097c0:	4824      	ldr	r0, [pc, #144]	@ (8009854 <_svfiprintf_r+0x1e8>)
 80097c2:	f88d 1028 	strb.w	r1, [sp, #40]	@ 0x28
 80097c6:	2206      	movs	r2, #6
 80097c8:	f7f6 fd0a 	bl	80001e0 <memchr>
 80097cc:	2800      	cmp	r0, #0
 80097ce:	d036      	beq.n	800983e <_svfiprintf_r+0x1d2>
 80097d0:	4b21      	ldr	r3, [pc, #132]	@ (8009858 <_svfiprintf_r+0x1ec>)
 80097d2:	bb1b      	cbnz	r3, 800981c <_svfiprintf_r+0x1b0>
 80097d4:	9b03      	ldr	r3, [sp, #12]
 80097d6:	3307      	adds	r3, #7
 80097d8:	f023 0307 	bic.w	r3, r3, #7
 80097dc:	3308      	adds	r3, #8
 80097de:	9303      	str	r3, [sp, #12]
 80097e0:	9b09      	ldr	r3, [sp, #36]	@ 0x24
 80097e2:	4433      	add	r3, r6
 80097e4:	9309      	str	r3, [sp, #36]	@ 0x24
 80097e6:	e76a      	b.n	80096be <_svfiprintf_r+0x52>
 80097e8:	fb0c 3202 	mla	r2, ip, r2, r3
 80097ec:	460c      	mov	r4, r1
 80097ee:	2001      	movs	r0, #1
 80097f0:	e7a8      	b.n	8009744 <_svfiprintf_r+0xd8>
 80097f2:	2300      	movs	r3, #0
 80097f4:	3401      	adds	r4, #1
 80097f6:	9305      	str	r3, [sp, #20]
 80097f8:	4619      	mov	r1, r3
 80097fa:	f04f 0c0a 	mov.w	ip, #10
 80097fe:	4620      	mov	r0, r4
 8009800:	f810 2b01 	ldrb.w	r2, [r0], #1
 8009804:	3a30      	subs	r2, #48	@ 0x30
 8009806:	2a09      	cmp	r2, #9
 8009808:	d903      	bls.n	8009812 <_svfiprintf_r+0x1a6>
 800980a:	2b00      	cmp	r3, #0
 800980c:	d0c6      	beq.n	800979c <_svfiprintf_r+0x130>
 800980e:	9105      	str	r1, [sp, #20]
 8009810:	e7c4      	b.n	800979c <_svfiprintf_r+0x130>
 8009812:	fb0c 2101 	mla	r1, ip, r1, r2
 8009816:	4604      	mov	r4, r0
 8009818:	2301      	movs	r3, #1
 800981a:	e7f0      	b.n	80097fe <_svfiprintf_r+0x192>
 800981c:	ab03      	add	r3, sp, #12
 800981e:	9300      	str	r3, [sp, #0]
 8009820:	462a      	mov	r2, r5
 8009822:	4b0e      	ldr	r3, [pc, #56]	@ (800985c <_svfiprintf_r+0x1f0>)
 8009824:	a904      	add	r1, sp, #16
 8009826:	4638      	mov	r0, r7
 8009828:	f7fd fe6e 	bl	8007508 <_printf_float>
 800982c:	1c42      	adds	r2, r0, #1
 800982e:	4606      	mov	r6, r0
 8009830:	d1d6      	bne.n	80097e0 <_svfiprintf_r+0x174>
 8009832:	89ab      	ldrh	r3, [r5, #12]
 8009834:	065b      	lsls	r3, r3, #25
 8009836:	f53f af2d 	bmi.w	8009694 <_svfiprintf_r+0x28>
 800983a:	9809      	ldr	r0, [sp, #36]	@ 0x24
 800983c:	e72c      	b.n	8009698 <_svfiprintf_r+0x2c>
 800983e:	ab03      	add	r3, sp, #12
 8009840:	9300      	str	r3, [sp, #0]
 8009842:	462a      	mov	r2, r5
 8009844:	4b05      	ldr	r3, [pc, #20]	@ (800985c <_svfiprintf_r+0x1f0>)
 8009846:	a904      	add	r1, sp, #16
 8009848:	4638      	mov	r0, r7
 800984a:	f7fe f8f5 	bl	8007a38 <_printf_i>
 800984e:	e7ed      	b.n	800982c <_svfiprintf_r+0x1c0>
 8009850:	0800ba56 	.word	0x0800ba56
 8009854:	0800ba60 	.word	0x0800ba60
 8009858:	08007509 	.word	0x08007509
 800985c:	080095b5 	.word	0x080095b5
 8009860:	0800ba5c 	.word	0x0800ba5c

08009864 <__sfputc_r>:
 8009864:	6893      	ldr	r3, [r2, #8]
 8009866:	3b01      	subs	r3, #1
 8009868:	2b00      	cmp	r3, #0
 800986a:	b410      	push	{r4}
 800986c:	6093      	str	r3, [r2, #8]
 800986e:	da08      	bge.n	8009882 <__sfputc_r+0x1e>
 8009870:	6994      	ldr	r4, [r2, #24]
 8009872:	42a3      	cmp	r3, r4
 8009874:	db01      	blt.n	800987a <__sfputc_r+0x16>
 8009876:	290a      	cmp	r1, #10
 8009878:	d103      	bne.n	8009882 <__sfputc_r+0x1e>
 800987a:	f85d 4b04 	ldr.w	r4, [sp], #4
 800987e:	f000 b9df 	b.w	8009c40 <__swbuf_r>
 8009882:	6813      	ldr	r3, [r2, #0]
 8009884:	1c58      	adds	r0, r3, #1
 8009886:	6010      	str	r0, [r2, #0]
 8009888:	7019      	strb	r1, [r3, #0]
 800988a:	4608      	mov	r0, r1
 800988c:	f85d 4b04 	ldr.w	r4, [sp], #4
 8009890:	4770      	bx	lr

08009892 <__sfputs_r>:
 8009892:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8009894:	4606      	mov	r6, r0
 8009896:	460f      	mov	r7, r1
 8009898:	4614      	mov	r4, r2
 800989a:	18d5      	adds	r5, r2, r3
 800989c:	42ac      	cmp	r4, r5
 800989e:	d101      	bne.n	80098a4 <__sfputs_r+0x12>
 80098a0:	2000      	movs	r0, #0
 80098a2:	e007      	b.n	80098b4 <__sfputs_r+0x22>
 80098a4:	f814 1b01 	ldrb.w	r1, [r4], #1
 80098a8:	463a      	mov	r2, r7
 80098aa:	4630      	mov	r0, r6
 80098ac:	f7ff ffda 	bl	8009864 <__sfputc_r>
 80098b0:	1c43      	adds	r3, r0, #1
 80098b2:	d1f3      	bne.n	800989c <__sfputs_r+0xa>
 80098b4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	...

080098b8 <_vfiprintf_r>:
 80098b8:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 80098bc:	460d      	mov	r5, r1
 80098be:	b09d      	sub	sp, #116	@ 0x74
 80098c0:	4614      	mov	r4, r2
 80098c2:	4698      	mov	r8, r3
 80098c4:	4606      	mov	r6, r0
 80098c6:	b118      	cbz	r0, 80098d0 <_vfiprintf_r+0x18>
 80098c8:	6a03      	ldr	r3, [r0, #32]
 80098ca:	b90b      	cbnz	r3, 80098d0 <_vfiprintf_r+0x18>
 80098cc:	f7fe fa5e 	bl	8007d8c <__sinit>
 80098d0:	6e6b      	ldr	r3, [r5, #100]	@ 0x64
 80098d2:	07d9      	lsls	r1, r3, #31
 80098d4:	d405      	bmi.n	80098e2 <_vfiprintf_r+0x2a>
 80098d6:	89ab      	ldrh	r3, [r5, #12]
 80098d8:	059a      	lsls	r2, r3, #22
 80098da:	d402      	bmi.n	80098e2 <_vfiprintf_r+0x2a>
 80098dc:	6da8      	ldr	r0, [r5, #88]	@ 0x58
 80098de:	f7fe fb94 	bl	800800a <__retarget_lock_acquire_recursive>
 80098e2:	89ab      	ldrh	r3, [r5, #12]
 80098e4:	071b      	lsls	r3, r3, #28
 80098e6:	d501      	bpl.n	80098ec <_vfiprintf_r+0x34>
 80098e8:	692b      	ldr	r3, [r5, #16]
 80098ea:	b99b      	cbnz	r3, 8009914 <_vfiprintf_r+0x5c>
 80098ec:	4629      	mov	r1, r5
 80098ee:	4630      	mov	r0, r6
 80098f0:	f000 f9e4 	bl	8009cbc <__swsetup_r>
 80098f4:	b170      	cbz	r0, 8009914 <_vfiprintf_r+0x5c>
 80098f6:	6e6b      	ldr	r3, [r5, #100]	@ 0x64
 80098f8:	07dc      	lsls	r4, r3, #31
 80098fa:	d504      	bpl.n	8009906 <_vfiprintf_r+0x4e>
 80098fc:	f04f 30ff 	mov.w	r0, #4294967295
 8009900:	b01d      	add	sp, #116	@ 0x74
 8009902:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 8009906:	89ab      	ldrh	r3, [r5, #12]
 8009908:	0598      	lsls	r0, r3, #22
 800990a:	d4f7      	bmi.n	80098fc <_vfiprintf_r+0x44>
 800990c:	6da8      	ldr	r0, [r5, #88]	@ 0x58
 800990e:	f7fe fb7d 	bl	800800c <__retarget_lock_release_recursive>
 8009912:	e7f3      	b.n	80098fc <_vfiprintf_r+0x44>
 8009914:	2300      	movs	r3, #0
 8009916:	9309      	str	r3, [sp, #36]	@ 0x24
 8009918:	2320      	movs	r3, #32
 800991a:	f88d 3029 	strb.w	r3, [sp, #41]	@ 0x29
 800991e:	f8cd 800c 	str.w	r8, [sp, #12]
 8009922:	2330      	movs	r3, #48	@ 0x30
 8009924:	f8df 81ac 	ldr.w	r8, [pc, #428]	@ 8009ad4 <_vfiprintf_r+0x21c>
 8009928:	f88d 302a 	strb.w	r3, [sp, #42]	@ 0x2a
 800992c:	f04f 0901 	mov.w	r9, #1
 8009930:	4623      	mov	r3, r4
 8009932:	469a      	mov	sl, r3
 8009934:	f813 2b01 	ldrb.w	r2, [r3], #1
 8009938:	b10a      	cbz	r2, 800993e <_vfiprintf_r+0x86>
 800993a:	2a25      	cmp	r2, #37	@ 0x25
 800993c:	d1f9      	bne.n	8009932 <_vfiprintf_r+0x7a>
 800993e:	ebba 0b04 	subs.w	fp, sl, r4
 8009942:	d00b      	beq.n	800995c <_vfiprintf_r+0xa4>
 8009944:	465b      	mov	r3, fp
 8009946:	4622      	mov	r2, r4
 8009948:	4629      	mov	r1, r5
 800994a:	4630      	mov	r0, r6
 800994c:	f7ff ffa1 	bl	8009892 <__sfputs_r>
 8009950:	3001      	adds	r0, #1
 8009952:	f000 80a7 	beq.w	8009aa4 <_vfiprintf_r+0x1ec>
 8009956:	9a09      	ldr	r2, [sp, #36]	@ 0x24
 8009958:	445a      	add	r2, fp
 800995a:	9209      	str	r2, [sp, #36]	@ 0x24
 800995c:	f89a 3000 	ldrb.w	r3, [sl]
 8009960:	2b00      	cmp	r3, #0
 8009962:	f000 809f 	beq.w	8009aa4 <_vfiprintf_r+0x1ec>
 8009966:	2300      	movs	r3, #0
 8009968:	f04f 32ff 	mov.w	r2, #4294967295
 800996c:	e9cd 2305 	strd	r2, r3, [sp, #20]
 8009970:	f10a 0a01 	add.w	sl, sl, #1
 8009974:	9304      	str	r3, [sp, #16]
 8009976:	9307      	str	r3, [sp, #28]
 8009978:	f88d 3053 	strb.w	r3, [sp, #83]	@ 0x53
 800997c:	931a      	str	r3, [sp, #104]	@ 0x68
 800997e:	4654      	mov	r4, sl
 8009980:	2205      	movs	r2, #5
 8009982:	f814 1b01 	ldrb.w	r1, [r4], #1
 8009986:	4853      	ldr	r0, [pc, #332]	@ (8009ad4 <_vfiprintf_r+0x21c>)
 8009988:	f7f6 fc2a 	bl	80001e0 <memchr>
 800998c:	9a04      	ldr	r2, [sp, #16]
 800998e:	b9d8      	cbnz	r0, 80099c8 <_vfiprintf_r+0x110>
 8009990:	06d1      	lsls	r1, r2, #27
 8009992:	bf44      	itt	mi
 8009994:	2320      	movmi	r3, #32
 8009996:	f88d 3053 	strbmi.w	r3, [sp, #83]	@ 0x53
 800999a:	0713      	lsls	r3, r2, #28
 800999c:	bf44      	itt	mi
 800999e:	232b      	movmi	r3, #43	@ 0x2b
 80099a0:	f88d 3053 	strbmi.w	r3, [sp, #83]	@ 0x53
 80099a4:	f89a 3000 	ldrb.w	r3, [sl]
 80099a8:	2b2a      	cmp	r3, #42	@ 0x2a
 80099aa:	d015      	beq.n	80099d8 <_vfiprintf_r+0x120>
 80099ac:	9a07      	ldr	r2, [sp, #28]
 80099ae:	4654      	mov	r4, sl
 80099b0:	2000      	movs	r0, #0
 80099b2:	f04f 0c0a 	mov.w	ip, #10
 80099b6:	4621      	mov	r1, r4
 80099b8:	f811 3b01 	ldrb.w	r3, [r1], #1
 80099bc:	3b30      	subs	r3, #48	@ 0x30
 80099be:	2b09      	cmp	r3, #9
 80099c0:	d94b      	bls.n	8009a5a <_vfiprintf_r+0x1a2>
 80099c2:	b1b0      	cbz	r0, 80099f2 <_vfiprintf_r+0x13a>
 80099c4:	9207      	str	r2, [sp, #28]
 80099c6:	e014      	b.n	80099f2 <_vfiprintf_r+0x13a>
 80099c8:	eba0 0308 	sub.w	r3, r0, r8
 80099cc:	fa09 f303 	lsl.w	r3, r9, r3
 80099d0:	4313      	orrs	r3, r2
 80099d2:	9304      	str	r3, [sp, #16]
 80099d4:	46a2      	mov	sl, r4
 80099d6:	e7d2      	b.n	800997e <_vfiprintf_r+0xc6>
 80099d8:	9b03      	ldr	r3, [sp, #12]
 80099da:	1d19      	adds	r1, r3, #4
 80099dc:	681b      	ldr	r3, [r3, #0]
 80099de:	9103      	str	r1, [sp, #12]
 80099e0:	2b00      	cmp	r3, #0
 80099e2:	bfbb      	ittet	lt
 80099e4:	425b      	neglt	r3, r3
 80099e6:	f042 0202 	orrlt.w	r2, r2, #2
 80099ea:	9307      	strge	r3, [sp, #28]
 80099ec:	9307      	strlt	r3, [sp, #28]
 80099ee:	bfb8      	it	lt
 80099f0:	9204      	strlt	r2, [sp, #16]
 80099f2:	7823      	ldrb	r3, [r4, #0]
 80099f4:	2b2e      	cmp	r3, #46	@ 0x2e
 80099f6:	d10a      	bne.n	8009a0e <_vfiprintf_r+0x156>
 80099f8:	7863      	ldrb	r3, [r4, #1]
 80099fa:	2b2a      	cmp	r3, #42	@ 0x2a
 80099fc:	d132      	bne.n	8009a64 <_vfiprintf_r+0x1ac>
 80099fe:	9b03      	ldr	r3, [sp, #12]
 8009a00:	1d1a      	adds	r2, r3, #4
 8009a02:	681b      	ldr	r3, [r3, #0]
 8009a04:	9203      	str	r2, [sp, #12]
 8009a06:	ea43 73e3 	orr.w	r3, r3, r3, asr #31
 8009a0a:	3402      	adds	r4, #2
 8009a0c:	9305      	str	r3, [sp, #20]
 8009a0e:	f8df a0d4 	ldr.w	sl, [pc, #212]	@ 8009ae4 <_vfiprintf_r+0x22c>
 8009a12:	7821      	ldrb	r1, [r4, #0]
 8009a14:	2203      	movs	r2, #3
 8009a16:	4650      	mov	r0, sl
 8009a18:	f7f6 fbe2 	bl	80001e0 <memchr>
 8009a1c:	b138      	cbz	r0, 8009a2e <_vfiprintf_r+0x176>
 8009a1e:	9b04      	ldr	r3, [sp, #16]
 8009a20:	eba0 000a 	sub.w	r0, r0, sl
 8009a24:	2240      	movs	r2, #64	@ 0x40
 8009a26:	4082      	lsls	r2, r0
 8009a28:	4313      	orrs	r3, r2
 8009a2a:	3401      	adds	r4, #1
 8009a2c:	9304      	str	r3, [sp, #16]
 8009a2e:	f814 1b01 	ldrb.w	r1, [r4], #1
 8009a32:	4829      	ldr	r0, [pc, #164]	@ (8009ad8 <_vfiprintf_r+0x220>)
 8009a34:	f88d 1028 	strb.w	r1, [sp, #40]	@ 0x28
 8009a38:	2206      	movs	r2, #6
 8009a3a:	f7f6 fbd1 	bl	80001e0 <memchr>
 8009a3e:	2800      	cmp	r0, #0
 8009a40:	d03f      	beq.n	8009ac2 <_vfiprintf_r+0x20a>
 8009a42:	4b26      	ldr	r3, [pc, #152]	@ (8009adc <_vfiprintf_r+0x224>)
 8009a44:	bb1b      	cbnz	r3, 8009a8e <_vfiprintf_r+0x1d6>
 8009a46:	9b03      	ldr	r3, [sp, #12]
 8009a48:	3307      	adds	r3, #7
 8009a4a:	f023 0307 	bic.w	r3, r3, #7
 8009a4e:	3308      	adds	r3, #8
 8009a50:	9303      	str	r3, [sp, #12]
 8009a52:	9b09      	ldr	r3, [sp, #36]	@ 0x24
 8009a54:	443b      	add	r3, r7
 8009a56:	9309      	str	r3, [sp, #36]	@ 0x24
 8009a58:	e76a      	b.n	8009930 <_vfiprintf_r+0x78>
 8009a5a:	fb0c 3202 	mla	r2, ip, r2, r3
 8009a5e:	460c      	mov	r4, r1
 8009a60:	2001      	movs	r0, #1
 8009a62:	e7a8      	b.n	80099b6 <_vfiprintf_r+0xfe>
 8009a64:	2300      	movs	r3, #0
 8009a66:	3401      	adds	r4, #1
 8009a68:	9305      	str	r3, [sp, #20]
 8009a6a:	4619      	mov	r1, r3
 8009a6c:	f04f 0c0a 	mov.w	ip, #10
 8009a70:	4620      	mov	r0, r4
 8009a72:	f810 2b01 	ldrb.w	r2, [r0], #1
 8009a76:	3a30      	subs	r2, #48	@ 0x30
 8009a78:	2a09      	cmp	r2, #9
 8009a7a:	d903      	bls.n	8009a84 <_vfiprintf_r+0x1cc>
 8009a7c:	2b00      	cmp	r3, #0
 8009a7e:	d0c6      	beq.n	8009a0e <_vfiprintf_r+0x156>
 8009a80:	9105      	str	r1, [sp, #20]
 8009a82:	e7c4      	b.n	8009a0e <_vfiprintf_r+0x156>
 8009a84:	fb0c 2101 	mla	r1, ip, r1, r2
 8009a88:	4604      	mov	r4, r0
 8009a8a:	2301      	movs	r3, #1
 8009a8c:	e7f0      	b.n	8009a70 <_vfiprintf_r+0x1b8>
 8009a8e:	ab03      	add	r3, sp, #12
 8009a90:	9300      	str	r3, [sp, #0]
 8009a92:	462a      	mov	r2, r5
 8009a94:	4b12      	ldr	r3, [pc, #72]	@ (8009ae0 <_vfiprintf_r+0x228>)
 8009a96:	a904      	add	r1, sp, #16
 8009a98:	4630      	mov	r0, r6
 8009a9a:	f7fd fd35 	bl	8007508 <_printf_float>
 8009a9e:	4607      	mov	r7, r0
 8009aa0:	1c78      	adds	r0, r7, #1
 8009aa2:	d1d6      	bne.n	8009a52 <_vfiprintf_r+0x19a>
 8009aa4:	6e6b      	ldr	r3, [r5, #100]	@ 0x64
 8009aa6:	07d9      	lsls	r1, r3, #31
 8009aa8:	d405      	bmi.n	8009ab6 <_vfiprintf_r+0x1fe>
 8009aaa:	89ab      	ldrh	r3, [r5, #12]
 8009aac:	059a      	lsls	r2, r3, #22
 8009aae:	d402      	bmi.n	8009ab6 <_vfiprintf_r+0x1fe>
 8009ab0:	6da8      	ldr	r0, [r5, #88]	@ 0x58
 8009ab2:	f7fe faab 	bl	800800c <__retarget_lock_release_recursive>
 8009ab6:	89ab      	ldrh	r3, [r5, #12]
 8009ab8:	065b      	lsls	r3, r3, #25
 8009aba:	f53f af1f 	bmi.w	80098fc <_vfiprintf_r+0x44>
 8009abe:	9809      	ldr	r0, [sp, #36]	@ 0x24
 8009ac0:	e71e      	b.n	8009900 <_vfiprintf_r+0x48>
 8009ac2:	ab03      	add	r3, sp, #12
 8009ac4:	9300      	str	r3, [sp, #0]
 8009ac6:	462a      	mov	r2, r5
 8009ac8:	4b05      	ldr	r3, [pc, #20]	@ (8009ae0 <_vfiprintf_r+0x228>)
 8009aca:	a904      	add	r1, sp, #16
 8009acc:	4630      	mov	r0, r6
 8009ace:	f7fd ffb3 	bl	8007a38 <_printf_i>
 8009ad2:	e7e4      	b.n	8009a9e <_vfiprintf_r+0x1e6>
 8009ad4:	0800ba56 	.word	0x0800ba56
 8009ad8:	0800ba60 	.word	0x0800ba60
 8009adc:	08007509 	.word	0x08007509
 8009ae0:	08009893 	.word	0x08009893
 8009ae4:	0800ba5c 	.word	0x0800ba5c

08009ae8 <__sflush_r>:
 8009ae8:	f9b1 200c 	ldrsh.w	r2, [r1, #12]
 8009aec:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8009af0:	0716      	lsls	r6, r2, #28
 8009af2:	4605      	mov	r5, r0
 8009af4:	460c      	mov	r4, r1
 8009af6:	d454      	bmi.n	8009ba2 <__sflush_r+0xba>
 8009af8:	684b      	ldr	r3, [r1, #4]
 8009afa:	2b00      	cmp	r3, #0
 8009afc:	dc02      	bgt.n	8009b04 <__sflush_r+0x1c>
 8009afe:	6c0b      	ldr	r3, [r1, #64]	@ 0x40
 8009b00:	2b00      	cmp	r3, #0
 8009b02:	dd48      	ble.n	8009b96 <__sflush_r+0xae>
 8009b04:	6ae6      	ldr	r6, [r4, #44]	@ 0x2c
 8009b06:	2e00      	cmp	r6, #0
 8009b08:	d045      	beq.n	8009b96 <__sflush_r+0xae>
 8009b0a:	2300      	movs	r3, #0
 8009b0c:	f412 5280 	ands.w	r2, r2, #4096	@ 0x1000
 8009b10:	682f      	ldr	r7, [r5, #0]
 8009b12:	6a21      	ldr	r1, [r4, #32]
 8009b14:	602b      	str	r3, [r5, #0]
 8009b16:	d030      	beq.n	8009b7a <__sflush_r+0x92>
 8009b18:	6d62      	ldr	r2, [r4, #84]	@ 0x54
 8009b1a:	89a3      	ldrh	r3, [r4, #12]
 8009b1c:	0759      	lsls	r1, r3, #29
 8009b1e:	d505      	bpl.n	8009b2c <__sflush_r+0x44>
 8009b20:	6863      	ldr	r3, [r4, #4]
 8009b22:	1ad2      	subs	r2, r2, r3
 8009b24:	6b63      	ldr	r3, [r4, #52]	@ 0x34
 8009b26:	b10b      	cbz	r3, 8009b2c <__sflush_r+0x44>
 8009b28:	6c23      	ldr	r3, [r4, #64]	@ 0x40
 8009b2a:	1ad2      	subs	r2, r2, r3
 8009b2c:	2300      	movs	r3, #0
 8009b2e:	6ae6      	ldr	r6, [r4, #44]	@ 0x2c
 8009b30:	6a21      	ldr	r1, [r4, #32]
 8009b32:	4628      	mov	r0, r5
 8009b34:	47b0      	blx	r6
 8009b36:	1c43      	adds	r3, r0, #1
 8009b38:	89a3      	ldrh	r3, [r4, #12]
 8009b3a:	d106      	bne.n	8009b4a <__sflush_r+0x62>
 8009b3c:	6829      	ldr	r1, [r5, #0]
 8009b3e:	291d      	cmp	r1, #29
 8009b40:	d82b      	bhi.n	8009b9a <__sflush_r+0xb2>
 8009b42:	4a2a      	ldr	r2, [pc, #168]	@ (8009bec <__sflush_r+0x104>)
 8009b44:	40ca      	lsrs	r2, r1
 8009b46:	07d6      	lsls	r6, r2, #31
 8009b48:	d527      	bpl.n	8009b9a <__sflush_r+0xb2>
 8009b4a:	2200      	movs	r2, #0
 8009b4c:	6062      	str	r2, [r4, #4]
 8009b4e:	04d9      	lsls	r1, r3, #19
 8009b50:	6922      	ldr	r2, [r4, #16]
 8009b52:	6022      	str	r2, [r4, #0]
 8009b54:	d504      	bpl.n	8009b60 <__sflush_r+0x78>
 8009b56:	1c42      	adds	r2, r0, #1
 8009b58:	d101      	bne.n	8009b5e <__sflush_r+0x76>
 8009b5a:	682b      	ldr	r3, [r5, #0]
 8009b5c:	b903      	cbnz	r3, 8009b60 <__sflush_r+0x78>
 8009b5e:	6560      	str	r0, [r4, #84]	@ 0x54
 8009b60:	6b61      	ldr	r1, [r4, #52]	@ 0x34
 8009b62:	602f      	str	r7, [r5, #0]
 8009b64:	b1b9      	cbz	r1, 8009b96 <__sflush_r+0xae>
 8009b66:	f104 0344 	add.w	r3, r4, #68	@ 0x44
 8009b6a:	4299      	cmp	r1, r3
 8009b6c:	d002      	beq.n	8009b74 <__sflush_r+0x8c>
 8009b6e:	4628      	mov	r0, r5
 8009b70:	f7ff f8a6 	bl	8008cc0 <_free_r>
 8009b74:	2300      	movs	r3, #0
 8009b76:	6363      	str	r3, [r4, #52]	@ 0x34
 8009b78:	e00d      	b.n	8009b96 <__sflush_r+0xae>
 8009b7a:	2301      	movs	r3, #1
 8009b7c:	4628      	mov	r0, r5
 8009b7e:	47b0      	blx	r6
 8009b80:	4602      	mov	r2, r0
 8009b82:	1c50      	adds	r0, r2, #1
 8009b84:	d1c9      	bne.n	8009b1a <__sflush_r+0x32>
 8009b86:	682b      	ldr	r3, [r5, #0]
 8009b88:	2b00      	cmp	r3, #0
 8009b8a:	d0c6      	beq.n	8009b1a <__sflush_r+0x32>
 8009b8c:	2b1d      	cmp	r3, #29
 8009b8e:	d001      	beq.n	8009b94 <__sflush_r+0xac>
 8009b90:	2b16      	cmp	r3, #22
 8009b92:	d11e      	bne.n	8009bd2 <__sflush_r+0xea>
 8009b94:	602f      	str	r7, [r5, #0]
 8009b96:	2000      	movs	r0, #0
 8009b98:	e022      	b.n	8009be0 <__sflush_r+0xf8>
 8009b9a:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 8009b9e:	b21b      	sxth	r3, r3
 8009ba0:	e01b      	b.n	8009bda <__sflush_r+0xf2>
 8009ba2:	690f      	ldr	r7, [r1, #16]
 8009ba4:	2f00      	cmp	r7, #0
 8009ba6:	d0f6      	beq.n	8009b96 <__sflush_r+0xae>
 8009ba8:	0793      	lsls	r3, r2, #30
 8009baa:	680e      	ldr	r6, [r1, #0]
 8009bac:	bf08      	it	eq
 8009bae:	694b      	ldreq	r3, [r1, #20]
 8009bb0:	600f      	str	r7, [r1, #0]
 8009bb2:	bf18      	it	ne
 8009bb4:	2300      	movne	r3, #0
 8009bb6:	eba6 0807 	sub.w	r8, r6, r7
 8009bba:	608b      	str	r3, [r1, #8]
 8009bbc:	f1b8 0f00 	cmp.w	r8, #0
 8009bc0:	dde9      	ble.n	8009b96 <__sflush_r+0xae>
 8009bc2:	6a21      	ldr	r1, [r4, #32]
 8009bc4:	6aa6      	ldr	r6, [r4, #40]	@ 0x28
 8009bc6:	4643      	mov	r3, r8
 8009bc8:	463a      	mov	r2, r7
 8009bca:	4628      	mov	r0, r5
 8009bcc:	47b0      	blx	r6
 8009bce:	2800      	cmp	r0, #0
 8009bd0:	dc08      	bgt.n	8009be4 <__sflush_r+0xfc>
 8009bd2:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8009bd6:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 8009bda:	81a3      	strh	r3, [r4, #12]
 8009bdc:	f04f 30ff 	mov.w	r0, #4294967295
 8009be0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8009be4:	4407      	add	r7, r0
 8009be6:	eba8 0800 	sub.w	r8, r8, r0
 8009bea:	e7e7      	b.n	8009bbc <__sflush_r+0xd4>
 8009bec:	20400001 	.word	0x20400001

08009bf0 <_fflush_r>:
 8009bf0:	b538      	push	{r3, r4, r5, lr}
 8009bf2:	690b      	ldr	r3, [r1, #16]
 8009bf4:	4605      	mov	r5, r0
 8009bf6:	460c      	mov	r4, r1
 8009bf8:	b913      	cbnz	r3, 8009c00 <_fflush_r+0x10>
 8009bfa:	2500      	movs	r5, #0
 8009bfc:	4628      	mov	r0, r5
 8009bfe:	bd38      	pop	{r3, r4, r5, pc}
 8009c00:	b118      	cbz	r0, 8009c0a <_fflush_r+0x1a>
 8009c02:	6a03      	ldr	r3, [r0, #32]
 8009c04:	b90b      	cbnz	r3, 8009c0a <_fflush_r+0x1a>
 8009c06:	f7fe f8c1 	bl	8007d8c <__sinit>
 8009c0a:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8009c0e:	2b00      	cmp	r3, #0
 8009c10:	d0f3      	beq.n	8009bfa <_fflush_r+0xa>
 8009c12:	6e62      	ldr	r2, [r4, #100]	@ 0x64
 8009c14:	07d0      	lsls	r0, r2, #31
 8009c16:	d404      	bmi.n	8009c22 <_fflush_r+0x32>
 8009c18:	0599      	lsls	r1, r3, #22
 8009c1a:	d402      	bmi.n	8009c22 <_fflush_r+0x32>
 8009c1c:	6da0      	ldr	r0, [r4, #88]	@ 0x58
 8009c1e:	f7fe f9f4 	bl	800800a <__retarget_lock_acquire_recursive>
 8009c22:	4628      	mov	r0, r5
 8009c24:	4621      	mov	r1, r4
 8009c26:	f7ff ff5f 	bl	8009ae8 <__sflush_r>
 8009c2a:	6e63      	ldr	r3, [r4, #100]	@ 0x64
 8009c2c:	07da      	lsls	r2, r3, #31
 8009c2e:	4605      	mov	r5, r0
 8009c30:	d4e4      	bmi.n	8009bfc <_fflush_r+0xc>
 8009c32:	89a3      	ldrh	r3, [r4, #12]
 8009c34:	059b      	lsls	r3, r3, #22
 8009c36:	d4e1      	bmi.n	8009bfc <_fflush_r+0xc>
 8009c38:	6da0      	ldr	r0, [r4, #88]	@ 0x58
 8009c3a:	f7fe f9e7 	bl	800800c <__retarget_lock_release_recursive>
 8009c3e:	e7dd      	b.n	8009bfc <_fflush_r+0xc>

08009c40 <__swbuf_r>:
 8009c40:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8009c42:	460e      	mov	r6, r1
 8009c44:	4614      	mov	r4, r2
 8009c46:	4605      	mov	r5, r0
 8009c48:	b118      	cbz	r0, 8009c52 <__swbuf_r+0x12>
 8009c4a:	6a03      	ldr	r3, [r0, #32]
 8009c4c:	b90b      	cbnz	r3, 8009c52 <__swbuf_r+0x12>
 8009c4e:	f7fe f89d 	bl	8007d8c <__sinit>
 8009c52:	69a3      	ldr	r3, [r4, #24]
 8009c54:	60a3      	str	r3, [r4, #8]
 8009c56:	89a3      	ldrh	r3, [r4, #12]
 8009c58:	071a      	lsls	r2, r3, #28
 8009c5a:	d501      	bpl.n	8009c60 <__swbuf_r+0x20>
 8009c5c:	6923      	ldr	r3, [r4, #16]
 8009c5e:	b943      	cbnz	r3, 8009c72 <__swbuf_r+0x32>
 8009c60:	4621      	mov	r1, r4
 8009c62:	4628      	mov	r0, r5
 8009c64:	f000 f82a 	bl	8009cbc <__swsetup_r>
 8009c68:	b118      	cbz	r0, 8009c72 <__swbuf_r+0x32>
 8009c6a:	f04f 37ff 	mov.w	r7, #4294967295
 8009c6e:	4638      	mov	r0, r7
 8009c70:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 8009c72:	6823      	ldr	r3, [r4, #0]
 8009c74:	6922      	ldr	r2, [r4, #16]
 8009c76:	1a98      	subs	r0, r3, r2
 8009c78:	6963      	ldr	r3, [r4, #20]
 8009c7a:	b2f6      	uxtb	r6, r6
 8009c7c:	4283      	cmp	r3, r0
 8009c7e:	4637      	mov	r7, r6
 8009c80:	dc05      	bgt.n	8009c8e <__swbuf_r+0x4e>
 8009c82:	4621      	mov	r1, r4
 8009c84:	4628      	mov	r0, r5
 8009c86:	f7ff ffb3 	bl	8009bf0 <_fflush_r>
 8009c8a:	2800      	cmp	r0, #0
 8009c8c:	d1ed      	bne.n	8009c6a <__swbuf_r+0x2a>
 8009c8e:	68a3      	ldr	r3, [r4, #8]
 8009c90:	3b01      	subs	r3, #1
 8009c92:	60a3      	str	r3, [r4, #8]
 8009c94:	6823      	ldr	r3, [r4, #0]
 8009c96:	1c5a      	adds	r2, r3, #1
 8009c98:	6022      	str	r2, [r4, #0]
 8009c9a:	701e      	strb	r6, [r3, #0]
 8009c9c:	6962      	ldr	r2, [r4, #20]
 8009c9e:	1c43      	adds	r3, r0, #1
 8009ca0:	429a      	cmp	r2, r3
 8009ca2:	d004      	beq.n	8009cae <__swbuf_r+0x6e>
 8009ca4:	89a3      	ldrh	r3, [r4, #12]
 8009ca6:	07db      	lsls	r3, r3, #31
 8009ca8:	d5e1      	bpl.n	8009c6e <__swbuf_r+0x2e>
 8009caa:	2e0a      	cmp	r6, #10
 8009cac:	d1df      	bne.n	8009c6e <__swbuf_r+0x2e>
 8009cae:	4621      	mov	r1, r4
 8009cb0:	4628      	mov	r0, r5
 8009cb2:	f7ff ff9d 	bl	8009bf0 <_fflush_r>
 8009cb6:	2800      	cmp	r0, #0
 8009cb8:	d0d9      	beq.n	8009c6e <__swbuf_r+0x2e>
 8009cba:	e7d6      	b.n	8009c6a <__swbuf_r+0x2a>

08009cbc <__swsetup_r>:
 8009cbc:	b538      	push	{r3, r4, r5, lr}
 8009cbe:	4b29      	ldr	r3, [pc, #164]	@ (8009d64 <__swsetup_r+0xa8>)
 8009cc0:	4605      	mov	r5, r0
 8009cc2:	6818      	ldr	r0, [r3, #0]
 8009cc4:	460c      	mov	r4, r1
 8009cc6:	b118      	cbz	r0, 8009cd0 <__swsetup_r+0x14>
 8009cc8:	6a03      	ldr	r3, [r0, #32]
 8009cca:	b90b      	cbnz	r3, 8009cd0 <__swsetup_r+0x14>
 8009ccc:	f7fe f85e 	bl	8007d8c <__sinit>
 8009cd0:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8009cd4:	0719      	lsls	r1, r3, #28
 8009cd6:	d422      	bmi.n	8009d1e <__swsetup_r+0x62>
 8009cd8:	06da      	lsls	r2, r3, #27
 8009cda:	d407      	bmi.n	8009cec <__swsetup_r+0x30>
 8009cdc:	2209      	movs	r2, #9
 8009cde:	602a      	str	r2, [r5, #0]
 8009ce0:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
 8009ce4:	81a3      	strh	r3, [r4, #12]
 8009ce6:	f04f 30ff 	mov.w	r0, #4294967295
 8009cea:	e033      	b.n	8009d54 <__swsetup_r+0x98>
 8009cec:	0758      	lsls	r0, r3, #29
 8009cee:	d512      	bpl.n	8009d16 <__swsetup_r+0x5a>
 8009cf0:	6b61      	ldr	r1, [r4, #52]	@ 0x34
 8009cf2:	b141      	cbz	r1, 8009d06 <__swsetup_r+0x4a>
 8009cf4:	f104 0344 	add.w	r3, r4, #68	@ 0x44
 8009cf8:	4299      	cmp	r1, r3
 8009cfa:	d002      	beq.n	8009d02 <__swsetup_r+0x46>
 8009cfc:	4628      	mov	r0, r5
 8009cfe:	f7fe ffdf 	bl	8008cc0 <_free_r>
 8009d02:	2300      	movs	r3, #0
 8009d04:	6363      	str	r3, [r4, #52]	@ 0x34
 8009d06:	89a3      	ldrh	r3, [r4, #12]
 8009d08:	f023 0324 	bic.w	r3, r3, #36	@ 0x24
 8009d0c:	81a3      	strh	r3, [r4, #12]
 8009d0e:	2300      	movs	r3, #0
 8009d10:	6063      	str	r3, [r4, #4]
 8009d12:	6923      	ldr	r3, [r4, #16]
 8009d14:	6023      	str	r3, [r4, #0]
 8009d16:	89a3      	ldrh	r3, [r4, #12]
 8009d18:	f043 0308 	orr.w	r3, r3, #8
 8009d1c:	81a3      	strh	r3, [r4, #12]
 8009d1e:	6923      	ldr	r3, [r4, #16]
 8009d20:	b94b      	cbnz	r3, 8009d36 <__swsetup_r+0x7a>
 8009d22:	89a3      	ldrh	r3, [r4, #12]
 8009d24:	f403 7320 	and.w	r3, r3, #640	@ 0x280
 8009d28:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
 8009d2c:	d003      	beq.n	8009d36 <__swsetup_r+0x7a>
 8009d2e:	4621      	mov	r1, r4
 8009d30:	4628      	mov	r0, r5
 8009d32:	f000 f909 	bl	8009f48 <__smakebuf_r>
 8009d36:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8009d3a:	f013 0201 	ands.w	r2, r3, #1
 8009d3e:	d00a      	beq.n	8009d56 <__swsetup_r+0x9a>
 8009d40:	2200      	movs	r2, #0
 8009d42:	60a2      	str	r2, [r4, #8]
 8009d44:	6962      	ldr	r2, [r4, #20]
 8009d46:	4252      	negs	r2, r2
 8009d48:	61a2      	str	r2, [r4, #24]
 8009d4a:	6922      	ldr	r2, [r4, #16]
 8009d4c:	b942      	cbnz	r2, 8009d60 <__swsetup_r+0xa4>
 8009d4e:	f013 0080 	ands.w	r0, r3, #128	@ 0x80
 8009d52:	d1c5      	bne.n	8009ce0 <__swsetup_r+0x24>
 8009d54:	bd38      	pop	{r3, r4, r5, pc}
 8009d56:	0799      	lsls	r1, r3, #30
 8009d58:	bf58      	it	pl
 8009d5a:	6962      	ldrpl	r2, [r4, #20]
 8009d5c:	60a2      	str	r2, [r4, #8]
 8009d5e:	e7f4      	b.n	8009d4a <__swsetup_r+0x8e>
 8009d60:	2000      	movs	r0, #0
 8009d62:	e7f7      	b.n	8009d54 <__swsetup_r+0x98>
 8009d64:	20000018 	.word	0x20000018

08009d68 <memmove>:
 8009d68:	4288      	cmp	r0, r1
 8009d6a:	b510      	push	{r4, lr}
 8009d6c:	eb01 0402 	add.w	r4, r1, r2
 8009d70:	d902      	bls.n	8009d78 <memmove+0x10>
 8009d72:	4284      	cmp	r4, r0
 8009d74:	4623      	mov	r3, r4
 8009d76:	d807      	bhi.n	8009d88 <memmove+0x20>
 8009d78:	1e43      	subs	r3, r0, #1
 8009d7a:	42a1      	cmp	r1, r4
 8009d7c:	d008      	beq.n	8009d90 <memmove+0x28>
 8009d7e:	f811 2b01 	ldrb.w	r2, [r1], #1
 8009d82:	f803 2f01 	strb.w	r2, [r3, #1]!
 8009d86:	e7f8      	b.n	8009d7a <memmove+0x12>
 8009d88:	4402      	add	r2, r0
 8009d8a:	4601      	mov	r1, r0
 8009d8c:	428a      	cmp	r2, r1
 8009d8e:	d100      	bne.n	8009d92 <memmove+0x2a>
 8009d90:	bd10      	pop	{r4, pc}
 8009d92:	f813 4d01 	ldrb.w	r4, [r3, #-1]!
 8009d96:	f802 4d01 	strb.w	r4, [r2, #-1]!
 8009d9a:	e7f7      	b.n	8009d8c <memmove+0x24>

08009d9c <_sbrk_r>:
 8009d9c:	b538      	push	{r3, r4, r5, lr}
 8009d9e:	4d06      	ldr	r5, [pc, #24]	@ (8009db8 <_sbrk_r+0x1c>)
 8009da0:	2300      	movs	r3, #0
 8009da2:	4604      	mov	r4, r0
 8009da4:	4608      	mov	r0, r1
 8009da6:	602b      	str	r3, [r5, #0]
 8009da8:	f7fa f8d6 	bl	8003f58 <_sbrk>
 8009dac:	1c43      	adds	r3, r0, #1
 8009dae:	d102      	bne.n	8009db6 <_sbrk_r+0x1a>
 8009db0:	682b      	ldr	r3, [r5, #0]
 8009db2:	b103      	cbz	r3, 8009db6 <_sbrk_r+0x1a>
 8009db4:	6023      	str	r3, [r4, #0]
 8009db6:	bd38      	pop	{r3, r4, r5, pc}
 8009db8:	200004e0 	.word	0x200004e0

08009dbc <memcpy>:
 8009dbc:	440a      	add	r2, r1
 8009dbe:	4291      	cmp	r1, r2
 8009dc0:	f100 33ff 	add.w	r3, r0, #4294967295
 8009dc4:	d100      	bne.n	8009dc8 <memcpy+0xc>
 8009dc6:	4770      	bx	lr
 8009dc8:	b510      	push	{r4, lr}
 8009dca:	f811 4b01 	ldrb.w	r4, [r1], #1
 8009dce:	f803 4f01 	strb.w	r4, [r3, #1]!
 8009dd2:	4291      	cmp	r1, r2
 8009dd4:	d1f9      	bne.n	8009dca <memcpy+0xe>
 8009dd6:	bd10      	pop	{r4, pc}

08009dd8 <__assert_func>:
 8009dd8:	b51f      	push	{r0, r1, r2, r3, r4, lr}
 8009dda:	4614      	mov	r4, r2
 8009ddc:	461a      	mov	r2, r3
 8009dde:	4b09      	ldr	r3, [pc, #36]	@ (8009e04 <__assert_func+0x2c>)
 8009de0:	681b      	ldr	r3, [r3, #0]
 8009de2:	4605      	mov	r5, r0
 8009de4:	68d8      	ldr	r0, [r3, #12]
 8009de6:	b14c      	cbz	r4, 8009dfc <__assert_func+0x24>
 8009de8:	4b07      	ldr	r3, [pc, #28]	@ (8009e08 <__assert_func+0x30>)
 8009dea:	9100      	str	r1, [sp, #0]
 8009dec:	e9cd 3401 	strd	r3, r4, [sp, #4]
 8009df0:	4906      	ldr	r1, [pc, #24]	@ (8009e0c <__assert_func+0x34>)
 8009df2:	462b      	mov	r3, r5
 8009df4:	f000 f870 	bl	8009ed8 <fiprintf>
 8009df8:	f000 f904 	bl	800a004 <abort>
 8009dfc:	4b04      	ldr	r3, [pc, #16]	@ (8009e10 <__assert_func+0x38>)
 8009dfe:	461c      	mov	r4, r3
 8009e00:	e7f3      	b.n	8009dea <__assert_func+0x12>
 8009e02:	bf00      	nop
 8009e04:	20000018 	.word	0x20000018
 8009e08:	0800ba71 	.word	0x0800ba71
 8009e0c:	0800ba7e 	.word	0x0800ba7e
 8009e10:	0800baac 	.word	0x0800baac

08009e14 <_calloc_r>:
 8009e14:	b570      	push	{r4, r5, r6, lr}
 8009e16:	fba1 5402 	umull	r5, r4, r1, r2
 8009e1a:	b934      	cbnz	r4, 8009e2a <_calloc_r+0x16>
 8009e1c:	4629      	mov	r1, r5
 8009e1e:	f7fe ffc3 	bl	8008da8 <_malloc_r>
 8009e22:	4606      	mov	r6, r0
 8009e24:	b928      	cbnz	r0, 8009e32 <_calloc_r+0x1e>
 8009e26:	4630      	mov	r0, r6
 8009e28:	bd70      	pop	{r4, r5, r6, pc}
 8009e2a:	220c      	movs	r2, #12
 8009e2c:	6002      	str	r2, [r0, #0]
 8009e2e:	2600      	movs	r6, #0
 8009e30:	e7f9      	b.n	8009e26 <_calloc_r+0x12>
 8009e32:	462a      	mov	r2, r5
 8009e34:	4621      	mov	r1, r4
 8009e36:	f7fe f86a 	bl	8007f0e <memset>
 8009e3a:	e7f4      	b.n	8009e26 <_calloc_r+0x12>

08009e3c <__ascii_mbtowc>:
 8009e3c:	b082      	sub	sp, #8
 8009e3e:	b901      	cbnz	r1, 8009e42 <__ascii_mbtowc+0x6>
 8009e40:	a901      	add	r1, sp, #4
 8009e42:	b142      	cbz	r2, 8009e56 <__ascii_mbtowc+0x1a>
 8009e44:	b14b      	cbz	r3, 8009e5a <__ascii_mbtowc+0x1e>
 8009e46:	7813      	ldrb	r3, [r2, #0]
 8009e48:	600b      	str	r3, [r1, #0]
 8009e4a:	7812      	ldrb	r2, [r2, #0]
 8009e4c:	1e10      	subs	r0, r2, #0
 8009e4e:	bf18      	it	ne
 8009e50:	2001      	movne	r0, #1
 8009e52:	b002      	add	sp, #8
 8009e54:	4770      	bx	lr
 8009e56:	4610      	mov	r0, r2
 8009e58:	e7fb      	b.n	8009e52 <__ascii_mbtowc+0x16>
 8009e5a:	f06f 0001 	mvn.w	r0, #1
 8009e5e:	e7f8      	b.n	8009e52 <__ascii_mbtowc+0x16>

08009e60 <_realloc_r>:
 8009e60:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8009e64:	4607      	mov	r7, r0
 8009e66:	4614      	mov	r4, r2
 8009e68:	460d      	mov	r5, r1
 8009e6a:	b921      	cbnz	r1, 8009e76 <_realloc_r+0x16>
 8009e6c:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
 8009e70:	4611      	mov	r1, r2
 8009e72:	f7fe bf99 	b.w	8008da8 <_malloc_r>
 8009e76:	b92a      	cbnz	r2, 8009e84 <_realloc_r+0x24>
 8009e78:	f7fe ff22 	bl	8008cc0 <_free_r>
 8009e7c:	4625      	mov	r5, r4
 8009e7e:	4628      	mov	r0, r5
 8009e80:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8009e84:	f000 f8c5 	bl	800a012 <_malloc_usable_size_r>
 8009e88:	4284      	cmp	r4, r0
 8009e8a:	4606      	mov	r6, r0
 8009e8c:	d802      	bhi.n	8009e94 <_realloc_r+0x34>
 8009e8e:	ebb4 0f50 	cmp.w	r4, r0, lsr #1
 8009e92:	d8f4      	bhi.n	8009e7e <_realloc_r+0x1e>
 8009e94:	4621      	mov	r1, r4
 8009e96:	4638      	mov	r0, r7
 8009e98:	f7fe ff86 	bl	8008da8 <_malloc_r>
 8009e9c:	4680      	mov	r8, r0
 8009e9e:	b908      	cbnz	r0, 8009ea4 <_realloc_r+0x44>
 8009ea0:	4645      	mov	r5, r8
 8009ea2:	e7ec      	b.n	8009e7e <_realloc_r+0x1e>
 8009ea4:	42b4      	cmp	r4, r6
 8009ea6:	4622      	mov	r2, r4
 8009ea8:	4629      	mov	r1, r5
 8009eaa:	bf28      	it	cs
 8009eac:	4632      	movcs	r2, r6
 8009eae:	f7ff ff85 	bl	8009dbc <memcpy>
 8009eb2:	4629      	mov	r1, r5
 8009eb4:	4638      	mov	r0, r7
 8009eb6:	f7fe ff03 	bl	8008cc0 <_free_r>
 8009eba:	e7f1      	b.n	8009ea0 <_realloc_r+0x40>

08009ebc <__ascii_wctomb>:
 8009ebc:	4603      	mov	r3, r0
 8009ebe:	4608      	mov	r0, r1
 8009ec0:	b141      	cbz	r1, 8009ed4 <__ascii_wctomb+0x18>
 8009ec2:	2aff      	cmp	r2, #255	@ 0xff
 8009ec4:	d904      	bls.n	8009ed0 <__ascii_wctomb+0x14>
 8009ec6:	228a      	movs	r2, #138	@ 0x8a
 8009ec8:	601a      	str	r2, [r3, #0]
 8009eca:	f04f 30ff 	mov.w	r0, #4294967295
 8009ece:	4770      	bx	lr
 8009ed0:	700a      	strb	r2, [r1, #0]
 8009ed2:	2001      	movs	r0, #1
 8009ed4:	4770      	bx	lr
	...

08009ed8 <fiprintf>:
 8009ed8:	b40e      	push	{r1, r2, r3}
 8009eda:	b503      	push	{r0, r1, lr}
 8009edc:	4601      	mov	r1, r0
 8009ede:	ab03      	add	r3, sp, #12
 8009ee0:	4805      	ldr	r0, [pc, #20]	@ (8009ef8 <fiprintf+0x20>)
 8009ee2:	f853 2b04 	ldr.w	r2, [r3], #4
 8009ee6:	6800      	ldr	r0, [r0, #0]
 8009ee8:	9301      	str	r3, [sp, #4]
 8009eea:	f7ff fce5 	bl	80098b8 <_vfiprintf_r>
 8009eee:	b002      	add	sp, #8
 8009ef0:	f85d eb04 	ldr.w	lr, [sp], #4
 8009ef4:	b003      	add	sp, #12
 8009ef6:	4770      	bx	lr
 8009ef8:	20000018 	.word	0x20000018

08009efc <__swhatbuf_r>:
 8009efc:	b570      	push	{r4, r5, r6, lr}
 8009efe:	460c      	mov	r4, r1
 8009f00:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8009f04:	2900      	cmp	r1, #0
 8009f06:	b096      	sub	sp, #88	@ 0x58
 8009f08:	4615      	mov	r5, r2
 8009f0a:	461e      	mov	r6, r3
 8009f0c:	da0d      	bge.n	8009f2a <__swhatbuf_r+0x2e>
 8009f0e:	89a3      	ldrh	r3, [r4, #12]
 8009f10:	f013 0f80 	tst.w	r3, #128	@ 0x80
 8009f14:	f04f 0100 	mov.w	r1, #0
 8009f18:	bf14      	ite	ne
 8009f1a:	2340      	movne	r3, #64	@ 0x40
 8009f1c:	f44f 6380 	moveq.w	r3, #1024	@ 0x400
 8009f20:	2000      	movs	r0, #0
 8009f22:	6031      	str	r1, [r6, #0]
 8009f24:	602b      	str	r3, [r5, #0]
 8009f26:	b016      	add	sp, #88	@ 0x58
 8009f28:	bd70      	pop	{r4, r5, r6, pc}
 8009f2a:	466a      	mov	r2, sp
 8009f2c:	f000 f848 	bl	8009fc0 <_fstat_r>
 8009f30:	2800      	cmp	r0, #0
 8009f32:	dbec      	blt.n	8009f0e <__swhatbuf_r+0x12>
 8009f34:	9901      	ldr	r1, [sp, #4]
 8009f36:	f401 4170 	and.w	r1, r1, #61440	@ 0xf000
 8009f3a:	f5a1 5300 	sub.w	r3, r1, #8192	@ 0x2000
 8009f3e:	4259      	negs	r1, r3
 8009f40:	4159      	adcs	r1, r3
 8009f42:	f44f 6380 	mov.w	r3, #1024	@ 0x400
 8009f46:	e7eb      	b.n	8009f20 <__swhatbuf_r+0x24>

08009f48 <__smakebuf_r>:
 8009f48:	898b      	ldrh	r3, [r1, #12]
 8009f4a:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
 8009f4c:	079d      	lsls	r5, r3, #30
 8009f4e:	4606      	mov	r6, r0
 8009f50:	460c      	mov	r4, r1
 8009f52:	d507      	bpl.n	8009f64 <__smakebuf_r+0x1c>
 8009f54:	f104 0347 	add.w	r3, r4, #71	@ 0x47
 8009f58:	6023      	str	r3, [r4, #0]
 8009f5a:	6123      	str	r3, [r4, #16]
 8009f5c:	2301      	movs	r3, #1
 8009f5e:	6163      	str	r3, [r4, #20]
 8009f60:	b003      	add	sp, #12
 8009f62:	bdf0      	pop	{r4, r5, r6, r7, pc}
 8009f64:	ab01      	add	r3, sp, #4
 8009f66:	466a      	mov	r2, sp
 8009f68:	f7ff ffc8 	bl	8009efc <__swhatbuf_r>
 8009f6c:	9f00      	ldr	r7, [sp, #0]
 8009f6e:	4605      	mov	r5, r0
 8009f70:	4639      	mov	r1, r7
 8009f72:	4630      	mov	r0, r6
 8009f74:	f7fe ff18 	bl	8008da8 <_malloc_r>
 8009f78:	b948      	cbnz	r0, 8009f8e <__smakebuf_r+0x46>
 8009f7a:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8009f7e:	059a      	lsls	r2, r3, #22
 8009f80:	d4ee      	bmi.n	8009f60 <__smakebuf_r+0x18>
 8009f82:	f023 0303 	bic.w	r3, r3, #3
 8009f86:	f043 0302 	orr.w	r3, r3, #2
 8009f8a:	81a3      	strh	r3, [r4, #12]
 8009f8c:	e7e2      	b.n	8009f54 <__smakebuf_r+0xc>
 8009f8e:	89a3      	ldrh	r3, [r4, #12]
 8009f90:	6020      	str	r0, [r4, #0]
 8009f92:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
 8009f96:	81a3      	strh	r3, [r4, #12]
 8009f98:	9b01      	ldr	r3, [sp, #4]
 8009f9a:	e9c4 0704 	strd	r0, r7, [r4, #16]
 8009f9e:	b15b      	cbz	r3, 8009fb8 <__smakebuf_r+0x70>
 8009fa0:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 8009fa4:	4630      	mov	r0, r6
 8009fa6:	f000 f81d 	bl	8009fe4 <_isatty_r>
 8009faa:	b128      	cbz	r0, 8009fb8 <__smakebuf_r+0x70>
 8009fac:	89a3      	ldrh	r3, [r4, #12]
 8009fae:	f023 0303 	bic.w	r3, r3, #3
 8009fb2:	f043 0301 	orr.w	r3, r3, #1
 8009fb6:	81a3      	strh	r3, [r4, #12]
 8009fb8:	89a3      	ldrh	r3, [r4, #12]
 8009fba:	431d      	orrs	r5, r3
 8009fbc:	81a5      	strh	r5, [r4, #12]
 8009fbe:	e7cf      	b.n	8009f60 <__smakebuf_r+0x18>

08009fc0 <_fstat_r>:
 8009fc0:	b538      	push	{r3, r4, r5, lr}
 8009fc2:	4d07      	ldr	r5, [pc, #28]	@ (8009fe0 <_fstat_r+0x20>)
 8009fc4:	2300      	movs	r3, #0
 8009fc6:	4604      	mov	r4, r0
 8009fc8:	4608      	mov	r0, r1
 8009fca:	4611      	mov	r1, r2
 8009fcc:	602b      	str	r3, [r5, #0]
 8009fce:	f7f9 ff9a 	bl	8003f06 <_fstat>
 8009fd2:	1c43      	adds	r3, r0, #1
 8009fd4:	d102      	bne.n	8009fdc <_fstat_r+0x1c>
 8009fd6:	682b      	ldr	r3, [r5, #0]
 8009fd8:	b103      	cbz	r3, 8009fdc <_fstat_r+0x1c>
 8009fda:	6023      	str	r3, [r4, #0]
 8009fdc:	bd38      	pop	{r3, r4, r5, pc}
 8009fde:	bf00      	nop
 8009fe0:	200004e0 	.word	0x200004e0

08009fe4 <_isatty_r>:
 8009fe4:	b538      	push	{r3, r4, r5, lr}
 8009fe6:	4d06      	ldr	r5, [pc, #24]	@ (800a000 <_isatty_r+0x1c>)
 8009fe8:	2300      	movs	r3, #0
 8009fea:	4604      	mov	r4, r0
 8009fec:	4608      	mov	r0, r1
 8009fee:	602b      	str	r3, [r5, #0]
 8009ff0:	f7f9 ff99 	bl	8003f26 <_isatty>
 8009ff4:	1c43      	adds	r3, r0, #1
 8009ff6:	d102      	bne.n	8009ffe <_isatty_r+0x1a>
 8009ff8:	682b      	ldr	r3, [r5, #0]
 8009ffa:	b103      	cbz	r3, 8009ffe <_isatty_r+0x1a>
 8009ffc:	6023      	str	r3, [r4, #0]
 8009ffe:	bd38      	pop	{r3, r4, r5, pc}
 800a000:	200004e0 	.word	0x200004e0

0800a004 <abort>:
 800a004:	b508      	push	{r3, lr}
 800a006:	2006      	movs	r0, #6
 800a008:	f000 f834 	bl	800a074 <raise>
 800a00c:	2001      	movs	r0, #1
 800a00e:	f7f9 ff2a 	bl	8003e66 <_exit>

0800a012 <_malloc_usable_size_r>:
 800a012:	f851 3c04 	ldr.w	r3, [r1, #-4]
 800a016:	1f18      	subs	r0, r3, #4
 800a018:	2b00      	cmp	r3, #0
 800a01a:	bfbc      	itt	lt
 800a01c:	580b      	ldrlt	r3, [r1, r0]
 800a01e:	18c0      	addlt	r0, r0, r3
 800a020:	4770      	bx	lr

0800a022 <_raise_r>:
 800a022:	291f      	cmp	r1, #31
 800a024:	b538      	push	{r3, r4, r5, lr}
 800a026:	4605      	mov	r5, r0
 800a028:	460c      	mov	r4, r1
 800a02a:	d904      	bls.n	800a036 <_raise_r+0x14>
 800a02c:	2316      	movs	r3, #22
 800a02e:	6003      	str	r3, [r0, #0]
 800a030:	f04f 30ff 	mov.w	r0, #4294967295
 800a034:	bd38      	pop	{r3, r4, r5, pc}
 800a036:	6bc2      	ldr	r2, [r0, #60]	@ 0x3c
 800a038:	b112      	cbz	r2, 800a040 <_raise_r+0x1e>
 800a03a:	f852 3021 	ldr.w	r3, [r2, r1, lsl #2]
 800a03e:	b94b      	cbnz	r3, 800a054 <_raise_r+0x32>
 800a040:	4628      	mov	r0, r5
 800a042:	f000 f831 	bl	800a0a8 <_getpid_r>
 800a046:	4622      	mov	r2, r4
 800a048:	4601      	mov	r1, r0
 800a04a:	4628      	mov	r0, r5
 800a04c:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 800a050:	f000 b818 	b.w	800a084 <_kill_r>
 800a054:	2b01      	cmp	r3, #1
 800a056:	d00a      	beq.n	800a06e <_raise_r+0x4c>
 800a058:	1c59      	adds	r1, r3, #1
 800a05a:	d103      	bne.n	800a064 <_raise_r+0x42>
 800a05c:	2316      	movs	r3, #22
 800a05e:	6003      	str	r3, [r0, #0]
 800a060:	2001      	movs	r0, #1
 800a062:	e7e7      	b.n	800a034 <_raise_r+0x12>
 800a064:	2100      	movs	r1, #0
 800a066:	f842 1024 	str.w	r1, [r2, r4, lsl #2]
 800a06a:	4620      	mov	r0, r4
 800a06c:	4798      	blx	r3
 800a06e:	2000      	movs	r0, #0
 800a070:	e7e0      	b.n	800a034 <_raise_r+0x12>
	...

0800a074 <raise>:
 800a074:	4b02      	ldr	r3, [pc, #8]	@ (800a080 <raise+0xc>)
 800a076:	4601      	mov	r1, r0
 800a078:	6818      	ldr	r0, [r3, #0]
 800a07a:	f7ff bfd2 	b.w	800a022 <_raise_r>
 800a07e:	bf00      	nop
 800a080:	20000018 	.word	0x20000018

0800a084 <_kill_r>:
 800a084:	b538      	push	{r3, r4, r5, lr}
 800a086:	4d07      	ldr	r5, [pc, #28]	@ (800a0a4 <_kill_r+0x20>)
 800a088:	2300      	movs	r3, #0
 800a08a:	4604      	mov	r4, r0
 800a08c:	4608      	mov	r0, r1
 800a08e:	4611      	mov	r1, r2
 800a090:	602b      	str	r3, [r5, #0]
 800a092:	f7f9 fed8 	bl	8003e46 <_kill>
 800a096:	1c43      	adds	r3, r0, #1
 800a098:	d102      	bne.n	800a0a0 <_kill_r+0x1c>
 800a09a:	682b      	ldr	r3, [r5, #0]
 800a09c:	b103      	cbz	r3, 800a0a0 <_kill_r+0x1c>
 800a09e:	6023      	str	r3, [r4, #0]
 800a0a0:	bd38      	pop	{r3, r4, r5, pc}
 800a0a2:	bf00      	nop
 800a0a4:	200004e0 	.word	0x200004e0

0800a0a8 <_getpid_r>:
 800a0a8:	f7f9 bec5 	b.w	8003e36 <_getpid>

0800a0ac <asinf>:
 800a0ac:	b508      	push	{r3, lr}
 800a0ae:	ed2d 8b02 	vpush	{d8}
 800a0b2:	eeb0 8a40 	vmov.f32	s16, s0
 800a0b6:	f000 f99f 	bl	800a3f8 <__ieee754_asinf>
 800a0ba:	eeb4 8a48 	vcmp.f32	s16, s16
 800a0be:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800a0c2:	eef0 8a40 	vmov.f32	s17, s0
 800a0c6:	d615      	bvs.n	800a0f4 <asinf+0x48>
 800a0c8:	eeb0 0a48 	vmov.f32	s0, s16
 800a0cc:	f000 f892 	bl	800a1f4 <fabsf>
 800a0d0:	eef7 7a00 	vmov.f32	s15, #112	@ 0x3f800000  1.0
 800a0d4:	eeb4 0ae7 	vcmpe.f32	s0, s15
 800a0d8:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800a0dc:	dd0a      	ble.n	800a0f4 <asinf+0x48>
 800a0de:	f7fd ff69 	bl	8007fb4 <__errno>
 800a0e2:	ecbd 8b02 	vpop	{d8}
 800a0e6:	2321      	movs	r3, #33	@ 0x21
 800a0e8:	6003      	str	r3, [r0, #0]
 800a0ea:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
 800a0ee:	4804      	ldr	r0, [pc, #16]	@ (800a100 <asinf+0x54>)
 800a0f0:	f000 b8d8 	b.w	800a2a4 <nanf>
 800a0f4:	eeb0 0a68 	vmov.f32	s0, s17
 800a0f8:	ecbd 8b02 	vpop	{d8}
 800a0fc:	bd08      	pop	{r3, pc}
 800a0fe:	bf00      	nop
 800a100:	0800baac 	.word	0x0800baac

0800a104 <atan2f>:
 800a104:	f000 ba5c 	b.w	800a5c0 <__ieee754_atan2f>

0800a108 <powf>:
 800a108:	b508      	push	{r3, lr}
 800a10a:	ed2d 8b04 	vpush	{d8-d9}
 800a10e:	eeb0 8a60 	vmov.f32	s16, s1
 800a112:	eeb0 9a40 	vmov.f32	s18, s0
 800a116:	f000 faf3 	bl	800a700 <__ieee754_powf>
 800a11a:	eeb4 8a48 	vcmp.f32	s16, s16
 800a11e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800a122:	eef0 8a40 	vmov.f32	s17, s0
 800a126:	d63e      	bvs.n	800a1a6 <powf+0x9e>
 800a128:	eeb5 9a40 	vcmp.f32	s18, #0.0
 800a12c:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800a130:	d112      	bne.n	800a158 <powf+0x50>
 800a132:	eeb5 8a40 	vcmp.f32	s16, #0.0
 800a136:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800a13a:	d039      	beq.n	800a1b0 <powf+0xa8>
 800a13c:	eeb0 0a48 	vmov.f32	s0, s16
 800a140:	f000 f8a6 	bl	800a290 <finitef>
 800a144:	b378      	cbz	r0, 800a1a6 <powf+0x9e>
 800a146:	eeb5 8ac0 	vcmpe.f32	s16, #0.0
 800a14a:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800a14e:	d52a      	bpl.n	800a1a6 <powf+0x9e>
 800a150:	f7fd ff30 	bl	8007fb4 <__errno>
 800a154:	2322      	movs	r3, #34	@ 0x22
 800a156:	e014      	b.n	800a182 <powf+0x7a>
 800a158:	f000 f89a 	bl	800a290 <finitef>
 800a15c:	b998      	cbnz	r0, 800a186 <powf+0x7e>
 800a15e:	eeb0 0a49 	vmov.f32	s0, s18
 800a162:	f000 f895 	bl	800a290 <finitef>
 800a166:	b170      	cbz	r0, 800a186 <powf+0x7e>
 800a168:	eeb0 0a48 	vmov.f32	s0, s16
 800a16c:	f000 f890 	bl	800a290 <finitef>
 800a170:	b148      	cbz	r0, 800a186 <powf+0x7e>
 800a172:	eef4 8a68 	vcmp.f32	s17, s17
 800a176:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800a17a:	d7e9      	bvc.n	800a150 <powf+0x48>
 800a17c:	f7fd ff1a 	bl	8007fb4 <__errno>
 800a180:	2321      	movs	r3, #33	@ 0x21
 800a182:	6003      	str	r3, [r0, #0]
 800a184:	e00f      	b.n	800a1a6 <powf+0x9e>
 800a186:	eef5 8a40 	vcmp.f32	s17, #0.0
 800a18a:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800a18e:	d10a      	bne.n	800a1a6 <powf+0x9e>
 800a190:	eeb0 0a49 	vmov.f32	s0, s18
 800a194:	f000 f87c 	bl	800a290 <finitef>
 800a198:	b128      	cbz	r0, 800a1a6 <powf+0x9e>
 800a19a:	eeb0 0a48 	vmov.f32	s0, s16
 800a19e:	f000 f877 	bl	800a290 <finitef>
 800a1a2:	2800      	cmp	r0, #0
 800a1a4:	d1d4      	bne.n	800a150 <powf+0x48>
 800a1a6:	eeb0 0a68 	vmov.f32	s0, s17
 800a1aa:	ecbd 8b04 	vpop	{d8-d9}
 800a1ae:	bd08      	pop	{r3, pc}
 800a1b0:	eef7 8a00 	vmov.f32	s17, #112	@ 0x3f800000  1.0
 800a1b4:	e7f7      	b.n	800a1a6 <powf+0x9e>
	...

0800a1b8 <sqrtf>:
 800a1b8:	b508      	push	{r3, lr}
 800a1ba:	ed2d 8b02 	vpush	{d8}
 800a1be:	eeb0 8a40 	vmov.f32	s16, s0
 800a1c2:	f000 f875 	bl	800a2b0 <__ieee754_sqrtf>
 800a1c6:	eeb4 8a48 	vcmp.f32	s16, s16
 800a1ca:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800a1ce:	d60c      	bvs.n	800a1ea <sqrtf+0x32>
 800a1d0:	eddf 8a07 	vldr	s17, [pc, #28]	@ 800a1f0 <sqrtf+0x38>
 800a1d4:	eeb4 8ae8 	vcmpe.f32	s16, s17
 800a1d8:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800a1dc:	d505      	bpl.n	800a1ea <sqrtf+0x32>
 800a1de:	f7fd fee9 	bl	8007fb4 <__errno>
 800a1e2:	ee88 0aa8 	vdiv.f32	s0, s17, s17
 800a1e6:	2321      	movs	r3, #33	@ 0x21
 800a1e8:	6003      	str	r3, [r0, #0]
 800a1ea:	ecbd 8b02 	vpop	{d8}
 800a1ee:	bd08      	pop	{r3, pc}
 800a1f0:	00000000 	.word	0x00000000

0800a1f4 <fabsf>:
 800a1f4:	ee10 3a10 	vmov	r3, s0
 800a1f8:	f023 4300 	bic.w	r3, r3, #2147483648	@ 0x80000000
 800a1fc:	ee00 3a10 	vmov	s0, r3
 800a200:	4770      	bx	lr
	...

0800a204 <sinf>:
 800a204:	ee10 3a10 	vmov	r3, s0
 800a208:	b507      	push	{r0, r1, r2, lr}
 800a20a:	4a1f      	ldr	r2, [pc, #124]	@ (800a288 <sinf+0x84>)
 800a20c:	f023 4300 	bic.w	r3, r3, #2147483648	@ 0x80000000
 800a210:	4293      	cmp	r3, r2
 800a212:	d807      	bhi.n	800a224 <sinf+0x20>
 800a214:	eddf 0a1d 	vldr	s1, [pc, #116]	@ 800a28c <sinf+0x88>
 800a218:	2000      	movs	r0, #0
 800a21a:	b003      	add	sp, #12
 800a21c:	f85d eb04 	ldr.w	lr, [sp], #4
 800a220:	f000 b8a2 	b.w	800a368 <__kernel_sinf>
 800a224:	f1b3 4fff 	cmp.w	r3, #2139095040	@ 0x7f800000
 800a228:	d304      	bcc.n	800a234 <sinf+0x30>
 800a22a:	ee30 0a40 	vsub.f32	s0, s0, s0
 800a22e:	b003      	add	sp, #12
 800a230:	f85d fb04 	ldr.w	pc, [sp], #4
 800a234:	4668      	mov	r0, sp
 800a236:	f000 fd31 	bl	800ac9c <__ieee754_rem_pio2f>
 800a23a:	f000 0003 	and.w	r0, r0, #3
 800a23e:	2801      	cmp	r0, #1
 800a240:	d00a      	beq.n	800a258 <sinf+0x54>
 800a242:	2802      	cmp	r0, #2
 800a244:	d00f      	beq.n	800a266 <sinf+0x62>
 800a246:	b9c0      	cbnz	r0, 800a27a <sinf+0x76>
 800a248:	eddd 0a01 	vldr	s1, [sp, #4]
 800a24c:	ed9d 0a00 	vldr	s0, [sp]
 800a250:	2001      	movs	r0, #1
 800a252:	f000 f889 	bl	800a368 <__kernel_sinf>
 800a256:	e7ea      	b.n	800a22e <sinf+0x2a>
 800a258:	eddd 0a01 	vldr	s1, [sp, #4]
 800a25c:	ed9d 0a00 	vldr	s0, [sp]
 800a260:	f000 f82a 	bl	800a2b8 <__kernel_cosf>
 800a264:	e7e3      	b.n	800a22e <sinf+0x2a>
 800a266:	eddd 0a01 	vldr	s1, [sp, #4]
 800a26a:	ed9d 0a00 	vldr	s0, [sp]
 800a26e:	2001      	movs	r0, #1
 800a270:	f000 f87a 	bl	800a368 <__kernel_sinf>
 800a274:	eeb1 0a40 	vneg.f32	s0, s0
 800a278:	e7d9      	b.n	800a22e <sinf+0x2a>
 800a27a:	eddd 0a01 	vldr	s1, [sp, #4]
 800a27e:	ed9d 0a00 	vldr	s0, [sp]
 800a282:	f000 f819 	bl	800a2b8 <__kernel_cosf>
 800a286:	e7f5      	b.n	800a274 <sinf+0x70>
 800a288:	3f490fd8 	.word	0x3f490fd8
 800a28c:	00000000 	.word	0x00000000

0800a290 <finitef>:
 800a290:	ee10 3a10 	vmov	r3, s0
 800a294:	f023 4000 	bic.w	r0, r3, #2147483648	@ 0x80000000
 800a298:	f1b0 4fff 	cmp.w	r0, #2139095040	@ 0x7f800000
 800a29c:	bfac      	ite	ge
 800a29e:	2000      	movge	r0, #0
 800a2a0:	2001      	movlt	r0, #1
 800a2a2:	4770      	bx	lr

0800a2a4 <nanf>:
 800a2a4:	ed9f 0a01 	vldr	s0, [pc, #4]	@ 800a2ac <nanf+0x8>
 800a2a8:	4770      	bx	lr
 800a2aa:	bf00      	nop
 800a2ac:	7fc00000 	.word	0x7fc00000

0800a2b0 <__ieee754_sqrtf>:
 800a2b0:	eeb1 0ac0 	vsqrt.f32	s0, s0
 800a2b4:	4770      	bx	lr
	...

0800a2b8 <__kernel_cosf>:
 800a2b8:	ee10 3a10 	vmov	r3, s0
 800a2bc:	f023 4300 	bic.w	r3, r3, #2147483648	@ 0x80000000
 800a2c0:	f1b3 5f48 	cmp.w	r3, #838860800	@ 0x32000000
 800a2c4:	eef0 6a40 	vmov.f32	s13, s0
 800a2c8:	eeb7 0a00 	vmov.f32	s0, #112	@ 0x3f800000  1.0
 800a2cc:	d204      	bcs.n	800a2d8 <__kernel_cosf+0x20>
 800a2ce:	eefd 7ae6 	vcvt.s32.f32	s15, s13
 800a2d2:	ee17 2a90 	vmov	r2, s15
 800a2d6:	b342      	cbz	r2, 800a32a <__kernel_cosf+0x72>
 800a2d8:	ee26 7aa6 	vmul.f32	s14, s13, s13
 800a2dc:	eddf 7a1a 	vldr	s15, [pc, #104]	@ 800a348 <__kernel_cosf+0x90>
 800a2e0:	ed9f 6a1a 	vldr	s12, [pc, #104]	@ 800a34c <__kernel_cosf+0x94>
 800a2e4:	4a1a      	ldr	r2, [pc, #104]	@ (800a350 <__kernel_cosf+0x98>)
 800a2e6:	eea7 6a27 	vfma.f32	s12, s14, s15
 800a2ea:	4293      	cmp	r3, r2
 800a2ec:	eddf 7a19 	vldr	s15, [pc, #100]	@ 800a354 <__kernel_cosf+0x9c>
 800a2f0:	eee6 7a07 	vfma.f32	s15, s12, s14
 800a2f4:	ed9f 6a18 	vldr	s12, [pc, #96]	@ 800a358 <__kernel_cosf+0xa0>
 800a2f8:	eea7 6a87 	vfma.f32	s12, s15, s14
 800a2fc:	eddf 7a17 	vldr	s15, [pc, #92]	@ 800a35c <__kernel_cosf+0xa4>
 800a300:	eee6 7a07 	vfma.f32	s15, s12, s14
 800a304:	ed9f 6a16 	vldr	s12, [pc, #88]	@ 800a360 <__kernel_cosf+0xa8>
 800a308:	eea7 6a87 	vfma.f32	s12, s15, s14
 800a30c:	ee60 0ae6 	vnmul.f32	s1, s1, s13
 800a310:	ee26 6a07 	vmul.f32	s12, s12, s14
 800a314:	eef6 7a00 	vmov.f32	s15, #96	@ 0x3f000000  0.5
 800a318:	eee7 0a06 	vfma.f32	s1, s14, s12
 800a31c:	ee67 7a27 	vmul.f32	s15, s14, s15
 800a320:	d804      	bhi.n	800a32c <__kernel_cosf+0x74>
 800a322:	ee77 7ae0 	vsub.f32	s15, s15, s1
 800a326:	ee30 0a67 	vsub.f32	s0, s0, s15
 800a32a:	4770      	bx	lr
 800a32c:	4a0d      	ldr	r2, [pc, #52]	@ (800a364 <__kernel_cosf+0xac>)
 800a32e:	4293      	cmp	r3, r2
 800a330:	bf9a      	itte	ls
 800a332:	f103 437f 	addls.w	r3, r3, #4278190080	@ 0xff000000
 800a336:	ee07 3a10 	vmovls	s14, r3
 800a33a:	eeb5 7a02 	vmovhi.f32	s14, #82	@ 0x3e900000  0.2812500
 800a33e:	ee30 0a47 	vsub.f32	s0, s0, s14
 800a342:	ee77 7ac7 	vsub.f32	s15, s15, s14
 800a346:	e7ec      	b.n	800a322 <__kernel_cosf+0x6a>
 800a348:	ad47d74e 	.word	0xad47d74e
 800a34c:	310f74f6 	.word	0x310f74f6
 800a350:	3e999999 	.word	0x3e999999
 800a354:	b493f27c 	.word	0xb493f27c
 800a358:	37d00d01 	.word	0x37d00d01
 800a35c:	bab60b61 	.word	0xbab60b61
 800a360:	3d2aaaab 	.word	0x3d2aaaab
 800a364:	3f480000 	.word	0x3f480000

0800a368 <__kernel_sinf>:
 800a368:	ee10 3a10 	vmov	r3, s0
 800a36c:	f023 4300 	bic.w	r3, r3, #2147483648	@ 0x80000000
 800a370:	f1b3 5f48 	cmp.w	r3, #838860800	@ 0x32000000
 800a374:	d204      	bcs.n	800a380 <__kernel_sinf+0x18>
 800a376:	eefd 7ac0 	vcvt.s32.f32	s15, s0
 800a37a:	ee17 3a90 	vmov	r3, s15
 800a37e:	b35b      	cbz	r3, 800a3d8 <__kernel_sinf+0x70>
 800a380:	ee20 7a00 	vmul.f32	s14, s0, s0
 800a384:	eddf 7a15 	vldr	s15, [pc, #84]	@ 800a3dc <__kernel_sinf+0x74>
 800a388:	ed9f 6a15 	vldr	s12, [pc, #84]	@ 800a3e0 <__kernel_sinf+0x78>
 800a38c:	eea7 6a27 	vfma.f32	s12, s14, s15
 800a390:	eddf 7a14 	vldr	s15, [pc, #80]	@ 800a3e4 <__kernel_sinf+0x7c>
 800a394:	eee6 7a07 	vfma.f32	s15, s12, s14
 800a398:	ed9f 6a13 	vldr	s12, [pc, #76]	@ 800a3e8 <__kernel_sinf+0x80>
 800a39c:	eea7 6a87 	vfma.f32	s12, s15, s14
 800a3a0:	eddf 7a12 	vldr	s15, [pc, #72]	@ 800a3ec <__kernel_sinf+0x84>
 800a3a4:	ee60 6a07 	vmul.f32	s13, s0, s14
 800a3a8:	eee6 7a07 	vfma.f32	s15, s12, s14
 800a3ac:	b930      	cbnz	r0, 800a3bc <__kernel_sinf+0x54>
 800a3ae:	ed9f 6a10 	vldr	s12, [pc, #64]	@ 800a3f0 <__kernel_sinf+0x88>
 800a3b2:	eea7 6a27 	vfma.f32	s12, s14, s15
 800a3b6:	eea6 0a26 	vfma.f32	s0, s12, s13
 800a3ba:	4770      	bx	lr
 800a3bc:	ee67 7ae6 	vnmul.f32	s15, s15, s13
 800a3c0:	eeb6 6a00 	vmov.f32	s12, #96	@ 0x3f000000  0.5
 800a3c4:	eee0 7a86 	vfma.f32	s15, s1, s12
 800a3c8:	eed7 0a87 	vfnms.f32	s1, s15, s14
 800a3cc:	eddf 7a09 	vldr	s15, [pc, #36]	@ 800a3f4 <__kernel_sinf+0x8c>
 800a3d0:	eee6 0aa7 	vfma.f32	s1, s13, s15
 800a3d4:	ee30 0a60 	vsub.f32	s0, s0, s1
 800a3d8:	4770      	bx	lr
 800a3da:	bf00      	nop
 800a3dc:	2f2ec9d3 	.word	0x2f2ec9d3
 800a3e0:	b2d72f34 	.word	0xb2d72f34
 800a3e4:	3638ef1b 	.word	0x3638ef1b
 800a3e8:	b9500d01 	.word	0xb9500d01
 800a3ec:	3c088889 	.word	0x3c088889
 800a3f0:	be2aaaab 	.word	0xbe2aaaab
 800a3f4:	3e2aaaab 	.word	0x3e2aaaab

0800a3f8 <__ieee754_asinf>:
 800a3f8:	b538      	push	{r3, r4, r5, lr}
 800a3fa:	ee10 5a10 	vmov	r5, s0
 800a3fe:	f025 4400 	bic.w	r4, r5, #2147483648	@ 0x80000000
 800a402:	f1b4 5f7e 	cmp.w	r4, #1065353216	@ 0x3f800000
 800a406:	ed2d 8b04 	vpush	{d8-d9}
 800a40a:	d10c      	bne.n	800a426 <__ieee754_asinf+0x2e>
 800a40c:	eddf 7a5c 	vldr	s15, [pc, #368]	@ 800a580 <__ieee754_asinf+0x188>
 800a410:	ed9f 7a5c 	vldr	s14, [pc, #368]	@ 800a584 <__ieee754_asinf+0x18c>
 800a414:	ee60 7a27 	vmul.f32	s15, s0, s15
 800a418:	eee0 7a07 	vfma.f32	s15, s0, s14
 800a41c:	eeb0 0a67 	vmov.f32	s0, s15
 800a420:	ecbd 8b04 	vpop	{d8-d9}
 800a424:	bd38      	pop	{r3, r4, r5, pc}
 800a426:	d904      	bls.n	800a432 <__ieee754_asinf+0x3a>
 800a428:	ee70 7a40 	vsub.f32	s15, s0, s0
 800a42c:	ee87 0aa7 	vdiv.f32	s0, s15, s15
 800a430:	e7f6      	b.n	800a420 <__ieee754_asinf+0x28>
 800a432:	f1b4 5f7c 	cmp.w	r4, #1056964608	@ 0x3f000000
 800a436:	eef7 8a00 	vmov.f32	s17, #112	@ 0x3f800000  1.0
 800a43a:	d20b      	bcs.n	800a454 <__ieee754_asinf+0x5c>
 800a43c:	f1b4 5f48 	cmp.w	r4, #838860800	@ 0x32000000
 800a440:	d252      	bcs.n	800a4e8 <__ieee754_asinf+0xf0>
 800a442:	eddf 7a51 	vldr	s15, [pc, #324]	@ 800a588 <__ieee754_asinf+0x190>
 800a446:	ee70 7a27 	vadd.f32	s15, s0, s15
 800a44a:	eef4 7ae8 	vcmpe.f32	s15, s17
 800a44e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800a452:	dce5      	bgt.n	800a420 <__ieee754_asinf+0x28>
 800a454:	f7ff fece 	bl	800a1f4 <fabsf>
 800a458:	ee38 8ac0 	vsub.f32	s16, s17, s0
 800a45c:	eef6 7a00 	vmov.f32	s15, #96	@ 0x3f000000  0.5
 800a460:	ee28 8a27 	vmul.f32	s16, s16, s15
 800a464:	ed9f 7a49 	vldr	s14, [pc, #292]	@ 800a58c <__ieee754_asinf+0x194>
 800a468:	eddf 7a49 	vldr	s15, [pc, #292]	@ 800a590 <__ieee754_asinf+0x198>
 800a46c:	ed9f 9a49 	vldr	s18, [pc, #292]	@ 800a594 <__ieee754_asinf+0x19c>
 800a470:	eea8 7a27 	vfma.f32	s14, s16, s15
 800a474:	eddf 7a48 	vldr	s15, [pc, #288]	@ 800a598 <__ieee754_asinf+0x1a0>
 800a478:	eee7 7a08 	vfma.f32	s15, s14, s16
 800a47c:	ed9f 7a47 	vldr	s14, [pc, #284]	@ 800a59c <__ieee754_asinf+0x1a4>
 800a480:	eea7 7a88 	vfma.f32	s14, s15, s16
 800a484:	eddf 7a46 	vldr	s15, [pc, #280]	@ 800a5a0 <__ieee754_asinf+0x1a8>
 800a488:	eee7 7a08 	vfma.f32	s15, s14, s16
 800a48c:	ed9f 7a45 	vldr	s14, [pc, #276]	@ 800a5a4 <__ieee754_asinf+0x1ac>
 800a490:	eea7 9a88 	vfma.f32	s18, s15, s16
 800a494:	eddf 7a44 	vldr	s15, [pc, #272]	@ 800a5a8 <__ieee754_asinf+0x1b0>
 800a498:	eee8 7a07 	vfma.f32	s15, s16, s14
 800a49c:	ed9f 7a43 	vldr	s14, [pc, #268]	@ 800a5ac <__ieee754_asinf+0x1b4>
 800a4a0:	eea7 7a88 	vfma.f32	s14, s15, s16
 800a4a4:	eddf 7a42 	vldr	s15, [pc, #264]	@ 800a5b0 <__ieee754_asinf+0x1b8>
 800a4a8:	eee7 7a08 	vfma.f32	s15, s14, s16
 800a4ac:	eeb0 0a48 	vmov.f32	s0, s16
 800a4b0:	eee7 8a88 	vfma.f32	s17, s15, s16
 800a4b4:	f7ff fefc 	bl	800a2b0 <__ieee754_sqrtf>
 800a4b8:	4b3e      	ldr	r3, [pc, #248]	@ (800a5b4 <__ieee754_asinf+0x1bc>)
 800a4ba:	ee29 9a08 	vmul.f32	s18, s18, s16
 800a4be:	429c      	cmp	r4, r3
 800a4c0:	ee89 6a28 	vdiv.f32	s12, s18, s17
 800a4c4:	eef0 6a00 	vmov.f32	s13, #0	@ 0x40000000  2.0
 800a4c8:	d93d      	bls.n	800a546 <__ieee754_asinf+0x14e>
 800a4ca:	eea0 0a06 	vfma.f32	s0, s0, s12
 800a4ce:	eddf 7a3a 	vldr	s15, [pc, #232]	@ 800a5b8 <__ieee754_asinf+0x1c0>
 800a4d2:	eee0 7a26 	vfma.f32	s15, s0, s13
 800a4d6:	ed9f 0a2b 	vldr	s0, [pc, #172]	@ 800a584 <__ieee754_asinf+0x18c>
 800a4da:	ee30 0a67 	vsub.f32	s0, s0, s15
 800a4de:	2d00      	cmp	r5, #0
 800a4e0:	bfd8      	it	le
 800a4e2:	eeb1 0a40 	vnegle.f32	s0, s0
 800a4e6:	e79b      	b.n	800a420 <__ieee754_asinf+0x28>
 800a4e8:	ee60 7a00 	vmul.f32	s15, s0, s0
 800a4ec:	eddf 6a28 	vldr	s13, [pc, #160]	@ 800a590 <__ieee754_asinf+0x198>
 800a4f0:	ed9f 7a26 	vldr	s14, [pc, #152]	@ 800a58c <__ieee754_asinf+0x194>
 800a4f4:	ed9f 6a2b 	vldr	s12, [pc, #172]	@ 800a5a4 <__ieee754_asinf+0x1ac>
 800a4f8:	eea7 7aa6 	vfma.f32	s14, s15, s13
 800a4fc:	eddf 6a26 	vldr	s13, [pc, #152]	@ 800a598 <__ieee754_asinf+0x1a0>
 800a500:	eee7 6a27 	vfma.f32	s13, s14, s15
 800a504:	ed9f 7a25 	vldr	s14, [pc, #148]	@ 800a59c <__ieee754_asinf+0x1a4>
 800a508:	eea6 7aa7 	vfma.f32	s14, s13, s15
 800a50c:	eddf 6a24 	vldr	s13, [pc, #144]	@ 800a5a0 <__ieee754_asinf+0x1a8>
 800a510:	eee7 6a27 	vfma.f32	s13, s14, s15
 800a514:	ed9f 7a1f 	vldr	s14, [pc, #124]	@ 800a594 <__ieee754_asinf+0x19c>
 800a518:	eea6 7aa7 	vfma.f32	s14, s13, s15
 800a51c:	eddf 6a22 	vldr	s13, [pc, #136]	@ 800a5a8 <__ieee754_asinf+0x1b0>
 800a520:	eee7 6a86 	vfma.f32	s13, s15, s12
 800a524:	ed9f 6a21 	vldr	s12, [pc, #132]	@ 800a5ac <__ieee754_asinf+0x1b4>
 800a528:	eea6 6aa7 	vfma.f32	s12, s13, s15
 800a52c:	eddf 6a20 	vldr	s13, [pc, #128]	@ 800a5b0 <__ieee754_asinf+0x1b8>
 800a530:	eee6 6a27 	vfma.f32	s13, s12, s15
 800a534:	ee27 7a27 	vmul.f32	s14, s14, s15
 800a538:	eee6 8aa7 	vfma.f32	s17, s13, s15
 800a53c:	eec7 7a28 	vdiv.f32	s15, s14, s17
 800a540:	eea0 0a27 	vfma.f32	s0, s0, s15
 800a544:	e76c      	b.n	800a420 <__ieee754_asinf+0x28>
 800a546:	ee10 3a10 	vmov	r3, s0
 800a54a:	f36f 030b 	bfc	r3, #0, #12
 800a54e:	ee07 3a10 	vmov	s14, r3
 800a552:	eea7 8a47 	vfms.f32	s16, s14, s14
 800a556:	ee70 5a00 	vadd.f32	s11, s0, s0
 800a55a:	ee30 0a07 	vadd.f32	s0, s0, s14
 800a55e:	eddf 7a08 	vldr	s15, [pc, #32]	@ 800a580 <__ieee754_asinf+0x188>
 800a562:	ee88 5a00 	vdiv.f32	s10, s16, s0
 800a566:	ed9f 0a15 	vldr	s0, [pc, #84]	@ 800a5bc <__ieee754_asinf+0x1c4>
 800a56a:	eee5 7a66 	vfms.f32	s15, s10, s13
 800a56e:	eed5 7a86 	vfnms.f32	s15, s11, s12
 800a572:	eeb0 6a40 	vmov.f32	s12, s0
 800a576:	eea7 6a66 	vfms.f32	s12, s14, s13
 800a57a:	ee77 7ac6 	vsub.f32	s15, s15, s12
 800a57e:	e7ac      	b.n	800a4da <__ieee754_asinf+0xe2>
 800a580:	b33bbd2e 	.word	0xb33bbd2e
 800a584:	3fc90fdb 	.word	0x3fc90fdb
 800a588:	7149f2ca 	.word	0x7149f2ca
 800a58c:	3a4f7f04 	.word	0x3a4f7f04
 800a590:	3811ef08 	.word	0x3811ef08
 800a594:	3e2aaaab 	.word	0x3e2aaaab
 800a598:	bd241146 	.word	0xbd241146
 800a59c:	3e4e0aa8 	.word	0x3e4e0aa8
 800a5a0:	bea6b090 	.word	0xbea6b090
 800a5a4:	3d9dc62e 	.word	0x3d9dc62e
 800a5a8:	bf303361 	.word	0xbf303361
 800a5ac:	4001572d 	.word	0x4001572d
 800a5b0:	c019d139 	.word	0xc019d139
 800a5b4:	3f799999 	.word	0x3f799999
 800a5b8:	333bbd2e 	.word	0x333bbd2e
 800a5bc:	3f490fdb 	.word	0x3f490fdb

0800a5c0 <__ieee754_atan2f>:
 800a5c0:	ee10 2a90 	vmov	r2, s1
 800a5c4:	f022 4100 	bic.w	r1, r2, #2147483648	@ 0x80000000
 800a5c8:	f1b1 4fff 	cmp.w	r1, #2139095040	@ 0x7f800000
 800a5cc:	b510      	push	{r4, lr}
 800a5ce:	eef0 7a40 	vmov.f32	s15, s0
 800a5d2:	d806      	bhi.n	800a5e2 <__ieee754_atan2f+0x22>
 800a5d4:	ee10 0a10 	vmov	r0, s0
 800a5d8:	f020 4300 	bic.w	r3, r0, #2147483648	@ 0x80000000
 800a5dc:	f1b3 4fff 	cmp.w	r3, #2139095040	@ 0x7f800000
 800a5e0:	d904      	bls.n	800a5ec <__ieee754_atan2f+0x2c>
 800a5e2:	ee77 7aa0 	vadd.f32	s15, s15, s1
 800a5e6:	eeb0 0a67 	vmov.f32	s0, s15
 800a5ea:	bd10      	pop	{r4, pc}
 800a5ec:	f1b2 5f7e 	cmp.w	r2, #1065353216	@ 0x3f800000
 800a5f0:	d103      	bne.n	800a5fa <__ieee754_atan2f+0x3a>
 800a5f2:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
 800a5f6:	f000 bc81 	b.w	800aefc <atanf>
 800a5fa:	1794      	asrs	r4, r2, #30
 800a5fc:	f004 0402 	and.w	r4, r4, #2
 800a600:	ea44 74d0 	orr.w	r4, r4, r0, lsr #31
 800a604:	b943      	cbnz	r3, 800a618 <__ieee754_atan2f+0x58>
 800a606:	2c02      	cmp	r4, #2
 800a608:	d05e      	beq.n	800a6c8 <__ieee754_atan2f+0x108>
 800a60a:	ed9f 7a34 	vldr	s14, [pc, #208]	@ 800a6dc <__ieee754_atan2f+0x11c>
 800a60e:	2c03      	cmp	r4, #3
 800a610:	bf08      	it	eq
 800a612:	eef0 7a47 	vmoveq.f32	s15, s14
 800a616:	e7e6      	b.n	800a5e6 <__ieee754_atan2f+0x26>
 800a618:	b941      	cbnz	r1, 800a62c <__ieee754_atan2f+0x6c>
 800a61a:	eddf 7a31 	vldr	s15, [pc, #196]	@ 800a6e0 <__ieee754_atan2f+0x120>
 800a61e:	ed9f 7a31 	vldr	s14, [pc, #196]	@ 800a6e4 <__ieee754_atan2f+0x124>
 800a622:	2800      	cmp	r0, #0
 800a624:	bfa8      	it	ge
 800a626:	eef0 7a47 	vmovge.f32	s15, s14
 800a62a:	e7dc      	b.n	800a5e6 <__ieee754_atan2f+0x26>
 800a62c:	f1b1 4fff 	cmp.w	r1, #2139095040	@ 0x7f800000
 800a630:	d110      	bne.n	800a654 <__ieee754_atan2f+0x94>
 800a632:	f1b3 4fff 	cmp.w	r3, #2139095040	@ 0x7f800000
 800a636:	f104 34ff 	add.w	r4, r4, #4294967295
 800a63a:	d107      	bne.n	800a64c <__ieee754_atan2f+0x8c>
 800a63c:	2c02      	cmp	r4, #2
 800a63e:	d846      	bhi.n	800a6ce <__ieee754_atan2f+0x10e>
 800a640:	4b29      	ldr	r3, [pc, #164]	@ (800a6e8 <__ieee754_atan2f+0x128>)
 800a642:	eb03 0384 	add.w	r3, r3, r4, lsl #2
 800a646:	edd3 7a00 	vldr	s15, [r3]
 800a64a:	e7cc      	b.n	800a5e6 <__ieee754_atan2f+0x26>
 800a64c:	2c02      	cmp	r4, #2
 800a64e:	d841      	bhi.n	800a6d4 <__ieee754_atan2f+0x114>
 800a650:	4b26      	ldr	r3, [pc, #152]	@ (800a6ec <__ieee754_atan2f+0x12c>)
 800a652:	e7f6      	b.n	800a642 <__ieee754_atan2f+0x82>
 800a654:	f1b3 4fff 	cmp.w	r3, #2139095040	@ 0x7f800000
 800a658:	d0df      	beq.n	800a61a <__ieee754_atan2f+0x5a>
 800a65a:	1a5b      	subs	r3, r3, r1
 800a65c:	f1b3 5ff4 	cmp.w	r3, #511705088	@ 0x1e800000
 800a660:	ea4f 51e3 	mov.w	r1, r3, asr #23
 800a664:	da1a      	bge.n	800a69c <__ieee754_atan2f+0xdc>
 800a666:	2a00      	cmp	r2, #0
 800a668:	da01      	bge.n	800a66e <__ieee754_atan2f+0xae>
 800a66a:	313c      	adds	r1, #60	@ 0x3c
 800a66c:	db19      	blt.n	800a6a2 <__ieee754_atan2f+0xe2>
 800a66e:	ee87 0aa0 	vdiv.f32	s0, s15, s1
 800a672:	f7ff fdbf 	bl	800a1f4 <fabsf>
 800a676:	f000 fc41 	bl	800aefc <atanf>
 800a67a:	eef0 7a40 	vmov.f32	s15, s0
 800a67e:	2c01      	cmp	r4, #1
 800a680:	d012      	beq.n	800a6a8 <__ieee754_atan2f+0xe8>
 800a682:	2c02      	cmp	r4, #2
 800a684:	d017      	beq.n	800a6b6 <__ieee754_atan2f+0xf6>
 800a686:	2c00      	cmp	r4, #0
 800a688:	d0ad      	beq.n	800a5e6 <__ieee754_atan2f+0x26>
 800a68a:	ed9f 7a19 	vldr	s14, [pc, #100]	@ 800a6f0 <__ieee754_atan2f+0x130>
 800a68e:	ee77 7a87 	vadd.f32	s15, s15, s14
 800a692:	ed9f 7a18 	vldr	s14, [pc, #96]	@ 800a6f4 <__ieee754_atan2f+0x134>
 800a696:	ee77 7ac7 	vsub.f32	s15, s15, s14
 800a69a:	e7a4      	b.n	800a5e6 <__ieee754_atan2f+0x26>
 800a69c:	eddf 7a11 	vldr	s15, [pc, #68]	@ 800a6e4 <__ieee754_atan2f+0x124>
 800a6a0:	e7ed      	b.n	800a67e <__ieee754_atan2f+0xbe>
 800a6a2:	eddf 7a15 	vldr	s15, [pc, #84]	@ 800a6f8 <__ieee754_atan2f+0x138>
 800a6a6:	e7ea      	b.n	800a67e <__ieee754_atan2f+0xbe>
 800a6a8:	ee17 3a90 	vmov	r3, s15
 800a6ac:	f103 4300 	add.w	r3, r3, #2147483648	@ 0x80000000
 800a6b0:	ee07 3a90 	vmov	s15, r3
 800a6b4:	e797      	b.n	800a5e6 <__ieee754_atan2f+0x26>
 800a6b6:	ed9f 7a0e 	vldr	s14, [pc, #56]	@ 800a6f0 <__ieee754_atan2f+0x130>
 800a6ba:	ee77 7a87 	vadd.f32	s15, s15, s14
 800a6be:	ed9f 7a0d 	vldr	s14, [pc, #52]	@ 800a6f4 <__ieee754_atan2f+0x134>
 800a6c2:	ee77 7a67 	vsub.f32	s15, s14, s15
 800a6c6:	e78e      	b.n	800a5e6 <__ieee754_atan2f+0x26>
 800a6c8:	eddf 7a0a 	vldr	s15, [pc, #40]	@ 800a6f4 <__ieee754_atan2f+0x134>
 800a6cc:	e78b      	b.n	800a5e6 <__ieee754_atan2f+0x26>
 800a6ce:	eddf 7a0b 	vldr	s15, [pc, #44]	@ 800a6fc <__ieee754_atan2f+0x13c>
 800a6d2:	e788      	b.n	800a5e6 <__ieee754_atan2f+0x26>
 800a6d4:	eddf 7a08 	vldr	s15, [pc, #32]	@ 800a6f8 <__ieee754_atan2f+0x138>
 800a6d8:	e785      	b.n	800a5e6 <__ieee754_atan2f+0x26>
 800a6da:	bf00      	nop
 800a6dc:	c0490fdb 	.word	0xc0490fdb
 800a6e0:	bfc90fdb 	.word	0xbfc90fdb
 800a6e4:	3fc90fdb 	.word	0x3fc90fdb
 800a6e8:	0800bcc0 	.word	0x0800bcc0
 800a6ec:	0800bcb4 	.word	0x0800bcb4
 800a6f0:	33bbbd2e 	.word	0x33bbbd2e
 800a6f4:	40490fdb 	.word	0x40490fdb
 800a6f8:	00000000 	.word	0x00000000
 800a6fc:	3f490fdb 	.word	0x3f490fdb

0800a700 <__ieee754_powf>:
 800a700:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 800a704:	ee10 4a90 	vmov	r4, s1
 800a708:	f034 4900 	bics.w	r9, r4, #2147483648	@ 0x80000000
 800a70c:	ed2d 8b02 	vpush	{d8}
 800a710:	ee10 6a10 	vmov	r6, s0
 800a714:	eeb0 8a40 	vmov.f32	s16, s0
 800a718:	eef0 8a60 	vmov.f32	s17, s1
 800a71c:	d10c      	bne.n	800a738 <__ieee754_powf+0x38>
 800a71e:	f486 0680 	eor.w	r6, r6, #4194304	@ 0x400000
 800a722:	0076      	lsls	r6, r6, #1
 800a724:	f516 0f00 	cmn.w	r6, #8388608	@ 0x800000
 800a728:	f240 8274 	bls.w	800ac14 <__ieee754_powf+0x514>
 800a72c:	ee38 0a28 	vadd.f32	s0, s16, s17
 800a730:	ecbd 8b02 	vpop	{d8}
 800a734:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 800a738:	f026 4800 	bic.w	r8, r6, #2147483648	@ 0x80000000
 800a73c:	f1b8 4fff 	cmp.w	r8, #2139095040	@ 0x7f800000
 800a740:	d802      	bhi.n	800a748 <__ieee754_powf+0x48>
 800a742:	f1b9 4fff 	cmp.w	r9, #2139095040	@ 0x7f800000
 800a746:	d908      	bls.n	800a75a <__ieee754_powf+0x5a>
 800a748:	f1b6 5f7e 	cmp.w	r6, #1065353216	@ 0x3f800000
 800a74c:	d1ee      	bne.n	800a72c <__ieee754_powf+0x2c>
 800a74e:	f484 0480 	eor.w	r4, r4, #4194304	@ 0x400000
 800a752:	0064      	lsls	r4, r4, #1
 800a754:	f514 0f00 	cmn.w	r4, #8388608	@ 0x800000
 800a758:	e7e6      	b.n	800a728 <__ieee754_powf+0x28>
 800a75a:	2e00      	cmp	r6, #0
 800a75c:	da1f      	bge.n	800a79e <__ieee754_powf+0x9e>
 800a75e:	f1b9 4f97 	cmp.w	r9, #1266679808	@ 0x4b800000
 800a762:	f080 8260 	bcs.w	800ac26 <__ieee754_powf+0x526>
 800a766:	f1b9 5f7e 	cmp.w	r9, #1065353216	@ 0x3f800000
 800a76a:	d32f      	bcc.n	800a7cc <__ieee754_powf+0xcc>
 800a76c:	ea4f 53e9 	mov.w	r3, r9, asr #23
 800a770:	f1c3 0396 	rsb	r3, r3, #150	@ 0x96
 800a774:	fa49 f503 	asr.w	r5, r9, r3
 800a778:	fa05 f303 	lsl.w	r3, r5, r3
 800a77c:	454b      	cmp	r3, r9
 800a77e:	d123      	bne.n	800a7c8 <__ieee754_powf+0xc8>
 800a780:	f005 0501 	and.w	r5, r5, #1
 800a784:	f1c5 0502 	rsb	r5, r5, #2
 800a788:	f1b9 5f7e 	cmp.w	r9, #1065353216	@ 0x3f800000
 800a78c:	d11f      	bne.n	800a7ce <__ieee754_powf+0xce>
 800a78e:	2c00      	cmp	r4, #0
 800a790:	f280 8246 	bge.w	800ac20 <__ieee754_powf+0x520>
 800a794:	eef7 7a00 	vmov.f32	s15, #112	@ 0x3f800000  1.0
 800a798:	ee87 0a88 	vdiv.f32	s0, s15, s16
 800a79c:	e7c8      	b.n	800a730 <__ieee754_powf+0x30>
 800a79e:	f1b9 4fff 	cmp.w	r9, #2139095040	@ 0x7f800000
 800a7a2:	d111      	bne.n	800a7c8 <__ieee754_powf+0xc8>
 800a7a4:	f1b8 5f7e 	cmp.w	r8, #1065353216	@ 0x3f800000
 800a7a8:	f000 8234 	beq.w	800ac14 <__ieee754_powf+0x514>
 800a7ac:	d906      	bls.n	800a7bc <__ieee754_powf+0xbc>
 800a7ae:	ed9f 0ac5 	vldr	s0, [pc, #788]	@ 800aac4 <__ieee754_powf+0x3c4>
 800a7b2:	2c00      	cmp	r4, #0
 800a7b4:	bfa8      	it	ge
 800a7b6:	eeb0 0a68 	vmovge.f32	s0, s17
 800a7ba:	e7b9      	b.n	800a730 <__ieee754_powf+0x30>
 800a7bc:	2c00      	cmp	r4, #0
 800a7be:	f280 822c 	bge.w	800ac1a <__ieee754_powf+0x51a>
 800a7c2:	eeb1 0a68 	vneg.f32	s0, s17
 800a7c6:	e7b3      	b.n	800a730 <__ieee754_powf+0x30>
 800a7c8:	2500      	movs	r5, #0
 800a7ca:	e7dd      	b.n	800a788 <__ieee754_powf+0x88>
 800a7cc:	2500      	movs	r5, #0
 800a7ce:	f1b4 4f80 	cmp.w	r4, #1073741824	@ 0x40000000
 800a7d2:	d102      	bne.n	800a7da <__ieee754_powf+0xda>
 800a7d4:	ee28 0a08 	vmul.f32	s0, s16, s16
 800a7d8:	e7aa      	b.n	800a730 <__ieee754_powf+0x30>
 800a7da:	f1b4 5f7c 	cmp.w	r4, #1056964608	@ 0x3f000000
 800a7de:	f040 8227 	bne.w	800ac30 <__ieee754_powf+0x530>
 800a7e2:	2e00      	cmp	r6, #0
 800a7e4:	f2c0 8224 	blt.w	800ac30 <__ieee754_powf+0x530>
 800a7e8:	eeb0 0a48 	vmov.f32	s0, s16
 800a7ec:	ecbd 8b02 	vpop	{d8}
 800a7f0:	e8bd 43f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 800a7f4:	f7ff bd5c 	b.w	800a2b0 <__ieee754_sqrtf>
 800a7f8:	2d01      	cmp	r5, #1
 800a7fa:	d199      	bne.n	800a730 <__ieee754_powf+0x30>
 800a7fc:	eeb1 0a40 	vneg.f32	s0, s0
 800a800:	e796      	b.n	800a730 <__ieee754_powf+0x30>
 800a802:	0ff0      	lsrs	r0, r6, #31
 800a804:	3801      	subs	r0, #1
 800a806:	ea55 0300 	orrs.w	r3, r5, r0
 800a80a:	d104      	bne.n	800a816 <__ieee754_powf+0x116>
 800a80c:	ee38 8a48 	vsub.f32	s16, s16, s16
 800a810:	ee88 0a08 	vdiv.f32	s0, s16, s16
 800a814:	e78c      	b.n	800a730 <__ieee754_powf+0x30>
 800a816:	f1b9 4f9a 	cmp.w	r9, #1291845632	@ 0x4d000000
 800a81a:	d96d      	bls.n	800a8f8 <__ieee754_powf+0x1f8>
 800a81c:	4baa      	ldr	r3, [pc, #680]	@ (800aac8 <__ieee754_powf+0x3c8>)
 800a81e:	4598      	cmp	r8, r3
 800a820:	d808      	bhi.n	800a834 <__ieee754_powf+0x134>
 800a822:	2c00      	cmp	r4, #0
 800a824:	da0b      	bge.n	800a83e <__ieee754_powf+0x13e>
 800a826:	2000      	movs	r0, #0
 800a828:	ecbd 8b02 	vpop	{d8}
 800a82c:	e8bd 43f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 800a830:	f000 bcbe 	b.w	800b1b0 <__math_oflowf>
 800a834:	4ba5      	ldr	r3, [pc, #660]	@ (800aacc <__ieee754_powf+0x3cc>)
 800a836:	4598      	cmp	r8, r3
 800a838:	d908      	bls.n	800a84c <__ieee754_powf+0x14c>
 800a83a:	2c00      	cmp	r4, #0
 800a83c:	dcf3      	bgt.n	800a826 <__ieee754_powf+0x126>
 800a83e:	2000      	movs	r0, #0
 800a840:	ecbd 8b02 	vpop	{d8}
 800a844:	e8bd 43f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 800a848:	f000 bcac 	b.w	800b1a4 <__math_uflowf>
 800a84c:	eef7 7a00 	vmov.f32	s15, #112	@ 0x3f800000  1.0
 800a850:	ee30 0a67 	vsub.f32	s0, s0, s15
 800a854:	eddf 6a9e 	vldr	s13, [pc, #632]	@ 800aad0 <__ieee754_powf+0x3d0>
 800a858:	eef5 7a00 	vmov.f32	s15, #80	@ 0x3e800000  0.250
 800a85c:	eee0 6a67 	vfms.f32	s13, s0, s15
 800a860:	eef6 7a00 	vmov.f32	s15, #96	@ 0x3f000000  0.5
 800a864:	eee6 7ac0 	vfms.f32	s15, s13, s0
 800a868:	ee20 7a00 	vmul.f32	s14, s0, s0
 800a86c:	eddf 6a99 	vldr	s13, [pc, #612]	@ 800aad4 <__ieee754_powf+0x3d4>
 800a870:	ee27 7a27 	vmul.f32	s14, s14, s15
 800a874:	eddf 7a98 	vldr	s15, [pc, #608]	@ 800aad8 <__ieee754_powf+0x3d8>
 800a878:	ee67 7ac7 	vnmul.f32	s15, s15, s14
 800a87c:	ed9f 7a97 	vldr	s14, [pc, #604]	@ 800aadc <__ieee754_powf+0x3dc>
 800a880:	eee0 7a07 	vfma.f32	s15, s0, s14
 800a884:	eeb0 7a67 	vmov.f32	s14, s15
 800a888:	eea0 7a26 	vfma.f32	s14, s0, s13
 800a88c:	ee17 3a10 	vmov	r3, s14
 800a890:	f36f 030b 	bfc	r3, #0, #12
 800a894:	ee07 3a10 	vmov	s14, r3
 800a898:	eeb0 6a47 	vmov.f32	s12, s14
 800a89c:	eea0 6a66 	vfms.f32	s12, s0, s13
 800a8a0:	ee77 7ac6 	vsub.f32	s15, s15, s12
 800a8a4:	3d01      	subs	r5, #1
 800a8a6:	4305      	orrs	r5, r0
 800a8a8:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800a8ac:	eebf 8a00 	vmov.f32	s16, #240	@ 0xbf800000 -1.0
 800a8b0:	f36f 040b 	bfc	r4, #0, #12
 800a8b4:	bf18      	it	ne
 800a8b6:	eeb0 8a66 	vmovne.f32	s16, s13
 800a8ba:	ee06 4a90 	vmov	s13, r4
 800a8be:	ee67 0aa8 	vmul.f32	s1, s15, s17
 800a8c2:	ee38 6ae6 	vsub.f32	s12, s17, s13
 800a8c6:	ee67 7a26 	vmul.f32	s15, s14, s13
 800a8ca:	eee6 0a07 	vfma.f32	s1, s12, s14
 800a8ce:	ee30 7aa7 	vadd.f32	s14, s1, s15
 800a8d2:	ee17 1a10 	vmov	r1, s14
 800a8d6:	2900      	cmp	r1, #0
 800a8d8:	f021 4300 	bic.w	r3, r1, #2147483648	@ 0x80000000
 800a8dc:	f340 80dd 	ble.w	800aa9a <__ieee754_powf+0x39a>
 800a8e0:	f1b3 4f86 	cmp.w	r3, #1124073472	@ 0x43000000
 800a8e4:	f240 80ca 	bls.w	800aa7c <__ieee754_powf+0x37c>
 800a8e8:	eeb5 8ac0 	vcmpe.f32	s16, #0.0
 800a8ec:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800a8f0:	bf4c      	ite	mi
 800a8f2:	2001      	movmi	r0, #1
 800a8f4:	2000      	movpl	r0, #0
 800a8f6:	e797      	b.n	800a828 <__ieee754_powf+0x128>
 800a8f8:	f016 4fff 	tst.w	r6, #2139095040	@ 0x7f800000
 800a8fc:	bf01      	itttt	eq
 800a8fe:	eddf 7a78 	vldreq	s15, [pc, #480]	@ 800aae0 <__ieee754_powf+0x3e0>
 800a902:	ee60 7a27 	vmuleq.f32	s15, s0, s15
 800a906:	f06f 0317 	mvneq.w	r3, #23
 800a90a:	ee17 7a90 	vmoveq	r7, s15
 800a90e:	ea4f 52e7 	mov.w	r2, r7, asr #23
 800a912:	bf18      	it	ne
 800a914:	2300      	movne	r3, #0
 800a916:	3a7f      	subs	r2, #127	@ 0x7f
 800a918:	441a      	add	r2, r3
 800a91a:	4b72      	ldr	r3, [pc, #456]	@ (800aae4 <__ieee754_powf+0x3e4>)
 800a91c:	f3c7 0716 	ubfx	r7, r7, #0, #23
 800a920:	429f      	cmp	r7, r3
 800a922:	f047 517e 	orr.w	r1, r7, #1065353216	@ 0x3f800000
 800a926:	dd06      	ble.n	800a936 <__ieee754_powf+0x236>
 800a928:	4b6f      	ldr	r3, [pc, #444]	@ (800aae8 <__ieee754_powf+0x3e8>)
 800a92a:	429f      	cmp	r7, r3
 800a92c:	f340 80a4 	ble.w	800aa78 <__ieee754_powf+0x378>
 800a930:	3201      	adds	r2, #1
 800a932:	f5a1 0100 	sub.w	r1, r1, #8388608	@ 0x800000
 800a936:	2600      	movs	r6, #0
 800a938:	4b6c      	ldr	r3, [pc, #432]	@ (800aaec <__ieee754_powf+0x3ec>)
 800a93a:	eb03 0386 	add.w	r3, r3, r6, lsl #2
 800a93e:	ee07 1a10 	vmov	s14, r1
 800a942:	edd3 5a00 	vldr	s11, [r3]
 800a946:	4b6a      	ldr	r3, [pc, #424]	@ (800aaf0 <__ieee754_powf+0x3f0>)
 800a948:	ee75 7a87 	vadd.f32	s15, s11, s14
 800a94c:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800a950:	eec6 4aa7 	vdiv.f32	s9, s13, s15
 800a954:	1049      	asrs	r1, r1, #1
 800a956:	f041 5100 	orr.w	r1, r1, #536870912	@ 0x20000000
 800a95a:	f501 2180 	add.w	r1, r1, #262144	@ 0x40000
 800a95e:	eb01 5146 	add.w	r1, r1, r6, lsl #21
 800a962:	ee37 6a65 	vsub.f32	s12, s14, s11
 800a966:	ee07 1a90 	vmov	s15, r1
 800a96a:	ee26 5a24 	vmul.f32	s10, s12, s9
 800a96e:	ee77 5ae5 	vsub.f32	s11, s15, s11
 800a972:	ee15 7a10 	vmov	r7, s10
 800a976:	401f      	ands	r7, r3
 800a978:	ee06 7a90 	vmov	s13, r7
 800a97c:	eea6 6ae7 	vfms.f32	s12, s13, s15
 800a980:	ee37 7a65 	vsub.f32	s14, s14, s11
 800a984:	ee65 7a05 	vmul.f32	s15, s10, s10
 800a988:	eea6 6ac7 	vfms.f32	s12, s13, s14
 800a98c:	eddf 5a59 	vldr	s11, [pc, #356]	@ 800aaf4 <__ieee754_powf+0x3f4>
 800a990:	ed9f 7a59 	vldr	s14, [pc, #356]	@ 800aaf8 <__ieee754_powf+0x3f8>
 800a994:	eee7 5a87 	vfma.f32	s11, s15, s14
 800a998:	ed9f 7a58 	vldr	s14, [pc, #352]	@ 800aafc <__ieee754_powf+0x3fc>
 800a99c:	eea5 7aa7 	vfma.f32	s14, s11, s15
 800a9a0:	eddf 5a4b 	vldr	s11, [pc, #300]	@ 800aad0 <__ieee754_powf+0x3d0>
 800a9a4:	eee7 5a27 	vfma.f32	s11, s14, s15
 800a9a8:	ed9f 7a55 	vldr	s14, [pc, #340]	@ 800ab00 <__ieee754_powf+0x400>
 800a9ac:	eea5 7aa7 	vfma.f32	s14, s11, s15
 800a9b0:	eddf 5a54 	vldr	s11, [pc, #336]	@ 800ab04 <__ieee754_powf+0x404>
 800a9b4:	ee26 6a24 	vmul.f32	s12, s12, s9
 800a9b8:	eee7 5a27 	vfma.f32	s11, s14, s15
 800a9bc:	ee35 7a26 	vadd.f32	s14, s10, s13
 800a9c0:	ee67 4aa7 	vmul.f32	s9, s15, s15
 800a9c4:	ee27 7a06 	vmul.f32	s14, s14, s12
 800a9c8:	eef0 7a08 	vmov.f32	s15, #8	@ 0x40400000  3.0
 800a9cc:	eea4 7aa5 	vfma.f32	s14, s9, s11
 800a9d0:	eef0 5a67 	vmov.f32	s11, s15
 800a9d4:	eee6 5aa6 	vfma.f32	s11, s13, s13
 800a9d8:	ee75 5a87 	vadd.f32	s11, s11, s14
 800a9dc:	ee15 1a90 	vmov	r1, s11
 800a9e0:	4019      	ands	r1, r3
 800a9e2:	ee05 1a90 	vmov	s11, r1
 800a9e6:	ee75 7ae7 	vsub.f32	s15, s11, s15
 800a9ea:	eee6 7ae6 	vfms.f32	s15, s13, s13
 800a9ee:	ee77 7a67 	vsub.f32	s15, s14, s15
 800a9f2:	ee67 7a85 	vmul.f32	s15, s15, s10
 800a9f6:	eee6 7a25 	vfma.f32	s15, s12, s11
 800a9fa:	eeb0 6a67 	vmov.f32	s12, s15
 800a9fe:	eea6 6aa5 	vfma.f32	s12, s13, s11
 800aa02:	ee16 1a10 	vmov	r1, s12
 800aa06:	4019      	ands	r1, r3
 800aa08:	ee06 1a10 	vmov	s12, r1
 800aa0c:	eeb0 7a46 	vmov.f32	s14, s12
 800aa10:	eea6 7ae5 	vfms.f32	s14, s13, s11
 800aa14:	493c      	ldr	r1, [pc, #240]	@ (800ab08 <__ieee754_powf+0x408>)
 800aa16:	eb01 0186 	add.w	r1, r1, r6, lsl #2
 800aa1a:	ee77 7ac7 	vsub.f32	s15, s15, s14
 800aa1e:	ed9f 7a3b 	vldr	s14, [pc, #236]	@ 800ab0c <__ieee754_powf+0x40c>
 800aa22:	eddf 5a3b 	vldr	s11, [pc, #236]	@ 800ab10 <__ieee754_powf+0x410>
 800aa26:	ee67 7a87 	vmul.f32	s15, s15, s14
 800aa2a:	ed9f 7a3a 	vldr	s14, [pc, #232]	@ 800ab14 <__ieee754_powf+0x414>
 800aa2e:	eee6 7a07 	vfma.f32	s15, s12, s14
 800aa32:	ed91 7a00 	vldr	s14, [r1]
 800aa36:	ee77 7a87 	vadd.f32	s15, s15, s14
 800aa3a:	ee07 2a10 	vmov	s14, r2
 800aa3e:	4a36      	ldr	r2, [pc, #216]	@ (800ab18 <__ieee754_powf+0x418>)
 800aa40:	eef8 6ac7 	vcvt.f32.s32	s13, s14
 800aa44:	eeb0 7a67 	vmov.f32	s14, s15
 800aa48:	eea6 7a25 	vfma.f32	s14, s12, s11
 800aa4c:	eb02 0286 	add.w	r2, r2, r6, lsl #2
 800aa50:	ed92 5a00 	vldr	s10, [r2]
 800aa54:	ee37 7a05 	vadd.f32	s14, s14, s10
 800aa58:	ee37 7a26 	vadd.f32	s14, s14, s13
 800aa5c:	ee17 2a10 	vmov	r2, s14
 800aa60:	401a      	ands	r2, r3
 800aa62:	ee07 2a10 	vmov	s14, r2
 800aa66:	ee77 6a66 	vsub.f32	s13, s14, s13
 800aa6a:	ee76 6ac5 	vsub.f32	s13, s13, s10
 800aa6e:	eee6 6a65 	vfms.f32	s13, s12, s11
 800aa72:	ee77 7ae6 	vsub.f32	s15, s15, s13
 800aa76:	e715      	b.n	800a8a4 <__ieee754_powf+0x1a4>
 800aa78:	2601      	movs	r6, #1
 800aa7a:	e75d      	b.n	800a938 <__ieee754_powf+0x238>
 800aa7c:	d152      	bne.n	800ab24 <__ieee754_powf+0x424>
 800aa7e:	eddf 6a27 	vldr	s13, [pc, #156]	@ 800ab1c <__ieee754_powf+0x41c>
 800aa82:	ee37 7a67 	vsub.f32	s14, s14, s15
 800aa86:	ee70 6aa6 	vadd.f32	s13, s1, s13
 800aa8a:	eef4 6ac7 	vcmpe.f32	s13, s14
 800aa8e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800aa92:	f73f af29 	bgt.w	800a8e8 <__ieee754_powf+0x1e8>
 800aa96:	2386      	movs	r3, #134	@ 0x86
 800aa98:	e048      	b.n	800ab2c <__ieee754_powf+0x42c>
 800aa9a:	4a21      	ldr	r2, [pc, #132]	@ (800ab20 <__ieee754_powf+0x420>)
 800aa9c:	4293      	cmp	r3, r2
 800aa9e:	d907      	bls.n	800aab0 <__ieee754_powf+0x3b0>
 800aaa0:	eeb5 8ac0 	vcmpe.f32	s16, #0.0
 800aaa4:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800aaa8:	bf4c      	ite	mi
 800aaaa:	2001      	movmi	r0, #1
 800aaac:	2000      	movpl	r0, #0
 800aaae:	e6c7      	b.n	800a840 <__ieee754_powf+0x140>
 800aab0:	d138      	bne.n	800ab24 <__ieee754_powf+0x424>
 800aab2:	ee37 7a67 	vsub.f32	s14, s14, s15
 800aab6:	eeb4 7ae0 	vcmpe.f32	s14, s1
 800aaba:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800aabe:	dbea      	blt.n	800aa96 <__ieee754_powf+0x396>
 800aac0:	e7ee      	b.n	800aaa0 <__ieee754_powf+0x3a0>
 800aac2:	bf00      	nop
 800aac4:	00000000 	.word	0x00000000
 800aac8:	3f7ffff3 	.word	0x3f7ffff3
 800aacc:	3f800007 	.word	0x3f800007
 800aad0:	3eaaaaab 	.word	0x3eaaaaab
 800aad4:	3fb8aa00 	.word	0x3fb8aa00
 800aad8:	3fb8aa3b 	.word	0x3fb8aa3b
 800aadc:	36eca570 	.word	0x36eca570
 800aae0:	4b800000 	.word	0x4b800000
 800aae4:	001cc471 	.word	0x001cc471
 800aae8:	005db3d6 	.word	0x005db3d6
 800aaec:	0800bcdc 	.word	0x0800bcdc
 800aaf0:	fffff000 	.word	0xfffff000
 800aaf4:	3e6c3255 	.word	0x3e6c3255
 800aaf8:	3e53f142 	.word	0x3e53f142
 800aafc:	3e8ba305 	.word	0x3e8ba305
 800ab00:	3edb6db7 	.word	0x3edb6db7
 800ab04:	3f19999a 	.word	0x3f19999a
 800ab08:	0800bccc 	.word	0x0800bccc
 800ab0c:	3f76384f 	.word	0x3f76384f
 800ab10:	3f763800 	.word	0x3f763800
 800ab14:	369dc3a0 	.word	0x369dc3a0
 800ab18:	0800bcd4 	.word	0x0800bcd4
 800ab1c:	3338aa3c 	.word	0x3338aa3c
 800ab20:	43160000 	.word	0x43160000
 800ab24:	f1b3 5f7c 	cmp.w	r3, #1056964608	@ 0x3f000000
 800ab28:	d96f      	bls.n	800ac0a <__ieee754_powf+0x50a>
 800ab2a:	15db      	asrs	r3, r3, #23
 800ab2c:	3b7e      	subs	r3, #126	@ 0x7e
 800ab2e:	f44f 0000 	mov.w	r0, #8388608	@ 0x800000
 800ab32:	4118      	asrs	r0, r3
 800ab34:	4408      	add	r0, r1
 800ab36:	f3c0 53c7 	ubfx	r3, r0, #23, #8
 800ab3a:	4a4e      	ldr	r2, [pc, #312]	@ (800ac74 <__ieee754_powf+0x574>)
 800ab3c:	3b7f      	subs	r3, #127	@ 0x7f
 800ab3e:	411a      	asrs	r2, r3
 800ab40:	4002      	ands	r2, r0
 800ab42:	ee07 2a10 	vmov	s14, r2
 800ab46:	f3c0 0016 	ubfx	r0, r0, #0, #23
 800ab4a:	f440 0000 	orr.w	r0, r0, #8388608	@ 0x800000
 800ab4e:	f1c3 0317 	rsb	r3, r3, #23
 800ab52:	4118      	asrs	r0, r3
 800ab54:	2900      	cmp	r1, #0
 800ab56:	ee77 7ac7 	vsub.f32	s15, s15, s14
 800ab5a:	bfb8      	it	lt
 800ab5c:	4240      	neglt	r0, r0
 800ab5e:	ee77 6aa0 	vadd.f32	s13, s15, s1
 800ab62:	ed9f 7a45 	vldr	s14, [pc, #276]	@ 800ac78 <__ieee754_powf+0x578>
 800ab66:	ed9f 6a45 	vldr	s12, [pc, #276]	@ 800ac7c <__ieee754_powf+0x57c>
 800ab6a:	ee16 3a90 	vmov	r3, s13
 800ab6e:	f36f 030b 	bfc	r3, #0, #12
 800ab72:	ee06 3a90 	vmov	s13, r3
 800ab76:	ee76 7ae7 	vsub.f32	s15, s13, s15
 800ab7a:	eeb7 0a00 	vmov.f32	s0, #112	@ 0x3f800000  1.0
 800ab7e:	ee70 0ae7 	vsub.f32	s1, s1, s15
 800ab82:	eddf 7a3f 	vldr	s15, [pc, #252]	@ 800ac80 <__ieee754_powf+0x580>
 800ab86:	ee66 7aa7 	vmul.f32	s15, s13, s15
 800ab8a:	eee0 7a87 	vfma.f32	s15, s1, s14
 800ab8e:	eeb0 7a67 	vmov.f32	s14, s15
 800ab92:	eea6 7a86 	vfma.f32	s14, s13, s12
 800ab96:	eef0 5a47 	vmov.f32	s11, s14
 800ab9a:	eee6 5ac6 	vfms.f32	s11, s13, s12
 800ab9e:	ee67 6a07 	vmul.f32	s13, s14, s14
 800aba2:	ee77 7ae5 	vsub.f32	s15, s15, s11
 800aba6:	ed9f 6a37 	vldr	s12, [pc, #220]	@ 800ac84 <__ieee754_powf+0x584>
 800abaa:	eddf 5a37 	vldr	s11, [pc, #220]	@ 800ac88 <__ieee754_powf+0x588>
 800abae:	eea6 6aa5 	vfma.f32	s12, s13, s11
 800abb2:	eddf 5a36 	vldr	s11, [pc, #216]	@ 800ac8c <__ieee754_powf+0x58c>
 800abb6:	eee6 5a26 	vfma.f32	s11, s12, s13
 800abba:	ed9f 6a35 	vldr	s12, [pc, #212]	@ 800ac90 <__ieee754_powf+0x590>
 800abbe:	eea5 6aa6 	vfma.f32	s12, s11, s13
 800abc2:	eddf 5a34 	vldr	s11, [pc, #208]	@ 800ac94 <__ieee754_powf+0x594>
 800abc6:	eee6 5a26 	vfma.f32	s11, s12, s13
 800abca:	eeb0 6a47 	vmov.f32	s12, s14
 800abce:	eea5 6ae6 	vfms.f32	s12, s11, s13
 800abd2:	eef0 6a00 	vmov.f32	s13, #0	@ 0x40000000  2.0
 800abd6:	ee67 5a06 	vmul.f32	s11, s14, s12
 800abda:	ee36 6a66 	vsub.f32	s12, s12, s13
 800abde:	eee7 7a27 	vfma.f32	s15, s14, s15
 800abe2:	eec5 6a86 	vdiv.f32	s13, s11, s12
 800abe6:	ee76 7ae7 	vsub.f32	s15, s13, s15
 800abea:	ee77 7ac7 	vsub.f32	s15, s15, s14
 800abee:	ee30 0a67 	vsub.f32	s0, s0, s15
 800abf2:	ee10 3a10 	vmov	r3, s0
 800abf6:	eb03 53c0 	add.w	r3, r3, r0, lsl #23
 800abfa:	f5b3 0f00 	cmp.w	r3, #8388608	@ 0x800000
 800abfe:	da06      	bge.n	800ac0e <__ieee754_powf+0x50e>
 800ac00:	f000 fa50 	bl	800b0a4 <scalbnf>
 800ac04:	ee20 0a08 	vmul.f32	s0, s0, s16
 800ac08:	e592      	b.n	800a730 <__ieee754_powf+0x30>
 800ac0a:	2000      	movs	r0, #0
 800ac0c:	e7a7      	b.n	800ab5e <__ieee754_powf+0x45e>
 800ac0e:	ee00 3a10 	vmov	s0, r3
 800ac12:	e7f7      	b.n	800ac04 <__ieee754_powf+0x504>
 800ac14:	eeb7 0a00 	vmov.f32	s0, #112	@ 0x3f800000  1.0
 800ac18:	e58a      	b.n	800a730 <__ieee754_powf+0x30>
 800ac1a:	ed9f 0a1f 	vldr	s0, [pc, #124]	@ 800ac98 <__ieee754_powf+0x598>
 800ac1e:	e587      	b.n	800a730 <__ieee754_powf+0x30>
 800ac20:	eeb0 0a48 	vmov.f32	s0, s16
 800ac24:	e584      	b.n	800a730 <__ieee754_powf+0x30>
 800ac26:	f1b9 4fff 	cmp.w	r9, #2139095040	@ 0x7f800000
 800ac2a:	f43f adbb 	beq.w	800a7a4 <__ieee754_powf+0xa4>
 800ac2e:	2502      	movs	r5, #2
 800ac30:	eeb0 0a48 	vmov.f32	s0, s16
 800ac34:	f7ff fade 	bl	800a1f4 <fabsf>
 800ac38:	f026 4340 	bic.w	r3, r6, #3221225472	@ 0xc0000000
 800ac3c:	f1b3 5f7e 	cmp.w	r3, #1065353216	@ 0x3f800000
 800ac40:	4647      	mov	r7, r8
 800ac42:	d003      	beq.n	800ac4c <__ieee754_powf+0x54c>
 800ac44:	f1b8 0f00 	cmp.w	r8, #0
 800ac48:	f47f addb 	bne.w	800a802 <__ieee754_powf+0x102>
 800ac4c:	2c00      	cmp	r4, #0
 800ac4e:	bfbc      	itt	lt
 800ac50:	eef7 7a00 	vmovlt.f32	s15, #112	@ 0x3f800000  1.0
 800ac54:	ee87 0a80 	vdivlt.f32	s0, s15, s0
 800ac58:	2e00      	cmp	r6, #0
 800ac5a:	f6bf ad69 	bge.w	800a730 <__ieee754_powf+0x30>
 800ac5e:	f1a8 587e 	sub.w	r8, r8, #1065353216	@ 0x3f800000
 800ac62:	ea58 0805 	orrs.w	r8, r8, r5
 800ac66:	f47f adc7 	bne.w	800a7f8 <__ieee754_powf+0xf8>
 800ac6a:	ee70 7a40 	vsub.f32	s15, s0, s0
 800ac6e:	ee87 0aa7 	vdiv.f32	s0, s15, s15
 800ac72:	e55d      	b.n	800a730 <__ieee754_powf+0x30>
 800ac74:	ff800000 	.word	0xff800000
 800ac78:	3f317218 	.word	0x3f317218
 800ac7c:	3f317200 	.word	0x3f317200
 800ac80:	35bfbe8c 	.word	0x35bfbe8c
 800ac84:	b5ddea0e 	.word	0xb5ddea0e
 800ac88:	3331bb4c 	.word	0x3331bb4c
 800ac8c:	388ab355 	.word	0x388ab355
 800ac90:	bb360b61 	.word	0xbb360b61
 800ac94:	3e2aaaab 	.word	0x3e2aaaab
 800ac98:	00000000 	.word	0x00000000

0800ac9c <__ieee754_rem_pio2f>:
 800ac9c:	b5f0      	push	{r4, r5, r6, r7, lr}
 800ac9e:	ee10 6a10 	vmov	r6, s0
 800aca2:	4b88      	ldr	r3, [pc, #544]	@ (800aec4 <__ieee754_rem_pio2f+0x228>)
 800aca4:	f026 4500 	bic.w	r5, r6, #2147483648	@ 0x80000000
 800aca8:	429d      	cmp	r5, r3
 800acaa:	b087      	sub	sp, #28
 800acac:	4604      	mov	r4, r0
 800acae:	d805      	bhi.n	800acbc <__ieee754_rem_pio2f+0x20>
 800acb0:	2300      	movs	r3, #0
 800acb2:	ed80 0a00 	vstr	s0, [r0]
 800acb6:	6043      	str	r3, [r0, #4]
 800acb8:	2000      	movs	r0, #0
 800acba:	e022      	b.n	800ad02 <__ieee754_rem_pio2f+0x66>
 800acbc:	4b82      	ldr	r3, [pc, #520]	@ (800aec8 <__ieee754_rem_pio2f+0x22c>)
 800acbe:	429d      	cmp	r5, r3
 800acc0:	d83a      	bhi.n	800ad38 <__ieee754_rem_pio2f+0x9c>
 800acc2:	f026 4300 	bic.w	r3, r6, #2147483648	@ 0x80000000
 800acc6:	2e00      	cmp	r6, #0
 800acc8:	ed9f 7a80 	vldr	s14, [pc, #512]	@ 800aecc <__ieee754_rem_pio2f+0x230>
 800accc:	4a80      	ldr	r2, [pc, #512]	@ (800aed0 <__ieee754_rem_pio2f+0x234>)
 800acce:	f023 030f 	bic.w	r3, r3, #15
 800acd2:	dd18      	ble.n	800ad06 <__ieee754_rem_pio2f+0x6a>
 800acd4:	4293      	cmp	r3, r2
 800acd6:	ee70 7a47 	vsub.f32	s15, s0, s14
 800acda:	bf09      	itett	eq
 800acdc:	ed9f 7a7d 	vldreq	s14, [pc, #500]	@ 800aed4 <__ieee754_rem_pio2f+0x238>
 800ace0:	eddf 6a7d 	vldrne	s13, [pc, #500]	@ 800aed8 <__ieee754_rem_pio2f+0x23c>
 800ace4:	eddf 6a7d 	vldreq	s13, [pc, #500]	@ 800aedc <__ieee754_rem_pio2f+0x240>
 800ace8:	ee77 7ac7 	vsubeq.f32	s15, s15, s14
 800acec:	ee37 7ae6 	vsub.f32	s14, s15, s13
 800acf0:	ee77 7ac7 	vsub.f32	s15, s15, s14
 800acf4:	ed80 7a00 	vstr	s14, [r0]
 800acf8:	ee77 7ae6 	vsub.f32	s15, s15, s13
 800acfc:	edc0 7a01 	vstr	s15, [r0, #4]
 800ad00:	2001      	movs	r0, #1
 800ad02:	b007      	add	sp, #28
 800ad04:	bdf0      	pop	{r4, r5, r6, r7, pc}
 800ad06:	4293      	cmp	r3, r2
 800ad08:	ee70 7a07 	vadd.f32	s15, s0, s14
 800ad0c:	bf09      	itett	eq
 800ad0e:	ed9f 7a71 	vldreq	s14, [pc, #452]	@ 800aed4 <__ieee754_rem_pio2f+0x238>
 800ad12:	eddf 6a71 	vldrne	s13, [pc, #452]	@ 800aed8 <__ieee754_rem_pio2f+0x23c>
 800ad16:	eddf 6a71 	vldreq	s13, [pc, #452]	@ 800aedc <__ieee754_rem_pio2f+0x240>
 800ad1a:	ee77 7a87 	vaddeq.f32	s15, s15, s14
 800ad1e:	ee37 7aa6 	vadd.f32	s14, s15, s13
 800ad22:	ee77 7ac7 	vsub.f32	s15, s15, s14
 800ad26:	ed80 7a00 	vstr	s14, [r0]
 800ad2a:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800ad2e:	edc0 7a01 	vstr	s15, [r0, #4]
 800ad32:	f04f 30ff 	mov.w	r0, #4294967295
 800ad36:	e7e4      	b.n	800ad02 <__ieee754_rem_pio2f+0x66>
 800ad38:	4b69      	ldr	r3, [pc, #420]	@ (800aee0 <__ieee754_rem_pio2f+0x244>)
 800ad3a:	429d      	cmp	r5, r3
 800ad3c:	d873      	bhi.n	800ae26 <__ieee754_rem_pio2f+0x18a>
 800ad3e:	f7ff fa59 	bl	800a1f4 <fabsf>
 800ad42:	ed9f 7a68 	vldr	s14, [pc, #416]	@ 800aee4 <__ieee754_rem_pio2f+0x248>
 800ad46:	eef6 7a00 	vmov.f32	s15, #96	@ 0x3f000000  0.5
 800ad4a:	eee0 7a07 	vfma.f32	s15, s0, s14
 800ad4e:	eefd 7ae7 	vcvt.s32.f32	s15, s15
 800ad52:	eeb8 7ae7 	vcvt.f32.s32	s14, s15
 800ad56:	ee17 0a90 	vmov	r0, s15
 800ad5a:	eddf 7a5c 	vldr	s15, [pc, #368]	@ 800aecc <__ieee754_rem_pio2f+0x230>
 800ad5e:	eea7 0a67 	vfms.f32	s0, s14, s15
 800ad62:	281f      	cmp	r0, #31
 800ad64:	eddf 7a5c 	vldr	s15, [pc, #368]	@ 800aed8 <__ieee754_rem_pio2f+0x23c>
 800ad68:	ee67 7a27 	vmul.f32	s15, s14, s15
 800ad6c:	eeb1 6a47 	vneg.f32	s12, s14
 800ad70:	ee70 6a67 	vsub.f32	s13, s0, s15
 800ad74:	ee16 1a90 	vmov	r1, s13
 800ad78:	dc09      	bgt.n	800ad8e <__ieee754_rem_pio2f+0xf2>
 800ad7a:	4a5b      	ldr	r2, [pc, #364]	@ (800aee8 <__ieee754_rem_pio2f+0x24c>)
 800ad7c:	1e47      	subs	r7, r0, #1
 800ad7e:	f026 4300 	bic.w	r3, r6, #2147483648	@ 0x80000000
 800ad82:	f852 2027 	ldr.w	r2, [r2, r7, lsl #2]
 800ad86:	f023 03ff 	bic.w	r3, r3, #255	@ 0xff
 800ad8a:	4293      	cmp	r3, r2
 800ad8c:	d107      	bne.n	800ad9e <__ieee754_rem_pio2f+0x102>
 800ad8e:	f3c1 52c7 	ubfx	r2, r1, #23, #8
 800ad92:	ebc2 52d5 	rsb	r2, r2, r5, lsr #23
 800ad96:	2a08      	cmp	r2, #8
 800ad98:	ea4f 53e5 	mov.w	r3, r5, asr #23
 800ad9c:	dc14      	bgt.n	800adc8 <__ieee754_rem_pio2f+0x12c>
 800ad9e:	6021      	str	r1, [r4, #0]
 800ada0:	ed94 7a00 	vldr	s14, [r4]
 800ada4:	ee30 0a47 	vsub.f32	s0, s0, s14
 800ada8:	2e00      	cmp	r6, #0
 800adaa:	ee30 0a67 	vsub.f32	s0, s0, s15
 800adae:	ed84 0a01 	vstr	s0, [r4, #4]
 800adb2:	daa6      	bge.n	800ad02 <__ieee754_rem_pio2f+0x66>
 800adb4:	eeb1 7a47 	vneg.f32	s14, s14
 800adb8:	eeb1 0a40 	vneg.f32	s0, s0
 800adbc:	ed84 7a00 	vstr	s14, [r4]
 800adc0:	ed84 0a01 	vstr	s0, [r4, #4]
 800adc4:	4240      	negs	r0, r0
 800adc6:	e79c      	b.n	800ad02 <__ieee754_rem_pio2f+0x66>
 800adc8:	eddf 5a42 	vldr	s11, [pc, #264]	@ 800aed4 <__ieee754_rem_pio2f+0x238>
 800adcc:	eef0 6a40 	vmov.f32	s13, s0
 800add0:	eee6 6a25 	vfma.f32	s13, s12, s11
 800add4:	ee70 7a66 	vsub.f32	s15, s0, s13
 800add8:	eee6 7a25 	vfma.f32	s15, s12, s11
 800addc:	eddf 5a3f 	vldr	s11, [pc, #252]	@ 800aedc <__ieee754_rem_pio2f+0x240>
 800ade0:	eed7 7a25 	vfnms.f32	s15, s14, s11
 800ade4:	ee76 5ae7 	vsub.f32	s11, s13, s15
 800ade8:	ee15 2a90 	vmov	r2, s11
 800adec:	f3c2 51c7 	ubfx	r1, r2, #23, #8
 800adf0:	1a5b      	subs	r3, r3, r1
 800adf2:	2b19      	cmp	r3, #25
 800adf4:	dc04      	bgt.n	800ae00 <__ieee754_rem_pio2f+0x164>
 800adf6:	edc4 5a00 	vstr	s11, [r4]
 800adfa:	eeb0 0a66 	vmov.f32	s0, s13
 800adfe:	e7cf      	b.n	800ada0 <__ieee754_rem_pio2f+0x104>
 800ae00:	eddf 5a3a 	vldr	s11, [pc, #232]	@ 800aeec <__ieee754_rem_pio2f+0x250>
 800ae04:	eeb0 0a66 	vmov.f32	s0, s13
 800ae08:	eea6 0a25 	vfma.f32	s0, s12, s11
 800ae0c:	ee76 7ac0 	vsub.f32	s15, s13, s0
 800ae10:	eddf 6a37 	vldr	s13, [pc, #220]	@ 800aef0 <__ieee754_rem_pio2f+0x254>
 800ae14:	eee6 7a25 	vfma.f32	s15, s12, s11
 800ae18:	eed7 7a26 	vfnms.f32	s15, s14, s13
 800ae1c:	ee30 7a67 	vsub.f32	s14, s0, s15
 800ae20:	ed84 7a00 	vstr	s14, [r4]
 800ae24:	e7bc      	b.n	800ada0 <__ieee754_rem_pio2f+0x104>
 800ae26:	f1b5 4fff 	cmp.w	r5, #2139095040	@ 0x7f800000
 800ae2a:	d306      	bcc.n	800ae3a <__ieee754_rem_pio2f+0x19e>
 800ae2c:	ee70 7a40 	vsub.f32	s15, s0, s0
 800ae30:	edc0 7a01 	vstr	s15, [r0, #4]
 800ae34:	edc0 7a00 	vstr	s15, [r0]
 800ae38:	e73e      	b.n	800acb8 <__ieee754_rem_pio2f+0x1c>
 800ae3a:	15ea      	asrs	r2, r5, #23
 800ae3c:	3a86      	subs	r2, #134	@ 0x86
 800ae3e:	eba5 53c2 	sub.w	r3, r5, r2, lsl #23
 800ae42:	ee07 3a90 	vmov	s15, r3
 800ae46:	eebd 7ae7 	vcvt.s32.f32	s14, s15
 800ae4a:	eddf 6a2a 	vldr	s13, [pc, #168]	@ 800aef4 <__ieee754_rem_pio2f+0x258>
 800ae4e:	eeb8 7ac7 	vcvt.f32.s32	s14, s14
 800ae52:	ee77 7ac7 	vsub.f32	s15, s15, s14
 800ae56:	ed8d 7a03 	vstr	s14, [sp, #12]
 800ae5a:	ee67 7aa6 	vmul.f32	s15, s15, s13
 800ae5e:	eebd 7ae7 	vcvt.s32.f32	s14, s15
 800ae62:	eeb8 7ac7 	vcvt.f32.s32	s14, s14
 800ae66:	ee77 7ac7 	vsub.f32	s15, s15, s14
 800ae6a:	ed8d 7a04 	vstr	s14, [sp, #16]
 800ae6e:	ee67 7aa6 	vmul.f32	s15, s15, s13
 800ae72:	eef5 7a40 	vcmp.f32	s15, #0.0
 800ae76:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800ae7a:	edcd 7a05 	vstr	s15, [sp, #20]
 800ae7e:	d11e      	bne.n	800aebe <__ieee754_rem_pio2f+0x222>
 800ae80:	eeb5 7a40 	vcmp.f32	s14, #0.0
 800ae84:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800ae88:	bf0c      	ite	eq
 800ae8a:	2301      	moveq	r3, #1
 800ae8c:	2302      	movne	r3, #2
 800ae8e:	491a      	ldr	r1, [pc, #104]	@ (800aef8 <__ieee754_rem_pio2f+0x25c>)
 800ae90:	9101      	str	r1, [sp, #4]
 800ae92:	2102      	movs	r1, #2
 800ae94:	9100      	str	r1, [sp, #0]
 800ae96:	a803      	add	r0, sp, #12
 800ae98:	4621      	mov	r1, r4
 800ae9a:	f000 f98f 	bl	800b1bc <__kernel_rem_pio2f>
 800ae9e:	2e00      	cmp	r6, #0
 800aea0:	f6bf af2f 	bge.w	800ad02 <__ieee754_rem_pio2f+0x66>
 800aea4:	edd4 7a00 	vldr	s15, [r4]
 800aea8:	eef1 7a67 	vneg.f32	s15, s15
 800aeac:	edc4 7a00 	vstr	s15, [r4]
 800aeb0:	edd4 7a01 	vldr	s15, [r4, #4]
 800aeb4:	eef1 7a67 	vneg.f32	s15, s15
 800aeb8:	edc4 7a01 	vstr	s15, [r4, #4]
 800aebc:	e782      	b.n	800adc4 <__ieee754_rem_pio2f+0x128>
 800aebe:	2303      	movs	r3, #3
 800aec0:	e7e5      	b.n	800ae8e <__ieee754_rem_pio2f+0x1f2>
 800aec2:	bf00      	nop
 800aec4:	3f490fd8 	.word	0x3f490fd8
 800aec8:	4016cbe3 	.word	0x4016cbe3
 800aecc:	3fc90f80 	.word	0x3fc90f80
 800aed0:	3fc90fd0 	.word	0x3fc90fd0
 800aed4:	37354400 	.word	0x37354400
 800aed8:	37354443 	.word	0x37354443
 800aedc:	2e85a308 	.word	0x2e85a308
 800aee0:	43490f80 	.word	0x43490f80
 800aee4:	3f22f984 	.word	0x3f22f984
 800aee8:	0800bce4 	.word	0x0800bce4
 800aeec:	2e85a300 	.word	0x2e85a300
 800aef0:	248d3132 	.word	0x248d3132
 800aef4:	43800000 	.word	0x43800000
 800aef8:	0800bd64 	.word	0x0800bd64

0800aefc <atanf>:
 800aefc:	b538      	push	{r3, r4, r5, lr}
 800aefe:	ee10 5a10 	vmov	r5, s0
 800af02:	f025 4400 	bic.w	r4, r5, #2147483648	@ 0x80000000
 800af06:	f1b4 4fa1 	cmp.w	r4, #1350565888	@ 0x50800000
 800af0a:	eef0 7a40 	vmov.f32	s15, s0
 800af0e:	d310      	bcc.n	800af32 <atanf+0x36>
 800af10:	f1b4 4fff 	cmp.w	r4, #2139095040	@ 0x7f800000
 800af14:	d904      	bls.n	800af20 <atanf+0x24>
 800af16:	ee70 7a00 	vadd.f32	s15, s0, s0
 800af1a:	eeb0 0a67 	vmov.f32	s0, s15
 800af1e:	bd38      	pop	{r3, r4, r5, pc}
 800af20:	eddf 7a4d 	vldr	s15, [pc, #308]	@ 800b058 <atanf+0x15c>
 800af24:	ed9f 7a4d 	vldr	s14, [pc, #308]	@ 800b05c <atanf+0x160>
 800af28:	2d00      	cmp	r5, #0
 800af2a:	bfc8      	it	gt
 800af2c:	eef0 7a47 	vmovgt.f32	s15, s14
 800af30:	e7f3      	b.n	800af1a <atanf+0x1e>
 800af32:	4b4b      	ldr	r3, [pc, #300]	@ (800b060 <atanf+0x164>)
 800af34:	429c      	cmp	r4, r3
 800af36:	d810      	bhi.n	800af5a <atanf+0x5e>
 800af38:	f1b4 5f44 	cmp.w	r4, #822083584	@ 0x31000000
 800af3c:	d20a      	bcs.n	800af54 <atanf+0x58>
 800af3e:	ed9f 7a49 	vldr	s14, [pc, #292]	@ 800b064 <atanf+0x168>
 800af42:	ee30 7a07 	vadd.f32	s14, s0, s14
 800af46:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
 800af4a:	eeb4 7ae6 	vcmpe.f32	s14, s13
 800af4e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800af52:	dce2      	bgt.n	800af1a <atanf+0x1e>
 800af54:	f04f 33ff 	mov.w	r3, #4294967295
 800af58:	e013      	b.n	800af82 <atanf+0x86>
 800af5a:	f7ff f94b 	bl	800a1f4 <fabsf>
 800af5e:	4b42      	ldr	r3, [pc, #264]	@ (800b068 <atanf+0x16c>)
 800af60:	429c      	cmp	r4, r3
 800af62:	d84f      	bhi.n	800b004 <atanf+0x108>
 800af64:	f5a3 03d0 	sub.w	r3, r3, #6815744	@ 0x680000
 800af68:	429c      	cmp	r4, r3
 800af6a:	d841      	bhi.n	800aff0 <atanf+0xf4>
 800af6c:	eef0 7a00 	vmov.f32	s15, #0	@ 0x40000000  2.0
 800af70:	eebf 7a00 	vmov.f32	s14, #240	@ 0xbf800000 -1.0
 800af74:	eea0 7a27 	vfma.f32	s14, s0, s15
 800af78:	2300      	movs	r3, #0
 800af7a:	ee30 0a27 	vadd.f32	s0, s0, s15
 800af7e:	eec7 7a00 	vdiv.f32	s15, s14, s0
 800af82:	1c5a      	adds	r2, r3, #1
 800af84:	ee27 6aa7 	vmul.f32	s12, s15, s15
 800af88:	ed9f 7a38 	vldr	s14, [pc, #224]	@ 800b06c <atanf+0x170>
 800af8c:	eddf 5a38 	vldr	s11, [pc, #224]	@ 800b070 <atanf+0x174>
 800af90:	ed9f 5a38 	vldr	s10, [pc, #224]	@ 800b074 <atanf+0x178>
 800af94:	ee66 6a06 	vmul.f32	s13, s12, s12
 800af98:	eee6 5a87 	vfma.f32	s11, s13, s14
 800af9c:	ed9f 7a36 	vldr	s14, [pc, #216]	@ 800b078 <atanf+0x17c>
 800afa0:	eea5 7aa6 	vfma.f32	s14, s11, s13
 800afa4:	eddf 5a35 	vldr	s11, [pc, #212]	@ 800b07c <atanf+0x180>
 800afa8:	eee7 5a26 	vfma.f32	s11, s14, s13
 800afac:	ed9f 7a34 	vldr	s14, [pc, #208]	@ 800b080 <atanf+0x184>
 800afb0:	eea5 7aa6 	vfma.f32	s14, s11, s13
 800afb4:	eddf 5a33 	vldr	s11, [pc, #204]	@ 800b084 <atanf+0x188>
 800afb8:	eee7 5a26 	vfma.f32	s11, s14, s13
 800afbc:	ed9f 7a32 	vldr	s14, [pc, #200]	@ 800b088 <atanf+0x18c>
 800afc0:	eea6 5a87 	vfma.f32	s10, s13, s14
 800afc4:	ed9f 7a31 	vldr	s14, [pc, #196]	@ 800b08c <atanf+0x190>
 800afc8:	eea5 7a26 	vfma.f32	s14, s10, s13
 800afcc:	ed9f 5a30 	vldr	s10, [pc, #192]	@ 800b090 <atanf+0x194>
 800afd0:	eea7 5a26 	vfma.f32	s10, s14, s13
 800afd4:	ed9f 7a2f 	vldr	s14, [pc, #188]	@ 800b094 <atanf+0x198>
 800afd8:	eea5 7a26 	vfma.f32	s14, s10, s13
 800afdc:	ee27 7a26 	vmul.f32	s14, s14, s13
 800afe0:	eea5 7a86 	vfma.f32	s14, s11, s12
 800afe4:	ee27 7a87 	vmul.f32	s14, s15, s14
 800afe8:	d121      	bne.n	800b02e <atanf+0x132>
 800afea:	ee77 7ac7 	vsub.f32	s15, s15, s14
 800afee:	e794      	b.n	800af1a <atanf+0x1e>
 800aff0:	eef7 7a00 	vmov.f32	s15, #112	@ 0x3f800000  1.0
 800aff4:	ee30 7a67 	vsub.f32	s14, s0, s15
 800aff8:	ee30 0a27 	vadd.f32	s0, s0, s15
 800affc:	2301      	movs	r3, #1
 800affe:	eec7 7a00 	vdiv.f32	s15, s14, s0
 800b002:	e7be      	b.n	800af82 <atanf+0x86>
 800b004:	4b24      	ldr	r3, [pc, #144]	@ (800b098 <atanf+0x19c>)
 800b006:	429c      	cmp	r4, r3
 800b008:	d80b      	bhi.n	800b022 <atanf+0x126>
 800b00a:	eef7 7a08 	vmov.f32	s15, #120	@ 0x3fc00000  1.5
 800b00e:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
 800b012:	eea0 7a27 	vfma.f32	s14, s0, s15
 800b016:	2302      	movs	r3, #2
 800b018:	ee70 6a67 	vsub.f32	s13, s0, s15
 800b01c:	eec6 7a87 	vdiv.f32	s15, s13, s14
 800b020:	e7af      	b.n	800af82 <atanf+0x86>
 800b022:	eebf 7a00 	vmov.f32	s14, #240	@ 0xbf800000 -1.0
 800b026:	eec7 7a00 	vdiv.f32	s15, s14, s0
 800b02a:	2303      	movs	r3, #3
 800b02c:	e7a9      	b.n	800af82 <atanf+0x86>
 800b02e:	4a1b      	ldr	r2, [pc, #108]	@ (800b09c <atanf+0x1a0>)
 800b030:	491b      	ldr	r1, [pc, #108]	@ (800b0a0 <atanf+0x1a4>)
 800b032:	eb02 0283 	add.w	r2, r2, r3, lsl #2
 800b036:	eb01 0383 	add.w	r3, r1, r3, lsl #2
 800b03a:	edd3 6a00 	vldr	s13, [r3]
 800b03e:	ee37 7a66 	vsub.f32	s14, s14, s13
 800b042:	2d00      	cmp	r5, #0
 800b044:	ee37 7a67 	vsub.f32	s14, s14, s15
 800b048:	edd2 7a00 	vldr	s15, [r2]
 800b04c:	ee77 7ac7 	vsub.f32	s15, s15, s14
 800b050:	bfb8      	it	lt
 800b052:	eef1 7a67 	vneglt.f32	s15, s15
 800b056:	e760      	b.n	800af1a <atanf+0x1e>
 800b058:	bfc90fdb 	.word	0xbfc90fdb
 800b05c:	3fc90fdb 	.word	0x3fc90fdb
 800b060:	3edfffff 	.word	0x3edfffff
 800b064:	7149f2ca 	.word	0x7149f2ca
 800b068:	3f97ffff 	.word	0x3f97ffff
 800b06c:	3c8569d7 	.word	0x3c8569d7
 800b070:	3d4bda59 	.word	0x3d4bda59
 800b074:	bd6ef16b 	.word	0xbd6ef16b
 800b078:	3d886b35 	.word	0x3d886b35
 800b07c:	3dba2e6e 	.word	0x3dba2e6e
 800b080:	3e124925 	.word	0x3e124925
 800b084:	3eaaaaab 	.word	0x3eaaaaab
 800b088:	bd15a221 	.word	0xbd15a221
 800b08c:	bd9d8795 	.word	0xbd9d8795
 800b090:	bde38e38 	.word	0xbde38e38
 800b094:	be4ccccd 	.word	0xbe4ccccd
 800b098:	401bffff 	.word	0x401bffff
 800b09c:	0800c08c 	.word	0x0800c08c
 800b0a0:	0800c07c 	.word	0x0800c07c

0800b0a4 <scalbnf>:
 800b0a4:	ee10 3a10 	vmov	r3, s0
 800b0a8:	f033 4200 	bics.w	r2, r3, #2147483648	@ 0x80000000
 800b0ac:	d02b      	beq.n	800b106 <scalbnf+0x62>
 800b0ae:	f1b2 4fff 	cmp.w	r2, #2139095040	@ 0x7f800000
 800b0b2:	d302      	bcc.n	800b0ba <scalbnf+0x16>
 800b0b4:	ee30 0a00 	vadd.f32	s0, s0, s0
 800b0b8:	4770      	bx	lr
 800b0ba:	f013 4fff 	tst.w	r3, #2139095040	@ 0x7f800000
 800b0be:	d123      	bne.n	800b108 <scalbnf+0x64>
 800b0c0:	4b24      	ldr	r3, [pc, #144]	@ (800b154 <scalbnf+0xb0>)
 800b0c2:	eddf 7a25 	vldr	s15, [pc, #148]	@ 800b158 <scalbnf+0xb4>
 800b0c6:	4298      	cmp	r0, r3
 800b0c8:	ee20 0a27 	vmul.f32	s0, s0, s15
 800b0cc:	db17      	blt.n	800b0fe <scalbnf+0x5a>
 800b0ce:	ee10 3a10 	vmov	r3, s0
 800b0d2:	f3c3 52c7 	ubfx	r2, r3, #23, #8
 800b0d6:	3a19      	subs	r2, #25
 800b0d8:	f24c 3150 	movw	r1, #50000	@ 0xc350
 800b0dc:	4288      	cmp	r0, r1
 800b0de:	dd15      	ble.n	800b10c <scalbnf+0x68>
 800b0e0:	eddf 7a1e 	vldr	s15, [pc, #120]	@ 800b15c <scalbnf+0xb8>
 800b0e4:	eddf 6a1e 	vldr	s13, [pc, #120]	@ 800b160 <scalbnf+0xbc>
 800b0e8:	ee10 3a10 	vmov	r3, s0
 800b0ec:	eeb0 7a67 	vmov.f32	s14, s15
 800b0f0:	2b00      	cmp	r3, #0
 800b0f2:	bfb8      	it	lt
 800b0f4:	eef0 7a66 	vmovlt.f32	s15, s13
 800b0f8:	ee27 0a87 	vmul.f32	s0, s15, s14
 800b0fc:	4770      	bx	lr
 800b0fe:	eddf 7a19 	vldr	s15, [pc, #100]	@ 800b164 <scalbnf+0xc0>
 800b102:	ee27 0a80 	vmul.f32	s0, s15, s0
 800b106:	4770      	bx	lr
 800b108:	0dd2      	lsrs	r2, r2, #23
 800b10a:	e7e5      	b.n	800b0d8 <scalbnf+0x34>
 800b10c:	4410      	add	r0, r2
 800b10e:	28fe      	cmp	r0, #254	@ 0xfe
 800b110:	dce6      	bgt.n	800b0e0 <scalbnf+0x3c>
 800b112:	2800      	cmp	r0, #0
 800b114:	dd06      	ble.n	800b124 <scalbnf+0x80>
 800b116:	f023 43ff 	bic.w	r3, r3, #2139095040	@ 0x7f800000
 800b11a:	ea43 53c0 	orr.w	r3, r3, r0, lsl #23
 800b11e:	ee00 3a10 	vmov	s0, r3
 800b122:	4770      	bx	lr
 800b124:	f110 0f16 	cmn.w	r0, #22
 800b128:	da09      	bge.n	800b13e <scalbnf+0x9a>
 800b12a:	eddf 7a0e 	vldr	s15, [pc, #56]	@ 800b164 <scalbnf+0xc0>
 800b12e:	eddf 6a0e 	vldr	s13, [pc, #56]	@ 800b168 <scalbnf+0xc4>
 800b132:	ee10 3a10 	vmov	r3, s0
 800b136:	eeb0 7a67 	vmov.f32	s14, s15
 800b13a:	2b00      	cmp	r3, #0
 800b13c:	e7d9      	b.n	800b0f2 <scalbnf+0x4e>
 800b13e:	3019      	adds	r0, #25
 800b140:	f023 43ff 	bic.w	r3, r3, #2139095040	@ 0x7f800000
 800b144:	ea43 53c0 	orr.w	r3, r3, r0, lsl #23
 800b148:	ed9f 0a08 	vldr	s0, [pc, #32]	@ 800b16c <scalbnf+0xc8>
 800b14c:	ee07 3a90 	vmov	s15, r3
 800b150:	e7d7      	b.n	800b102 <scalbnf+0x5e>
 800b152:	bf00      	nop
 800b154:	ffff3cb0 	.word	0xffff3cb0
 800b158:	4c000000 	.word	0x4c000000
 800b15c:	7149f2ca 	.word	0x7149f2ca
 800b160:	f149f2ca 	.word	0xf149f2ca
 800b164:	0da24260 	.word	0x0da24260
 800b168:	8da24260 	.word	0x8da24260
 800b16c:	33000000 	.word	0x33000000

0800b170 <with_errnof>:
 800b170:	b510      	push	{r4, lr}
 800b172:	ed2d 8b02 	vpush	{d8}
 800b176:	eeb0 8a40 	vmov.f32	s16, s0
 800b17a:	4604      	mov	r4, r0
 800b17c:	f7fc ff1a 	bl	8007fb4 <__errno>
 800b180:	eeb0 0a48 	vmov.f32	s0, s16
 800b184:	ecbd 8b02 	vpop	{d8}
 800b188:	6004      	str	r4, [r0, #0]
 800b18a:	bd10      	pop	{r4, pc}

0800b18c <xflowf>:
 800b18c:	b130      	cbz	r0, 800b19c <xflowf+0x10>
 800b18e:	eef1 7a40 	vneg.f32	s15, s0
 800b192:	ee27 0a80 	vmul.f32	s0, s15, s0
 800b196:	2022      	movs	r0, #34	@ 0x22
 800b198:	f7ff bfea 	b.w	800b170 <with_errnof>
 800b19c:	eef0 7a40 	vmov.f32	s15, s0
 800b1a0:	e7f7      	b.n	800b192 <xflowf+0x6>
	...

0800b1a4 <__math_uflowf>:
 800b1a4:	ed9f 0a01 	vldr	s0, [pc, #4]	@ 800b1ac <__math_uflowf+0x8>
 800b1a8:	f7ff bff0 	b.w	800b18c <xflowf>
 800b1ac:	10000000 	.word	0x10000000

0800b1b0 <__math_oflowf>:
 800b1b0:	ed9f 0a01 	vldr	s0, [pc, #4]	@ 800b1b8 <__math_oflowf+0x8>
 800b1b4:	f7ff bfea 	b.w	800b18c <xflowf>
 800b1b8:	70000000 	.word	0x70000000

0800b1bc <__kernel_rem_pio2f>:
 800b1bc:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 800b1c0:	ed2d 8b04 	vpush	{d8-d9}
 800b1c4:	b0d9      	sub	sp, #356	@ 0x164
 800b1c6:	4690      	mov	r8, r2
 800b1c8:	9001      	str	r0, [sp, #4]
 800b1ca:	4ab6      	ldr	r2, [pc, #728]	@ (800b4a4 <__kernel_rem_pio2f+0x2e8>)
 800b1cc:	9866      	ldr	r0, [sp, #408]	@ 0x198
 800b1ce:	f118 0f04 	cmn.w	r8, #4
 800b1d2:	f852 a020 	ldr.w	sl, [r2, r0, lsl #2]
 800b1d6:	460f      	mov	r7, r1
 800b1d8:	f103 3bff 	add.w	fp, r3, #4294967295
 800b1dc:	db26      	blt.n	800b22c <__kernel_rem_pio2f+0x70>
 800b1de:	f1b8 0203 	subs.w	r2, r8, #3
 800b1e2:	bf48      	it	mi
 800b1e4:	f108 0204 	addmi.w	r2, r8, #4
 800b1e8:	10d2      	asrs	r2, r2, #3
 800b1ea:	1c55      	adds	r5, r2, #1
 800b1ec:	9967      	ldr	r1, [sp, #412]	@ 0x19c
 800b1ee:	ed9f 7ab1 	vldr	s14, [pc, #708]	@ 800b4b4 <__kernel_rem_pio2f+0x2f8>
 800b1f2:	00e8      	lsls	r0, r5, #3
 800b1f4:	eba2 060b 	sub.w	r6, r2, fp
 800b1f8:	9002      	str	r0, [sp, #8]
 800b1fa:	eba8 05c5 	sub.w	r5, r8, r5, lsl #3
 800b1fe:	eb0a 0c0b 	add.w	ip, sl, fp
 800b202:	ac1c      	add	r4, sp, #112	@ 0x70
 800b204:	eb01 0e86 	add.w	lr, r1, r6, lsl #2
 800b208:	2000      	movs	r0, #0
 800b20a:	4560      	cmp	r0, ip
 800b20c:	dd10      	ble.n	800b230 <__kernel_rem_pio2f+0x74>
 800b20e:	a91c      	add	r1, sp, #112	@ 0x70
 800b210:	eb01 0083 	add.w	r0, r1, r3, lsl #2
 800b214:	f50d 7988 	add.w	r9, sp, #272	@ 0x110
 800b218:	2600      	movs	r6, #0
 800b21a:	4556      	cmp	r6, sl
 800b21c:	dc24      	bgt.n	800b268 <__kernel_rem_pio2f+0xac>
 800b21e:	f8dd e004 	ldr.w	lr, [sp, #4]
 800b222:	eddf 7aa4 	vldr	s15, [pc, #656]	@ 800b4b4 <__kernel_rem_pio2f+0x2f8>
 800b226:	4684      	mov	ip, r0
 800b228:	2400      	movs	r4, #0
 800b22a:	e016      	b.n	800b25a <__kernel_rem_pio2f+0x9e>
 800b22c:	2200      	movs	r2, #0
 800b22e:	e7dc      	b.n	800b1ea <__kernel_rem_pio2f+0x2e>
 800b230:	42c6      	cmn	r6, r0
 800b232:	bf5d      	ittte	pl
 800b234:	f85e 1020 	ldrpl.w	r1, [lr, r0, lsl #2]
 800b238:	ee07 1a90 	vmovpl	s15, r1
 800b23c:	eef8 7ae7 	vcvtpl.f32.s32	s15, s15
 800b240:	eef0 7a47 	vmovmi.f32	s15, s14
 800b244:	ece4 7a01 	vstmia	r4!, {s15}
 800b248:	3001      	adds	r0, #1
 800b24a:	e7de      	b.n	800b20a <__kernel_rem_pio2f+0x4e>
 800b24c:	ecfe 6a01 	vldmia	lr!, {s13}
 800b250:	ed3c 7a01 	vldmdb	ip!, {s14}
 800b254:	eee6 7a87 	vfma.f32	s15, s13, s14
 800b258:	3401      	adds	r4, #1
 800b25a:	455c      	cmp	r4, fp
 800b25c:	ddf6      	ble.n	800b24c <__kernel_rem_pio2f+0x90>
 800b25e:	ece9 7a01 	vstmia	r9!, {s15}
 800b262:	3601      	adds	r6, #1
 800b264:	3004      	adds	r0, #4
 800b266:	e7d8      	b.n	800b21a <__kernel_rem_pio2f+0x5e>
 800b268:	a908      	add	r1, sp, #32
 800b26a:	eb01 018a 	add.w	r1, r1, sl, lsl #2
 800b26e:	9104      	str	r1, [sp, #16]
 800b270:	9967      	ldr	r1, [sp, #412]	@ 0x19c
 800b272:	eddf 8a8f 	vldr	s17, [pc, #572]	@ 800b4b0 <__kernel_rem_pio2f+0x2f4>
 800b276:	ed9f 9a8d 	vldr	s18, [pc, #564]	@ 800b4ac <__kernel_rem_pio2f+0x2f0>
 800b27a:	eb01 0282 	add.w	r2, r1, r2, lsl #2
 800b27e:	9203      	str	r2, [sp, #12]
 800b280:	4654      	mov	r4, sl
 800b282:	00a2      	lsls	r2, r4, #2
 800b284:	9205      	str	r2, [sp, #20]
 800b286:	aa58      	add	r2, sp, #352	@ 0x160
 800b288:	eb02 0284 	add.w	r2, r2, r4, lsl #2
 800b28c:	ed12 0a14 	vldr	s0, [r2, #-80]	@ 0xffffffb0
 800b290:	a944      	add	r1, sp, #272	@ 0x110
 800b292:	aa08      	add	r2, sp, #32
 800b294:	eb01 0084 	add.w	r0, r1, r4, lsl #2
 800b298:	4694      	mov	ip, r2
 800b29a:	4626      	mov	r6, r4
 800b29c:	2e00      	cmp	r6, #0
 800b29e:	dc4c      	bgt.n	800b33a <__kernel_rem_pio2f+0x17e>
 800b2a0:	4628      	mov	r0, r5
 800b2a2:	e9cd 2306 	strd	r2, r3, [sp, #24]
 800b2a6:	f7ff fefd 	bl	800b0a4 <scalbnf>
 800b2aa:	eeb0 8a40 	vmov.f32	s16, s0
 800b2ae:	eeb4 0a00 	vmov.f32	s0, #64	@ 0x3e000000  0.125
 800b2b2:	ee28 0a00 	vmul.f32	s0, s16, s0
 800b2b6:	f000 f9e9 	bl	800b68c <floorf>
 800b2ba:	eef2 7a00 	vmov.f32	s15, #32	@ 0x41000000  8.0
 800b2be:	eea0 8a67 	vfms.f32	s16, s0, s15
 800b2c2:	2d00      	cmp	r5, #0
 800b2c4:	e9dd 2306 	ldrd	r2, r3, [sp, #24]
 800b2c8:	eefd 7ac8 	vcvt.s32.f32	s15, s16
 800b2cc:	ee17 9a90 	vmov	r9, s15
 800b2d0:	eef8 7ae7 	vcvt.f32.s32	s15, s15
 800b2d4:	ee38 8a67 	vsub.f32	s16, s16, s15
 800b2d8:	dd41      	ble.n	800b35e <__kernel_rem_pio2f+0x1a2>
 800b2da:	f104 3cff 	add.w	ip, r4, #4294967295
 800b2de:	a908      	add	r1, sp, #32
 800b2e0:	f1c5 0e08 	rsb	lr, r5, #8
 800b2e4:	f851 602c 	ldr.w	r6, [r1, ip, lsl #2]
 800b2e8:	fa46 f00e 	asr.w	r0, r6, lr
 800b2ec:	4481      	add	r9, r0
 800b2ee:	fa00 f00e 	lsl.w	r0, r0, lr
 800b2f2:	1a36      	subs	r6, r6, r0
 800b2f4:	f1c5 0007 	rsb	r0, r5, #7
 800b2f8:	f841 602c 	str.w	r6, [r1, ip, lsl #2]
 800b2fc:	4106      	asrs	r6, r0
 800b2fe:	2e00      	cmp	r6, #0
 800b300:	dd3c      	ble.n	800b37c <__kernel_rem_pio2f+0x1c0>
 800b302:	f04f 0e00 	mov.w	lr, #0
 800b306:	f109 0901 	add.w	r9, r9, #1
 800b30a:	4670      	mov	r0, lr
 800b30c:	4574      	cmp	r4, lr
 800b30e:	dc68      	bgt.n	800b3e2 <__kernel_rem_pio2f+0x226>
 800b310:	2d00      	cmp	r5, #0
 800b312:	dd03      	ble.n	800b31c <__kernel_rem_pio2f+0x160>
 800b314:	2d01      	cmp	r5, #1
 800b316:	d074      	beq.n	800b402 <__kernel_rem_pio2f+0x246>
 800b318:	2d02      	cmp	r5, #2
 800b31a:	d07d      	beq.n	800b418 <__kernel_rem_pio2f+0x25c>
 800b31c:	2e02      	cmp	r6, #2
 800b31e:	d12d      	bne.n	800b37c <__kernel_rem_pio2f+0x1c0>
 800b320:	eeb7 0a00 	vmov.f32	s0, #112	@ 0x3f800000  1.0
 800b324:	ee30 8a48 	vsub.f32	s16, s0, s16
 800b328:	b340      	cbz	r0, 800b37c <__kernel_rem_pio2f+0x1c0>
 800b32a:	4628      	mov	r0, r5
 800b32c:	9306      	str	r3, [sp, #24]
 800b32e:	f7ff feb9 	bl	800b0a4 <scalbnf>
 800b332:	9b06      	ldr	r3, [sp, #24]
 800b334:	ee38 8a40 	vsub.f32	s16, s16, s0
 800b338:	e020      	b.n	800b37c <__kernel_rem_pio2f+0x1c0>
 800b33a:	ee60 7a28 	vmul.f32	s15, s0, s17
 800b33e:	3e01      	subs	r6, #1
 800b340:	eefd 7ae7 	vcvt.s32.f32	s15, s15
 800b344:	eef8 7ae7 	vcvt.f32.s32	s15, s15
 800b348:	eea7 0ac9 	vfms.f32	s0, s15, s18
 800b34c:	eebd 0ac0 	vcvt.s32.f32	s0, s0
 800b350:	ecac 0a01 	vstmia	ip!, {s0}
 800b354:	ed30 0a01 	vldmdb	r0!, {s0}
 800b358:	ee37 0a80 	vadd.f32	s0, s15, s0
 800b35c:	e79e      	b.n	800b29c <__kernel_rem_pio2f+0xe0>
 800b35e:	d105      	bne.n	800b36c <__kernel_rem_pio2f+0x1b0>
 800b360:	1e60      	subs	r0, r4, #1
 800b362:	a908      	add	r1, sp, #32
 800b364:	f851 6020 	ldr.w	r6, [r1, r0, lsl #2]
 800b368:	11f6      	asrs	r6, r6, #7
 800b36a:	e7c8      	b.n	800b2fe <__kernel_rem_pio2f+0x142>
 800b36c:	eef6 7a00 	vmov.f32	s15, #96	@ 0x3f000000  0.5
 800b370:	eeb4 8ae7 	vcmpe.f32	s16, s15
 800b374:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800b378:	da31      	bge.n	800b3de <__kernel_rem_pio2f+0x222>
 800b37a:	2600      	movs	r6, #0
 800b37c:	eeb5 8a40 	vcmp.f32	s16, #0.0
 800b380:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800b384:	f040 8098 	bne.w	800b4b8 <__kernel_rem_pio2f+0x2fc>
 800b388:	1e60      	subs	r0, r4, #1
 800b38a:	2200      	movs	r2, #0
 800b38c:	4550      	cmp	r0, sl
 800b38e:	da4b      	bge.n	800b428 <__kernel_rem_pio2f+0x26c>
 800b390:	2a00      	cmp	r2, #0
 800b392:	d065      	beq.n	800b460 <__kernel_rem_pio2f+0x2a4>
 800b394:	3c01      	subs	r4, #1
 800b396:	ab08      	add	r3, sp, #32
 800b398:	3d08      	subs	r5, #8
 800b39a:	f853 3024 	ldr.w	r3, [r3, r4, lsl #2]
 800b39e:	2b00      	cmp	r3, #0
 800b3a0:	d0f8      	beq.n	800b394 <__kernel_rem_pio2f+0x1d8>
 800b3a2:	4628      	mov	r0, r5
 800b3a4:	eeb7 0a00 	vmov.f32	s0, #112	@ 0x3f800000  1.0
 800b3a8:	f7ff fe7c 	bl	800b0a4 <scalbnf>
 800b3ac:	1c63      	adds	r3, r4, #1
 800b3ae:	aa44      	add	r2, sp, #272	@ 0x110
 800b3b0:	ed9f 7a3f 	vldr	s14, [pc, #252]	@ 800b4b0 <__kernel_rem_pio2f+0x2f4>
 800b3b4:	0099      	lsls	r1, r3, #2
 800b3b6:	eb02 0283 	add.w	r2, r2, r3, lsl #2
 800b3ba:	4623      	mov	r3, r4
 800b3bc:	2b00      	cmp	r3, #0
 800b3be:	f280 80a9 	bge.w	800b514 <__kernel_rem_pio2f+0x358>
 800b3c2:	4623      	mov	r3, r4
 800b3c4:	2b00      	cmp	r3, #0
 800b3c6:	f2c0 80c7 	blt.w	800b558 <__kernel_rem_pio2f+0x39c>
 800b3ca:	aa44      	add	r2, sp, #272	@ 0x110
 800b3cc:	eb02 0583 	add.w	r5, r2, r3, lsl #2
 800b3d0:	f8df c0d4 	ldr.w	ip, [pc, #212]	@ 800b4a8 <__kernel_rem_pio2f+0x2ec>
 800b3d4:	eddf 7a37 	vldr	s15, [pc, #220]	@ 800b4b4 <__kernel_rem_pio2f+0x2f8>
 800b3d8:	2000      	movs	r0, #0
 800b3da:	1ae2      	subs	r2, r4, r3
 800b3dc:	e0b1      	b.n	800b542 <__kernel_rem_pio2f+0x386>
 800b3de:	2602      	movs	r6, #2
 800b3e0:	e78f      	b.n	800b302 <__kernel_rem_pio2f+0x146>
 800b3e2:	f852 1b04 	ldr.w	r1, [r2], #4
 800b3e6:	b948      	cbnz	r0, 800b3fc <__kernel_rem_pio2f+0x240>
 800b3e8:	b121      	cbz	r1, 800b3f4 <__kernel_rem_pio2f+0x238>
 800b3ea:	f5c1 7180 	rsb	r1, r1, #256	@ 0x100
 800b3ee:	f842 1c04 	str.w	r1, [r2, #-4]
 800b3f2:	2101      	movs	r1, #1
 800b3f4:	f10e 0e01 	add.w	lr, lr, #1
 800b3f8:	4608      	mov	r0, r1
 800b3fa:	e787      	b.n	800b30c <__kernel_rem_pio2f+0x150>
 800b3fc:	f1c1 01ff 	rsb	r1, r1, #255	@ 0xff
 800b400:	e7f5      	b.n	800b3ee <__kernel_rem_pio2f+0x232>
 800b402:	f104 3cff 	add.w	ip, r4, #4294967295
 800b406:	aa08      	add	r2, sp, #32
 800b408:	f852 202c 	ldr.w	r2, [r2, ip, lsl #2]
 800b40c:	f002 027f 	and.w	r2, r2, #127	@ 0x7f
 800b410:	a908      	add	r1, sp, #32
 800b412:	f841 202c 	str.w	r2, [r1, ip, lsl #2]
 800b416:	e781      	b.n	800b31c <__kernel_rem_pio2f+0x160>
 800b418:	f104 3cff 	add.w	ip, r4, #4294967295
 800b41c:	aa08      	add	r2, sp, #32
 800b41e:	f852 202c 	ldr.w	r2, [r2, ip, lsl #2]
 800b422:	f002 023f 	and.w	r2, r2, #63	@ 0x3f
 800b426:	e7f3      	b.n	800b410 <__kernel_rem_pio2f+0x254>
 800b428:	a908      	add	r1, sp, #32
 800b42a:	f851 1020 	ldr.w	r1, [r1, r0, lsl #2]
 800b42e:	3801      	subs	r0, #1
 800b430:	430a      	orrs	r2, r1
 800b432:	e7ab      	b.n	800b38c <__kernel_rem_pio2f+0x1d0>
 800b434:	3201      	adds	r2, #1
 800b436:	f850 6d04 	ldr.w	r6, [r0, #-4]!
 800b43a:	2e00      	cmp	r6, #0
 800b43c:	d0fa      	beq.n	800b434 <__kernel_rem_pio2f+0x278>
 800b43e:	9905      	ldr	r1, [sp, #20]
 800b440:	f501 71b0 	add.w	r1, r1, #352	@ 0x160
 800b444:	eb0d 0001 	add.w	r0, sp, r1
 800b448:	18e6      	adds	r6, r4, r3
 800b44a:	a91c      	add	r1, sp, #112	@ 0x70
 800b44c:	f104 0c01 	add.w	ip, r4, #1
 800b450:	384c      	subs	r0, #76	@ 0x4c
 800b452:	eb01 0686 	add.w	r6, r1, r6, lsl #2
 800b456:	4422      	add	r2, r4
 800b458:	4562      	cmp	r2, ip
 800b45a:	da04      	bge.n	800b466 <__kernel_rem_pio2f+0x2aa>
 800b45c:	4614      	mov	r4, r2
 800b45e:	e710      	b.n	800b282 <__kernel_rem_pio2f+0xc6>
 800b460:	9804      	ldr	r0, [sp, #16]
 800b462:	2201      	movs	r2, #1
 800b464:	e7e7      	b.n	800b436 <__kernel_rem_pio2f+0x27a>
 800b466:	9903      	ldr	r1, [sp, #12]
 800b468:	f8dd e004 	ldr.w	lr, [sp, #4]
 800b46c:	f851 102c 	ldr.w	r1, [r1, ip, lsl #2]
 800b470:	9105      	str	r1, [sp, #20]
 800b472:	ee07 1a90 	vmov	s15, r1
 800b476:	eef8 7ae7 	vcvt.f32.s32	s15, s15
 800b47a:	2400      	movs	r4, #0
 800b47c:	ece6 7a01 	vstmia	r6!, {s15}
 800b480:	eddf 7a0c 	vldr	s15, [pc, #48]	@ 800b4b4 <__kernel_rem_pio2f+0x2f8>
 800b484:	46b1      	mov	r9, r6
 800b486:	455c      	cmp	r4, fp
 800b488:	dd04      	ble.n	800b494 <__kernel_rem_pio2f+0x2d8>
 800b48a:	ece0 7a01 	vstmia	r0!, {s15}
 800b48e:	f10c 0c01 	add.w	ip, ip, #1
 800b492:	e7e1      	b.n	800b458 <__kernel_rem_pio2f+0x29c>
 800b494:	ecfe 6a01 	vldmia	lr!, {s13}
 800b498:	ed39 7a01 	vldmdb	r9!, {s14}
 800b49c:	3401      	adds	r4, #1
 800b49e:	eee6 7a87 	vfma.f32	s15, s13, s14
 800b4a2:	e7f0      	b.n	800b486 <__kernel_rem_pio2f+0x2ca>
 800b4a4:	0800c0c8 	.word	0x0800c0c8
 800b4a8:	0800c09c 	.word	0x0800c09c
 800b4ac:	43800000 	.word	0x43800000
 800b4b0:	3b800000 	.word	0x3b800000
 800b4b4:	00000000 	.word	0x00000000
 800b4b8:	9b02      	ldr	r3, [sp, #8]
 800b4ba:	eeb0 0a48 	vmov.f32	s0, s16
 800b4be:	eba3 0008 	sub.w	r0, r3, r8
 800b4c2:	f7ff fdef 	bl	800b0a4 <scalbnf>
 800b4c6:	ed1f 7a07 	vldr	s14, [pc, #-28]	@ 800b4ac <__kernel_rem_pio2f+0x2f0>
 800b4ca:	eeb4 0ac7 	vcmpe.f32	s0, s14
 800b4ce:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800b4d2:	db19      	blt.n	800b508 <__kernel_rem_pio2f+0x34c>
 800b4d4:	ed5f 7a0a 	vldr	s15, [pc, #-40]	@ 800b4b0 <__kernel_rem_pio2f+0x2f4>
 800b4d8:	ee60 7a27 	vmul.f32	s15, s0, s15
 800b4dc:	aa08      	add	r2, sp, #32
 800b4de:	eefd 7ae7 	vcvt.s32.f32	s15, s15
 800b4e2:	3508      	adds	r5, #8
 800b4e4:	eef8 7ae7 	vcvt.f32.s32	s15, s15
 800b4e8:	eea7 0ac7 	vfms.f32	s0, s15, s14
 800b4ec:	eefd 7ae7 	vcvt.s32.f32	s15, s15
 800b4f0:	eebd 0ac0 	vcvt.s32.f32	s0, s0
 800b4f4:	ee10 3a10 	vmov	r3, s0
 800b4f8:	f842 3024 	str.w	r3, [r2, r4, lsl #2]
 800b4fc:	ee17 3a90 	vmov	r3, s15
 800b500:	3401      	adds	r4, #1
 800b502:	f842 3024 	str.w	r3, [r2, r4, lsl #2]
 800b506:	e74c      	b.n	800b3a2 <__kernel_rem_pio2f+0x1e6>
 800b508:	eebd 0ac0 	vcvt.s32.f32	s0, s0
 800b50c:	aa08      	add	r2, sp, #32
 800b50e:	ee10 3a10 	vmov	r3, s0
 800b512:	e7f6      	b.n	800b502 <__kernel_rem_pio2f+0x346>
 800b514:	a808      	add	r0, sp, #32
 800b516:	f850 0023 	ldr.w	r0, [r0, r3, lsl #2]
 800b51a:	9001      	str	r0, [sp, #4]
 800b51c:	ee07 0a90 	vmov	s15, r0
 800b520:	eef8 7ae7 	vcvt.f32.s32	s15, s15
 800b524:	3b01      	subs	r3, #1
 800b526:	ee67 7a80 	vmul.f32	s15, s15, s0
 800b52a:	ee20 0a07 	vmul.f32	s0, s0, s14
 800b52e:	ed62 7a01 	vstmdb	r2!, {s15}
 800b532:	e743      	b.n	800b3bc <__kernel_rem_pio2f+0x200>
 800b534:	ecfc 6a01 	vldmia	ip!, {s13}
 800b538:	ecb5 7a01 	vldmia	r5!, {s14}
 800b53c:	eee6 7a87 	vfma.f32	s15, s13, s14
 800b540:	3001      	adds	r0, #1
 800b542:	4550      	cmp	r0, sl
 800b544:	dc01      	bgt.n	800b54a <__kernel_rem_pio2f+0x38e>
 800b546:	4290      	cmp	r0, r2
 800b548:	ddf4      	ble.n	800b534 <__kernel_rem_pio2f+0x378>
 800b54a:	a858      	add	r0, sp, #352	@ 0x160
 800b54c:	eb00 0282 	add.w	r2, r0, r2, lsl #2
 800b550:	ed42 7a28 	vstr	s15, [r2, #-160]	@ 0xffffff60
 800b554:	3b01      	subs	r3, #1
 800b556:	e735      	b.n	800b3c4 <__kernel_rem_pio2f+0x208>
 800b558:	9b66      	ldr	r3, [sp, #408]	@ 0x198
 800b55a:	2b02      	cmp	r3, #2
 800b55c:	dc09      	bgt.n	800b572 <__kernel_rem_pio2f+0x3b6>
 800b55e:	2b00      	cmp	r3, #0
 800b560:	dc27      	bgt.n	800b5b2 <__kernel_rem_pio2f+0x3f6>
 800b562:	d040      	beq.n	800b5e6 <__kernel_rem_pio2f+0x42a>
 800b564:	f009 0007 	and.w	r0, r9, #7
 800b568:	b059      	add	sp, #356	@ 0x164
 800b56a:	ecbd 8b04 	vpop	{d8-d9}
 800b56e:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 800b572:	9b66      	ldr	r3, [sp, #408]	@ 0x198
 800b574:	2b03      	cmp	r3, #3
 800b576:	d1f5      	bne.n	800b564 <__kernel_rem_pio2f+0x3a8>
 800b578:	aa30      	add	r2, sp, #192	@ 0xc0
 800b57a:	1f0b      	subs	r3, r1, #4
 800b57c:	4413      	add	r3, r2
 800b57e:	461a      	mov	r2, r3
 800b580:	4620      	mov	r0, r4
 800b582:	2800      	cmp	r0, #0
 800b584:	dc50      	bgt.n	800b628 <__kernel_rem_pio2f+0x46c>
 800b586:	4622      	mov	r2, r4
 800b588:	2a01      	cmp	r2, #1
 800b58a:	dc5d      	bgt.n	800b648 <__kernel_rem_pio2f+0x48c>
 800b58c:	ab30      	add	r3, sp, #192	@ 0xc0
 800b58e:	ed5f 7a37 	vldr	s15, [pc, #-220]	@ 800b4b4 <__kernel_rem_pio2f+0x2f8>
 800b592:	440b      	add	r3, r1
 800b594:	2c01      	cmp	r4, #1
 800b596:	dc67      	bgt.n	800b668 <__kernel_rem_pio2f+0x4ac>
 800b598:	eddd 6a30 	vldr	s13, [sp, #192]	@ 0xc0
 800b59c:	ed9d 7a31 	vldr	s14, [sp, #196]	@ 0xc4
 800b5a0:	2e00      	cmp	r6, #0
 800b5a2:	d167      	bne.n	800b674 <__kernel_rem_pio2f+0x4b8>
 800b5a4:	edc7 6a00 	vstr	s13, [r7]
 800b5a8:	ed87 7a01 	vstr	s14, [r7, #4]
 800b5ac:	edc7 7a02 	vstr	s15, [r7, #8]
 800b5b0:	e7d8      	b.n	800b564 <__kernel_rem_pio2f+0x3a8>
 800b5b2:	ab30      	add	r3, sp, #192	@ 0xc0
 800b5b4:	ed1f 7a41 	vldr	s14, [pc, #-260]	@ 800b4b4 <__kernel_rem_pio2f+0x2f8>
 800b5b8:	440b      	add	r3, r1
 800b5ba:	4622      	mov	r2, r4
 800b5bc:	2a00      	cmp	r2, #0
 800b5be:	da24      	bge.n	800b60a <__kernel_rem_pio2f+0x44e>
 800b5c0:	b34e      	cbz	r6, 800b616 <__kernel_rem_pio2f+0x45a>
 800b5c2:	eef1 7a47 	vneg.f32	s15, s14
 800b5c6:	edc7 7a00 	vstr	s15, [r7]
 800b5ca:	eddd 7a30 	vldr	s15, [sp, #192]	@ 0xc0
 800b5ce:	ee77 7ac7 	vsub.f32	s15, s15, s14
 800b5d2:	aa31      	add	r2, sp, #196	@ 0xc4
 800b5d4:	2301      	movs	r3, #1
 800b5d6:	429c      	cmp	r4, r3
 800b5d8:	da20      	bge.n	800b61c <__kernel_rem_pio2f+0x460>
 800b5da:	b10e      	cbz	r6, 800b5e0 <__kernel_rem_pio2f+0x424>
 800b5dc:	eef1 7a67 	vneg.f32	s15, s15
 800b5e0:	edc7 7a01 	vstr	s15, [r7, #4]
 800b5e4:	e7be      	b.n	800b564 <__kernel_rem_pio2f+0x3a8>
 800b5e6:	ab30      	add	r3, sp, #192	@ 0xc0
 800b5e8:	ed5f 7a4e 	vldr	s15, [pc, #-312]	@ 800b4b4 <__kernel_rem_pio2f+0x2f8>
 800b5ec:	440b      	add	r3, r1
 800b5ee:	2c00      	cmp	r4, #0
 800b5f0:	da05      	bge.n	800b5fe <__kernel_rem_pio2f+0x442>
 800b5f2:	b10e      	cbz	r6, 800b5f8 <__kernel_rem_pio2f+0x43c>
 800b5f4:	eef1 7a67 	vneg.f32	s15, s15
 800b5f8:	edc7 7a00 	vstr	s15, [r7]
 800b5fc:	e7b2      	b.n	800b564 <__kernel_rem_pio2f+0x3a8>
 800b5fe:	ed33 7a01 	vldmdb	r3!, {s14}
 800b602:	3c01      	subs	r4, #1
 800b604:	ee77 7a87 	vadd.f32	s15, s15, s14
 800b608:	e7f1      	b.n	800b5ee <__kernel_rem_pio2f+0x432>
 800b60a:	ed73 7a01 	vldmdb	r3!, {s15}
 800b60e:	3a01      	subs	r2, #1
 800b610:	ee37 7a27 	vadd.f32	s14, s14, s15
 800b614:	e7d2      	b.n	800b5bc <__kernel_rem_pio2f+0x400>
 800b616:	eef0 7a47 	vmov.f32	s15, s14
 800b61a:	e7d4      	b.n	800b5c6 <__kernel_rem_pio2f+0x40a>
 800b61c:	ecb2 7a01 	vldmia	r2!, {s14}
 800b620:	3301      	adds	r3, #1
 800b622:	ee77 7a87 	vadd.f32	s15, s15, s14
 800b626:	e7d6      	b.n	800b5d6 <__kernel_rem_pio2f+0x41a>
 800b628:	ed72 7a01 	vldmdb	r2!, {s15}
 800b62c:	edd2 6a01 	vldr	s13, [r2, #4]
 800b630:	ee37 7aa6 	vadd.f32	s14, s15, s13
 800b634:	3801      	subs	r0, #1
 800b636:	ee77 7ac7 	vsub.f32	s15, s15, s14
 800b63a:	ed82 7a00 	vstr	s14, [r2]
 800b63e:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800b642:	edc2 7a01 	vstr	s15, [r2, #4]
 800b646:	e79c      	b.n	800b582 <__kernel_rem_pio2f+0x3c6>
 800b648:	ed73 7a01 	vldmdb	r3!, {s15}
 800b64c:	edd3 6a01 	vldr	s13, [r3, #4]
 800b650:	ee37 7aa6 	vadd.f32	s14, s15, s13
 800b654:	3a01      	subs	r2, #1
 800b656:	ee77 7ac7 	vsub.f32	s15, s15, s14
 800b65a:	ed83 7a00 	vstr	s14, [r3]
 800b65e:	ee77 7aa6 	vadd.f32	s15, s15, s13
 800b662:	edc3 7a01 	vstr	s15, [r3, #4]
 800b666:	e78f      	b.n	800b588 <__kernel_rem_pio2f+0x3cc>
 800b668:	ed33 7a01 	vldmdb	r3!, {s14}
 800b66c:	3c01      	subs	r4, #1
 800b66e:	ee77 7a87 	vadd.f32	s15, s15, s14
 800b672:	e78f      	b.n	800b594 <__kernel_rem_pio2f+0x3d8>
 800b674:	eef1 6a66 	vneg.f32	s13, s13
 800b678:	eeb1 7a47 	vneg.f32	s14, s14
 800b67c:	edc7 6a00 	vstr	s13, [r7]
 800b680:	ed87 7a01 	vstr	s14, [r7, #4]
 800b684:	eef1 7a67 	vneg.f32	s15, s15
 800b688:	e790      	b.n	800b5ac <__kernel_rem_pio2f+0x3f0>
 800b68a:	bf00      	nop

0800b68c <floorf>:
 800b68c:	ee10 3a10 	vmov	r3, s0
 800b690:	f3c3 52c7 	ubfx	r2, r3, #23, #8
 800b694:	3a7f      	subs	r2, #127	@ 0x7f
 800b696:	2a16      	cmp	r2, #22
 800b698:	f023 4100 	bic.w	r1, r3, #2147483648	@ 0x80000000
 800b69c:	dc2b      	bgt.n	800b6f6 <floorf+0x6a>
 800b69e:	2a00      	cmp	r2, #0
 800b6a0:	da12      	bge.n	800b6c8 <floorf+0x3c>
 800b6a2:	eddf 7a19 	vldr	s15, [pc, #100]	@ 800b708 <floorf+0x7c>
 800b6a6:	ee30 0a27 	vadd.f32	s0, s0, s15
 800b6aa:	eeb5 0ac0 	vcmpe.f32	s0, #0.0
 800b6ae:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800b6b2:	dd06      	ble.n	800b6c2 <floorf+0x36>
 800b6b4:	2b00      	cmp	r3, #0
 800b6b6:	da24      	bge.n	800b702 <floorf+0x76>
 800b6b8:	2900      	cmp	r1, #0
 800b6ba:	4b14      	ldr	r3, [pc, #80]	@ (800b70c <floorf+0x80>)
 800b6bc:	bf08      	it	eq
 800b6be:	f04f 4300 	moveq.w	r3, #2147483648	@ 0x80000000
 800b6c2:	ee00 3a10 	vmov	s0, r3
 800b6c6:	4770      	bx	lr
 800b6c8:	4911      	ldr	r1, [pc, #68]	@ (800b710 <floorf+0x84>)
 800b6ca:	4111      	asrs	r1, r2
 800b6cc:	420b      	tst	r3, r1
 800b6ce:	d0fa      	beq.n	800b6c6 <floorf+0x3a>
 800b6d0:	eddf 7a0d 	vldr	s15, [pc, #52]	@ 800b708 <floorf+0x7c>
 800b6d4:	ee30 0a27 	vadd.f32	s0, s0, s15
 800b6d8:	eeb5 0ac0 	vcmpe.f32	s0, #0.0
 800b6dc:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
 800b6e0:	ddef      	ble.n	800b6c2 <floorf+0x36>
 800b6e2:	2b00      	cmp	r3, #0
 800b6e4:	bfbe      	ittt	lt
 800b6e6:	f44f 0000 	movlt.w	r0, #8388608	@ 0x800000
 800b6ea:	fa40 f202 	asrlt.w	r2, r0, r2
 800b6ee:	189b      	addlt	r3, r3, r2
 800b6f0:	ea23 0301 	bic.w	r3, r3, r1
 800b6f4:	e7e5      	b.n	800b6c2 <floorf+0x36>
 800b6f6:	f1b1 4fff 	cmp.w	r1, #2139095040	@ 0x7f800000
 800b6fa:	d3e4      	bcc.n	800b6c6 <floorf+0x3a>
 800b6fc:	ee30 0a00 	vadd.f32	s0, s0, s0
 800b700:	4770      	bx	lr
 800b702:	2300      	movs	r3, #0
 800b704:	e7dd      	b.n	800b6c2 <floorf+0x36>
 800b706:	bf00      	nop
 800b708:	7149f2ca 	.word	0x7149f2ca
 800b70c:	bf800000 	.word	0xbf800000
 800b710:	007fffff 	.word	0x007fffff

0800b714 <_init>:
 800b714:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800b716:	bf00      	nop
 800b718:	bcf8      	pop	{r3, r4, r5, r6, r7}
 800b71a:	bc08      	pop	{r3}
 800b71c:	469e      	mov	lr, r3
 800b71e:	4770      	bx	lr

0800b720 <_fini>:
 800b720:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800b722:	bf00      	nop
 800b724:	bcf8      	pop	{r3, r4, r5, r6, r7}
 800b726:	bc08      	pop	{r3}
 800b728:	469e      	mov	lr, r3
 800b72a:	4770      	bx	lr